Search results for: sapphire wafer

Authors: Feng Wei, Lu Wenzhuang, Cai Wenjun, Yu Yaping, Basnet Rabin, Zuo Dunwen

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Diamond coatings were prepared on cemented carbide by hot filament chemical vapor deposition (HFCVD) method. Lapping experiment of single-crystal sapphire wafer was carried out using the prepared diamond coated tools. The diamond coatings and machined surface of the sapphire wafer were evaluated by SEM, laser confocal microscope and Raman spectrum. The results indicate that the lapping sapphire chips are small irregular debris and long thread-like debris. There is graphitization of diamond crystal during the lapping process. A low surface roughness can be obtained using a spherical grain diamond coated tool.

Keywords: lapping, nano-micro crystalline diamond coating, Raman spectrum, sapphire

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Authors: Qiao Pei Wen, Ng Seng Lee, Sae Tae Veera, Chiu Ah Fong, Loke Weng Onn

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Thin film thickness uniformity is crucial to get consistent film etch rate and device yield across the wafer. In the capacitive-coupled parallel plate PECVD system; the film thickness uniformity can be affected by many factors such as the heater temperature uniformity, the spacing between top and bottom electrode, RF power, pressure, gas flows and etc. In this paper, we studied how the PECVD SiN film thickness uniformity is affected by the substrate electrical conductivity and the RF power coupling efficiency. PECVD SiN film was deposited on 150-mm sapphire wafers in 200-mm Lam Sequel tool, fork marks were observed on the wafers. On the fork marks area SiN film thickness is thinner than that on the non-fork area. The forks are the wafer handler inside the process chamber to move the wafers from one station to another. The sapphire wafers and the ceramic forks both are insulator. The high resistivity of the sapphire wafers and the forks inhibits the RF power coupling efficiency during PECVD deposition, thereby reducing the deposition rate. Comparing between the high frequency and low frequency RF power (HFRF and LFRF respectively), the LFRF power coupling effect on the sapphire wafers is more dominant than the HFRF power on the film thickness. This paper demonstrated that the SiN thickness uniformity on sapphire wafers can be improved by depositing a thin TiW layer on the wafer before the SiN deposition. The TiW layer can be on the wafer surface, bottom or any layer before SiN deposition.

Keywords: PECVD SiN deposition, sapphire wafer, substrate electrical conductivity, RF power coupling, high frequency RF power, low frequency RF power, film deposition rate, thickness uniformity

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Authors: Anil Kawan, Soon Jae Yu, Jong Min Park

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GaN-based 365 nm wavelength ultraviolet (UV) light emitting diodes (LED) have various applications: curing, molding, purification, deodorization, and disinfection etc. However, their usage is limited by very low output power, because of the light absorption in the GaN layers. In this study, we demonstrate a method utilizing removal of 365 nm absorption layer buffer GaN and thinning the n-type GaN so as to improve the light extraction efficiency of the GaN-based 365 nm UV LED. The UV flip chip LEDs of chip size 1.3 mm x 1.3 mm were fabricated using GaN epilayers on a sapphire substrate. Via-hole n-type contacts and highly reflective Ag metal were used for efficient light extraction. LED wafer was aligned and bonded to AlN carrier wafer. To improve the extraction efficiency of the flip chip LED, sapphire substrate and absorption layer buffer GaN were removed by using laser lift-off and dry etching, respectively. To further increase the extraction efficiency of the LED, exposed n-type GaN thickness was reduced by using inductively coupled plasma etching.

Keywords: extraction efficiency, light emitting diodes, n-GaN thinning, ultraviolet

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Authors: Z. W. Zhong, C. Xu, W. K. Choi

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To build a thin fan-out wafer-level package, the package had to be ground to a thin level. In this work, the influence of the grinding processes on the strength of the fan-out wafer-level packages was investigated. After different grinding processes, all specimens were placed on a three-point-bending fixture installed on a universal tester for three-point-bending testing, and the strength of the fan-out wafer-level packages was measured. The experiments revealed that the average flexure strength increased with the decreasing surface roughness height of the fan-out wafer-level package tested. The grinding processes had a significant influence on the strength of the fan-out wafer-level packages investigated.

Keywords: FOWLP strength, surface roughness, three-point bending, grinding

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Authors: Mengjun Zhang, Yuli Sun, Dunwen Zuo, Chunxiang Xie, Chunming Zhang

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Experimental study on slicing of sapphire with fixed abrasive diamond wire saw was conducted in this paper. The process parameters were optimized through orthogonal experiment of three factors and four levels. The effects of wire speed, feed speed and tension pressure on the surface roughness were analyzed. Surface roughness in cutting direction and feed direction were both detected. The results show that feed speed plays the most significant role on the surface roughness of sliced sapphire followed by wire speed and tension pressure. The optimized process parameters are as follows: wire speed 1.9 m/s, feed speed 0.187 mm/min and tension pressure 0.18 MPa. In the end, the results were verified by analysis of variance.

Keywords: fixed abrasive, diamond wire saw, slicing, sapphire, orthogonal experiment

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Authors: Byeong-Sam Kim, Kyoungwoo Park

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This research analyzes structure of flat panel display (FPD) such as LCD as quantitative through CFD analysis and modeling change to minimize the badness rate and rate of production decrease by damage of large scale plater at wafer heating chamber at semi-conductor manufacturing process. This glass panel and wafer device with atmospheric pressure or chemical vapor deposition equipment for transporting and transferring wafers, robot hands carry these longer and wider wafers can also be easily handled. As a contact handling system composed of several problems in increased potential for fracture or warping. A non-contact handling system is required to solve this problem. The panel and wafer warping makes it difficult to carry out conventional contact to analysis. We propose a new non-contact transportation system with combining air suction and blowout. The numerical analysis and experimental is, therefore, should be performed to obtain compared to results achieved with non-contact solutions. This wafer panel noncontact handler shows its strength in maintaining high cleanliness levels for semiconductor production processes.

Keywords: flat panel display, non contact transportation, heat treatment process, CFD analysis

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Authors: Takashi Ehara, Takayoshi Nakanishi, Kohei Sasaki, Marina Abe, Hiroshi Abe, Kiyoaki Abe, Ryo Iizaka, Takuya Sato

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CuAlO₂ thin films are prepared on Si or sapphire substrate by sol-gel method using two kinds of sols. One is combination of Cu acetate and Al acetate basic, and the other is Cu nitrate and Al nitrate. In the case of acetate sol, XRD peaks of CuAlO₂ observed at annealing temperature of 800-950 ºC on both Si and sapphire substrates. In contrast, in the case of the films prepared using nitrate on Si substrate, XRD peaks of CuAlO₂ have been observed only at the annealing temperature of 800-850 ºC. At annealing temperature of 850ºC, peaks of other species have been observed beside the CuAlO₂ peaks, then, the CuAlO₂ peaks disappeared at annealing temperature of 900 °C with increasing in intensity of the other peaks. Intensity of the other peaks decreased at annealing temperature of 950 ºC with appearance of broad SiO₂ peak. In the present, we ascribe these peaks as metal silicide.

Keywords: CuAlO2, silicide, thin Films, transparent conducting oxide

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Authors: S. Zhuiykov, Z. Wei

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Conformal defect-free two-dimensional (2D) WO₃ and TiO₂ semiconductors have been developed by the atomic layer deposition (ALD) technique on wafer scale with unique approach to the thickness control with precision of ± 10% from the monolayer of nanomaterial (less than 1.0 nm thick) to the nano-layered 2D structures with thickness of ~3.0-7.0 nm. Developed 2D nanostructures exhibited unique, distinguishable properties at nanoscale compare to their thicker counterparts. Specifically, 2D TiO₂-Au bilayer demonstrated improved photocatalytic degradation of palmitic acid under UV and visible light illumination. Improved functional capabilities of 2D semiconductors would be advantageous to various environmental, nano-energy and bio-sensing applications. The ALD-enabled approach is proven to be versatile, scalable and applicable to the broader range of 2D semiconductors.

Keywords: two-dimensional (2D) semiconductors, ALD, WO₃, TiO₂, wafer scale

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Authors: Ilsun Pang, Kwanghun Kim, Sungsun Baik

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Large diameter Si wafer is used as semiconductor substrate. Large diameter Si crystal ingot should be needed in order to increase wafer size. To make convection of large silicon melt stable, magnetic field is normally applied, but magnetic field is expensive and it is not proper to stabilize the large Si melt. To solve the problem, we propose a continuous Czochralski process which can be applied to small melt without magnetic field. We used granule poly, which has size distribution of 1~3 mm and is easily supplied in double crucible during silicon ingot growth. As the result, we produced 420 mm diameter ingot. In this paper, we describe an experimental study on crystal growth of large diameter silicon by Continuous Czochralski process.

Keywords: Czochralski, ingot, silicon crystal, wafer

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Authors: De-Shin Liu, Po-Chun Wen, Zhen-Wei Zhuang, Hsueh-Chih Liu, Pei-Chen Huang

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Wafer probing tests play an important role in semiconductor manufacturing procedures in accordance with the yield and reliability requirement of the wafer after the backend-of-the-line process. Accordingly, the stable physical and electrical contact between the probe and the tested wafer during wafer probing is regarded as an essential issue in identifying the known good die. The probe card can be integrated with multiple probe needles, which are classified as vertical, cantilever and micro-electro-mechanical systems type probe selections. Among all potential probe types, the vertical probe has several advantages as compared with other probe types, including maintainability, high probe density and feasibility for high-speed wafer testing. In the present study, the mechanical response of the wafer probing test with the vertical cobra probe on 720 μm thick silicon (Si) substrate with a 1.4 μm thick aluminum (Al) pad is investigated by the experiment and transient dynamic simulation approach. Because the deformation mechanism of the vertical cobra probe is determined by both bending and buckling mechanisms, the stable correlation between contact forces and overdrive (OD) length must be carefully verified. Moreover, the decent OD length with corresponding contact force contributed to piercing the native oxide layer of the Al pad and preventing the probing test-induced damage on the interconnect system. Accordingly, the scratch depth of the Al pad under various OD lengths is estimated by the atomic force microscope (AFM) and simulation work. In the wafer probing test configuration, the contact phenomenon between the probe needle and the tested object introduced large deformation and twisting of mesh gridding, causing the subsequent numerical divergence issue. For this reason, the arbitrary Lagrangian-Eulerian method is utilized in the present simulation work to conquer the aforementioned issue. The analytic results revealed a slight difference when the OD is considered as 40 μm, and the simulated is almost identical to the measured scratch depths of the Al pad under higher OD lengths up to 70 μm. This phenomenon can be attributed to the unstable contact of the probe at low OD length with the scratch depth below 30% of Al pad thickness, and the contact status will be being stable when the scratch depth over 30% of pad thickness. The splash of the Al pad is observed by the AFM, and the splashed Al debris accumulates on a specific side; this phenomenon is successfully simulated in the transient dynamic simulation. Thus, the preferred testing OD lengths are found as 45 μm to 70 μm, and the corresponding scratch depths on the Al pad are represented as 31.4% and 47.1% of Al pad thickness, respectively. The investigation approach demonstrated in this study contributed to analyzing the mechanical response of wafer probing test configuration under large strain conditions and assessed the geometric designs and material selections of probe needles to meet the requirement of high resolution and high-speed wafer-level probing test for thinned wafer application.

Keywords: wafer probing test, vertical probe, probe mark, mechanical response, FEA simulation

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Authors: Guanlin Wu, Jiajia Yao, Fang Liu, Junshuai Xue, Jincheng Zhang, Yue Hao

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Owing to the excellent thermal conductivity and ultra-wide bandgap, Aluminum nitride (AlN)/Gallium nitride (GaN) is a highly promising material to achieve high breakdown voltage and output power devices among III-nitrides. In this study, we explore the growth and characterization of polarization-induced AlN/GaN heterostructures using plasma-assisted molecular beam epitaxy (PA-MBE) on AlN-on-sapphire templates. To improve the crystal quality and demonstrate the effectiveness of the PA-MBE approach, a thick AlN buffer of 180 nm was first grown on the AlN-on sapphire template. This buffer acts as a back-barrier to enhance the breakdown characteristic and isolate leakage paths that exist in the interface between the AlN epilayer and the AlN template. A root-mean-square roughness of 0.2 nm over a scanned area of 2×2 µm2 was measured by atomic force microscopy (AFM), and the full-width at half-maximum of (002) and (102) planes on the X-ray rocking curve was 101 and 206 arcsec, respectively, using by high-resolution X-ray diffraction (HR-XRD). The electron mobility of 443 cm2/Vs with a carrier concentration of 2.50×1013 cm-2 at room temperature was achieved in the AlN/GaN heterostructures by using a polarization-induced GaN channel. The low depletion capacitance of 15 pF is resolved by the capacitance-voltage. These results indicate that the polarization-induced AlN/GaN heterostructures have great potential for next-generation high-temperature, high-frequency, and high-power electronics.

Keywords: AlN, GaN, MBE, heterostructures

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

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Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: fast vs slow BTI, fast wafer level reliability (FWLR), negative bias temperature instability (NBTI), NBTI measurement system, metal-oxide-semiconductor field-effect transistor (MOSFET), NBTI recovery, reliability

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Authors: Youngji Yoo, Seung Hwan Park, Daewoong An, Sung-Shick Kim, Jun-Geol Baek

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The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.

Keywords: semiconductor, wafer bin map, feature extraction, spatial point patterns, contour map

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Authors: Deb Kumar Shah, M. Shaheer Akhtar, Ha Ryeon Lee, O-Bong Yang, Chong Yeal Kim

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The crystalline silicon (Si) solar cells are highly renowned photovoltaic technology and well-established as the commercial solar technology. Most of the solar panels are globally installed with the crystalline Si solar modules. At the present scenario, the major photovoltaic (PV) market is shared by c-Si solar cells, but the cost of c-Si panels are still very high as compared with the other PV technology. In order to reduce the cost of Si solar panels, few necessary steps such as low-cost Si manufacturing, cheap antireflection coating materials, inexpensive solar panel manufacturing are to be considered. It is known that the antireflection (AR) layer in c-Si solar cell is an important component to reduce Fresnel reflection for improving the overall conversion efficiency. Generally, Si wafer exhibits the 30% reflection because it normally poses the two major intrinsic drawbacks such as; the spectral mismatch loss and the high Fresnel reflection loss due to the high contrast of refractive indices between air and silicon wafer. In recent years, researchers and scientists are highly devoted to a lot of researches in the field of searching effective and low-cost AR materials. Silicon nitride (SiNx) is well-known AR materials in commercial c-Si solar cells due to its good deposition and interaction with passivated Si surfaces. However, the deposition of SiNx AR is usually performed by expensive plasma enhanced chemical vapor deposition (PECVD) process which could have several demerits like difficult handling and damaging the Si substrate by plasma when secondary electrons collide with the wafer surface for AR coating. It is very important to explore new, low cost and effective AR deposition process to cut the manufacturing cost of c-Si solar cells. One can also be realized that a nano-texturing process like the growth of nanowires, nanorods, nanopyramids, nanopillars, etc. on Si wafer can provide a low reflection on the surface of Si wafer based solar cells. The above nanostructures might be enhanced the antireflection property which provides the larger surface area and effective light trapping. In this work, we report on the development of crystalline Si solar cells without using the AR layer. The Silicon wafer was modified by growing nanowires like Si nanostructures using the wet controlled etching method and directly used for the fabrication of Si solar cell without AR. The nanostructures over Si wafer were optimized in terms of sizes, lengths, and densities by changing the etching conditions. Well-defined and aligned wires like structures were achieved when the etching time is 20 to 30 min. The prepared Si nanostructured displayed the minimum reflectance ~1.64% at 850 nm with the average reflectance of ~2.25% in the wavelength range from 400-1000 nm. The nanostructured Si wafer based solar cells achieved the comparable power conversion efficiency in comparison with c-Si solar cells with SiNx AR layer. From this study, it is confirmed that the reported method (controlled wet etching) is an easy, facile method for preparation of nanostructured like wires on Si wafer with low reflectance in the whole visible region, which has greater prospects in developing c-Si solar cells without AR layer at low cost.

Keywords: chemical etching, conversion efficiency, silicon nanostructures, silicon solar cells, surface modification

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Authors: Jeff Moussodji, Dominique Drouin

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The highly complex technology requirements of today’s integrated circuits (ICs), lead to the increased use of several materials types such as metal structures, brittle and porous low-k materials which are used in both front end of line (FEOL) and back end of line (BEOL) process for wafer manufacturing. In order to singulate chip from wafer, a critical laser-grooving process, prior to blade dicing, is used to remove these layers of materials out of the dicing street. The combination of laser-grooving and blade dicing allows to reduce the potential risk of induced mechanical defects such micro-cracks, chipping, on the wafer top surface where circuitry is located. It seems, therefore, essential to have a fundamental understanding of the physics involving laser-dicing in order to maximize control of these critical process and reduce their undesirable effects on process efficiency, quality, and reliability. In this paper, the study was based on the convergence of two approaches, numerical and experimental studies which allowed us to investigate the interaction of a nanosecond pulsed laser and BEOL wafer materials. To evaluate this interaction, several laser grooved samples were compared with finite element modeling, in which three different aspects; phase change, thermo-mechanical and optic sensitive parameters were considered. The mathematical model makes it possible to highlight a groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat affected zone, and thermo-mechanical stress can be also predicted as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a satisfying correlation between experiment and modeling, results have been observed in terms of groove depth, width and heat affected zone. The study proposed in this work is a first step toward implementing a quick assessment tool for design and debug of multiple laser grooving conditions with limited experiments on hardware in industrial application. More correlations and validation tests are in progress and will be included in the full paper.

Keywords: laser-dicing, nano-second pulsed laser, wafer multi-stack, multiphysics modeling

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Authors: A.Chen Chao-Chang, Phong Pham-Quoc

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Chemical-mechanical polishing (CMP) process has been widely applied on fabricating integrated circuits (IC) with a soft polishing pad combined with slurry composed of micron or nano-scaled abrasives for generating chemical reaction to remove substrate or film materials from wafer. During CMP process, pad uniformity usually works as a datum surface of wafer planarization and pad asperities can dominate the microscopic pad-slurry-wafer interaction. However, pad topography can be changed by related mechanism factors of CMP and it needs to be re-conditioned or dressed by a diamond dresser of well-distributed diamond grits on a disc surface. It is still very complicated to analyze and understand kinematic of diamond dressing process under the effects of input variables including oscillatory of diamond dresser and rotation speed ratio between the pad and the diamond dresser. This paper has developed a generic geometric model to clarify the kinematic modeling of diamond dressing processes such as dresser/pad motion, pad cutting locus, the relative velocity of the diamond abrasive grits on pad surface, and overlap of cutting for prediction of pad surface topography. Simulation results focus on comparing and analysis kinematics of the diamond dressing on certain CMP tools. Results have shown the significant parameters for diamond dressing process and also discussed. Future study can apply on diamond dresser design and experimental verification of pad dressing process.

Keywords: kinematic modeling, diamond dresser, pad cutting locus, CMP

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Authors: Merve Yünlü, Nihat Kandemir, Aylin Ersoy

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Temperature sensors are used in home appliances not only to monitor the basic functions of the machine but also to minimize energy consumption and ensure safe operation. In parallel with the development of smart home applications and IoT algorithms, these sensors produce important data such as the frequency of use of the machine, user preferences, and the compilation of critical data in terms of diagnostic processes for fault detection throughout an appliance's operational lifespan. Commercially available thin-film resistive temperature sensors have a well-established manufacturing procedure that allows them to operate over a wide temperature range. However, these sensors are over-designed for white goods applications. The operating temperature range of these sensors is between -70°C and 850°C, while the temperature range requirement in home appliance applications is between 23°C and 500°C. To ensure the operation of commercial sensors in this wide temperature range, usually, a platinum coating of approximately 1-micron thickness is applied to the wafer. However, the use of platinum in coating and the high coating thickness extends the sensor production process time and therefore increases sensor costs. In this study, an attempt was made to develop a low-cost temperature sensor design and production method that meets the technical requirements of white goods applications. For this purpose, a custom design was made, and design parameters (length, width, trim points, and thin film deposition thickness) were optimized by using statistical methods to achieve the desired resistivity value. To develop thin film resistive temperature sensors, one side polished sapphire wafer was used. To enhance adhesion and insulation 100 nm silicon dioxide was coated by inductively coupled plasma chemical vapor deposition technique. The lithography process was performed by a direct laser writer. The lift-off process was performed after the e-beam evaporation of 10 nm titanium and 280 nm platinum layers. Standard four-point probe sheet resistance measurements were done at room temperature. The annealing process was performed. Resistivity measurements were done with a probe station before and after annealing at 600°C by using a rapid thermal processing machine. Temperature dependence between 25-300 °C was also tested. As a result of this study, a temperature sensor has been developed that has a lower coating thickness than commercial sensors but can produce reliable data in the white goods application temperature range. A relatively simplified but optimized production method has also been developed to produce this sensor.

Keywords: thin film resistive sensor, temperature sensor, household appliance, sustainability, energy efficiency

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Authors: Wheyming Song, Hung-Hsiang Lin, Scott Lian

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In this research, we investigate the optimal dispatching rule for machines and manpower allocation in the solar ingot-wafer systems. The performance of the method is measured by the sales profit for each dollar paid to the operators in a one week at steady-state. The decision variables are identification-number of machines and operators when each job is required to be served in each process. We propose a rule which is a function of operator’s ability, corresponding salary, and standing location while in the factory. The rule is named ‘Multi-nominal distribution dispatch rule’. The proposed rule performs better than many traditional rules including generic algorithm and particle swarm optimization. Simulation results show that the proposed Multi-nominal distribution dispatch rule improvement on the sales profit dramatically.

Keywords: dispatching, solar ingot, simulation, flexsim

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Authors: Kunal Bhardwaj, Christine Browne

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With the increase in global awareness of the environmental impacts of plastic-based products, there has been a massive drive to reduce our use of these products. Use of plastic-based substrates in electronic circuits has been a matter of concern recently. Plastics provide a very smooth and cheap surface for printing high-performance electronics due to their non-permeability to ink and easy mouldability. In this research, we explore the use of nano cellulose (NC) films in electronics as they provide an advantage of being 100% recyclable and eco-friendly. The main hindrance in the mass adoption of NC film as a substitute for plastic is its higher surface roughness which leads to ink penetration, and dispersion in the channels on the film. This research was conducted to tune the RMS roughness of NC films to a range where they can replace plastics in electronics(310-470nm). We studied the dependence of the surface roughness of the NC film on the following tunable aspects: 1) composition by weight of the NC suspension that is sprayed on a silicon wafer 2) the width and the depth of the channels on the silicon wafer used as a base. Various silicon wafers with channel depths ranging from 6 to 18 um and channel widths ranging from 5 to 500um were used as a base. Spray coating method for NC film production was used and two solutions namely, 1.5wt% NC and a 50-50 NC-CNC (cellulose nanocrystal) mixture in distilled water, were sprayed through a Wagner sprayer system model 117 at an angle of 90 degrees. The silicon wafer was kept on a conveyor moving at a velocity of 1.3+-0.1 cm/sec. Once the suspension was uniformly sprayed, the mould was left to dry in an oven at 50°C overnight. The images of the films were taken with the help of an optical profilometer, Olympus OLS 5000. These images were converted into a ‘.lext’ format and analyzed using Gwyddion, a data and image analysis software. Lowest measured RMS roughness of 291nm was with a 50-50 CNC-NC mixture, sprayed on a silicon wafer with a channel width of 5 µm and a channel depth of 12 µm. Surface roughness values of 320+-17nm were achieved at lower (5 to 10 µm) channel widths on a silicon wafer. This research opened the possibility of the usage of 100% recyclable NC films with an additive (50% CNC) in high-performance electronics. Possibility of using additives like Carboxymethyl Cellulose (CMC) is also being explored due to the hypothesis that CMC would reduce friction amongst fibers, which in turn would lead to better conformations amongst the NC fibers. CMC addition would thus be able to help tune the surface roughness of the NC film to an even greater extent in future.

Keywords: nano cellulose films, electronic circuits, nanocrystals and surface roughness

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Authors: Nelson Andres, Meeko C. Masangcap, John Denver D. Catapang

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Balanga City as, the heart of Bataan, is a growing City and is now at its fast pace of development. The growth of commerce in the city results to an increase in commuters who travel back and forth through the city, leading to congestions. Consequently, queuing of vehicles along national roads and even in the highways of the city have become a regular occurrence. This common scenario of commuters flocking the city, private and public vehicles going bumper to bumper, especially during the rush hours, greatly affect the flow of traffic vehicles and is now a burden not only to the commuters but also to the government who is trying to address this dilemma. Seeing these terrible events, the implementation of an elevated Automated Guide-way transit is seen as a possible solution to help in the decongestion of the affected parts of Balanga City.In response to the problem, the researchers identify if it is feasible to have an elevated guide-way transit in the vicinity of Sapphire Street in Balanga City, Bataan. Specifically, the study aims to determine who will be the riders based on the demographic profile, where the trip can be generated and distributed, the time when volume of people usually peaks and the estimated volume of passengers. Statistical analysis is applied to the data gathered to find out if there is an important relationship between the demographic profile of the respondents and their preference of having an elevated railway transit in the City of Balanga.

Keywords: ridership, AGT, railway, elevated track

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Authors: Sami Iqbal, Azam Hussain, Weiping Wu, Guo Xinli, Tong Zhang

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A novel octagonal upright micro-pyramid structure was generated by wet chemical anisotropic etching on a monocrystalline silicon wafer (100). The primary objectives are to reduce front surface reflectance of silicon wafers, improve wettability, enhance surface morphology, and maximize the area coverage by generated octagonal pyramids. Under rigorous control and observation, the etching process' response time was maintained precisely. The experimental outcomes show a significant decrease in the optical surface reflectance of silicon wafers, with the lowest reflectance of 8.98%, as well as enhanced surface structure, periodicity, and surface area coverage of more than 85%. The octagonal silicon pyramid was formed with a high etch rate of 0.41 um/min and a much shorter reaction time with the addition of hydrofluoric acid coupled with magnetic stirring (mechanical agitation) at 300 rpm.

Keywords: octagonal pyramids, rapid etching, solar cells, surface engineering, surface reflectance

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Authors: Jiajia Yao, GuanLin Wu, Fang liu, JunShuai Xue, JinCheng Zhang, Yue Hao

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Due to its outstanding material properties like high thermal conductivity and ultra-wide bandgap, Aluminum nitride (AlN) has the promising potential to provide high breakdown voltage and high output power among III-nitrides for various applications in electronics and optoelectronics. This work presents material growth and characterization of strained channel Aluminum nitride/Gallium nitride (AlN/GaN) heterostructures grown by plasma-assisted molecular beam epitaxy (PA-MBE) on AlN-on-sapphire templates. To improve the crystal quality and manifest the ability of the PA-MBE approach, a thick AlN buffer with a thickness of 180 nm is first grown on AlN template, which acts as a back-barrier to enhance the breakdown characteristic and isolates the leakage path existing in the interface between AlN epilayer and AlN template, as well as improve the heat dissipation. The grown AlN buffer features a root-mean-square roughness of 0.2 nm over a scanned area of 2×2 µm2 measured by atomic force microscopy (AFM), and exhibits full-width at half-maximum of 95 and 407 arcsec for the (002) and (102) plane the X-ray rocking curve, respectively, tested by high resolution x-ray diffraction (HR-XRD). With a thin and strained GaN channel, the electron mobility of 294 cm2 /Vs. with a carrier concentration of 2.82×1013 cm-2 at room temperature is achieved in AlN/GaN double-channel heterostructures, and the depletion capacitance is as low as 14 pF resolved by the capacitance-voltage, which indicates the promising opportunities for future applications in next-generation high temperature, high-frequency and high-power electronics with a further increased electron mobility by optimization of heterointerface quality.

Keywords: AlN/GaN, HEMT, MBE, homoepitaxy

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Authors: Luc Conti, Dimitry Dumont-Fillon, Harald van Lintel, Eric Chappel

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Flow control valves comprise a silicon flexible membrane that deflects against a substrate, usually made of glass, containing pillars, an outlet hole, and anti-stiction features. However, there is a strong interest in using silicon instead of glass as substrate material, as it would simplify the process flow by allowing the use of well controlled anisotropic etching. Moreover, specific devices demanding a bending of the substrate would also benefit from the inherent outstanding mechanical strength of monocrystalline silicon. Unfortunately, direct Si-Si bonding is not easily achieved with highly structured wafers since residual stress may prevent the good adhesion between wafers. Using a thermoplastic polymer, such as parylene, as intermediate layer is not well adapted to this design as the wafer-to-wafer alignment is critical. An alternative anodic bonding method using an intermediate borosilicate layer has been successfully tested. This layer has been deposited onto the silicon substrate. The bonding recipe has been adapted to account for the presence of the SOI buried oxide and intermediate glass layer in order not to exceed the breakdown voltage. Flow control valves dedicated to infusion of viscous fluids at very high pressure have been made and characterized. The results are compared to previous data obtained using the standard anodic bonding method.

Keywords: anodic bonding, evaporated glass, flow control valve, drug delivery

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Authors: C. Virgilio, J. Carlier, P. Campistron, M. Toubal, P. Garnier, L. Broussous, V. Thomy, B. Nongaillard

Abstract:

Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real challenge in integrated circuits manufacturing. In fact, bad or non-uniform wetting during wet processes limits chemical reactions and can lead to non-complete etching or cleaning inside the patterns and device defectivity. This issue is more and more important with the transistors size shrinkage and concerns mainly high aspect ratio structures. Deep Trench Isolation (DTI) structures enabling pixels’ isolation in imaging devices are subject to this phenomenon. While low-frequency acoustic reflectometry principle is a well-known method for Non Destructive Test applications, we have recently shown that it is also well suited for nanostructures wetting characterization in a higher frequency range. In this paper, we present a high-frequency acoustic reflectometry characterization of DTI wetting through a confrontation of both experimental and modeling results. The acoustic method proposed is based on the evaluation of the reflection of a longitudinal acoustic wave generated by a 100 µm diameter ZnO piezoelectric transducer sputtered on the silicon wafer backside using MEMS technologies. The transducers have been fabricated to work at 5 GHz corresponding to a wavelength of 1.7 µm in silicon. The DTI studied structures, manufactured on the wafer frontside, are crossing trenches of 200 nm wide and 4 µm deep (aspect ratio of 20) etched into a Si wafer frontside. In that case, the acoustic signal reflection occurs at the bottom and at the top of the DTI enabling its characterization by monitoring the electrical reflection coefficient of the transducer. A Finite Difference Time Domain (FDTD) model has been developed to predict the behavior of the emitted wave. The model shows that the separation of the reflected echoes (top and bottom of the DTI) from different acoustic modes is possible at 5 Ghz. A good correspondence between experimental and theoretical signals is observed. The model enables the identification of the different acoustic modes. The evaluation of DTI wetting is then performed by focusing on the first reflected echo obtained through the reflection at Si bottom interface, where wetting efficiency is crucial. The reflection coefficient is measured with different water / ethanol mixtures (tunable surface tension) deposited on the wafer frontside. Two cases are studied: with and without PFTS hydrophobic treatment. In the untreated surface case, acoustic reflection coefficient values with water show that liquid imbibition is partial. In the treated surface case, the acoustic reflection is total with water (no liquid in DTI). The impalement of the liquid occurs for a specific surface tension but it is still partial for pure ethanol. DTI bottom shape and local pattern collapse of the trenches can explain these incomplete wetting phenomena. This high-frequency acoustic method sensitivity coupled with a FDTD propagative model thus enables the local determination of the wetting state of a liquid on real structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are then detectable with this method.

Keywords: wetting, acoustic reflectometry, gigahertz, semiconductor

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Authors: T. Patcharawit, C. Kansomket, N. Wongnaree, W. Kritsrikan, T. Yingnakorn, S. Khumkoa

Abstract:

Recovery of pure copper and silver from end-of-life photovoltaic panels was investigated in this paper using an effective hybrid pyro-hydrometallurgical process. In the first step of waste treatment, solar panel waste was first dismantled to obtain a PV sheet to be cut and calcined at 500°C, to separate out PV ribbon from glass cullet, ash, and volatile while the silicon wafer containing silver finger was collected for recovery. In the second step of metal recovery, copper recovery from photovoltaic ribbon was via 1-3 M HCl leaching with SnCl₂ and H₂O₂ additions in order to remove the tin-lead coating on the ribbon. The leached copper band was cleaned and subsequently melted as an anode for the next step of electrorefining. Stainless steel was set as the cathode with CuSO₄ as an electrolyte, and at a potential of 0.2 V, high purity copper of 99.93% was obtained at 96.11% recovery after 24 hours. For silver recovery, the silicon wafer containing silver finger was leached using HNO₃ at 1-4 M in an ultrasonic bath. In the next step of precipitation, silver chloride was then obtained and subsequently reduced by sucrose and NaOH to give silver powder prior to oxy-acetylene melting to finally obtain pure silver metal. The integrated recycling process is considered to be economical, providing effective recovery of high purity metals such as copper and silver while other materials such as aluminum, copper wire, glass cullet can also be recovered to be reused commercially. Compounds such as PbCl₂ and SnO₂ obtained can also be recovered to enter the market.

Keywords: electrorefining, leaching, calcination, PV ribbon, silver finger, solar panel

Procedia PDF Downloads 134

Authors: Deybith Venegas-Rojas, Sercan Keskin, Svenja Riekeberg, Sana Azim, Stephanie Manz, R. J. Dwayne Miller, Hoc Khiem Trieu

Abstract:

Liquid Transmission Electron Microscopy (TEM) is a growing area with a broad range of applications from physics and chemistry to material engineering and biology, in which it is possible to image in-situ unseen phenomena. For this, a nanofluidic device is used to insert the nanoflow with the sample inside the microscope in order to keep the liquid encapsulated because of the high vacuum. In the last years, Si3N4 windows have been widely used because of its mechanical stability and low imaging contrast. Nevertheless, the pressure difference between the inside fluid and the outside vacuum in the TEM generates bulging in the windows. This increases the imaged fluid volume, which decreases the signal to noise ratio (SNR), limiting the achievable spatial resolution. With the proposed device, the membrane is fortified with a microstructure capable of stand higher pressure differences, and almost removing completely the bulging. A theoretical study is presented with Finite Element Method (FEM) simulations which provide a deep understanding of the membrane mechanical conditions and proves the effectiveness of this novel concept. Bulging and von Mises Stress were studied for different membrane dimensions, geometries, materials, and thicknesses. The microfabrication of the device was made with a thin wafer coated with thin layers of SiO2 and Si3N4. After the lithography process, these layers were etched (reactive ion etching and buffered oxide etch (BOE) respectively). After that, the microstructure was etched (deep reactive ion etching). Then the back side SiO2 was etched (BOE) and the array of free-standing micro-windows was obtained. Additionally, a Pyrex wafer was patterned with windows, and inlets/outlets, and bonded (anodic bonding) to the Si side to facilitate the thin wafer handling. Later, a thin spacer is sputtered and patterned with microchannels and trenches to guide the nanoflow with the samples. This approach reduces considerably the common bulging problem of the window, improving the SNR, contrast and spatial resolution, increasing substantially the mechanical stability of the windows, allowing a larger viewing area. These developments lead to a wider range of applications of liquid TEM, expanding the spectrum of possible experiments in the field.

Keywords: liquid cell, liquid transmission electron microscopy, nanofluidics, nanofluidic cell, thin films

Procedia PDF Downloads 255

Authors: A. Abbas, X. Tridon, J. Michelon

Abstract:

In the electronic or in the photovoltaic industries, components are made from wafers which are stacks of thin film layers of a few nanometers to serval micrometers thickness. Early evaluation of the bounding quality between different layers of a wafer is one of the challenges of these industries to avoid dysfunction of their final products. Traditional pump-probe experiments, which have been developed in the 70’s, give a partial solution to this problematic but with a non-negligible drawback. In fact, on one hand, these setups can generate and detect ultra-high ultrasounds frequencies which can be used to evaluate the adhesion quality of wafer layers. But, on the other hand, because of the quiet long acquisition time they need to perform one measurement, these setups remain shut in punctual measurement to evaluate global sample quality. This last point can lead to bad interpretation of the sample quality parameters, especially in the case of inhomogeneous samples. Asynchronous Optical Sampling (ASOPS) systems can perform sample characterization with picosecond acoustics up to 106 times faster than traditional pump-probe setups. This last point allows picosecond ultrasonic to unlock the acoustic imaging field at the nanometric scale to detect inhomogeneities regarding sample mechanical properties. This fact will be illustrated by presenting an image of the measured acoustical reflection coefficients obtained by mapping, with an ASOPS setup, a 255nm thin-film tungsten layer deposited on a silicone substrate. Interpretation of the coefficient reflection in terms of bounding quality adhesion will also be exposed. Origin of zones which exhibit good and bad quality bounding will be discussed.

Keywords: adhesion, picosecond ultrasonics, pump-probe, thin film

Procedia PDF Downloads 158

Authors: Sang Koo Jeon, Seung Hoon Nahm, Oh Heon Kwon

Abstract:

The unit cell of solid oxide fuel cell (SOFC) must be stacked as several layers type to obtain the high power. The most of researcher have concerned about the performance of stacked SOFC rather than the structural stability of stacked SOFC and especially interested how to design for reducing the electrical loss and improving the high efficiency. Consequently, the stacked SOFC able to produce the electrical high power and related parts like as manifold, gas seal, bipolar plate were developed to optimize the stack design. However, the unit cell of SOFC was just layered on the interconnector without the adhesion and the hydrogen and oxygen were injected to the interfacial layer in the high temperature. On the operating condition, the interfacial layer can be the one of the weak point in the stacked SOFC. Therefore the evaluation of the structural safety for the failure is essentially needed. In this study, interfacial adhesion between SOFC and metal adhesive was estimated in the high temperature environment. The metal adhesive was used to strongly connect the unit cell of SOFC with interconnector and provide the electrical conductivity between them. The four point bending test was performed to measure the interfacial adhesion. The unit cell of SOFC and SiO2 wafer were diced and then attached by metal adhesive. The SiO2 wafer had the center notch to initiate a crack from the tip of the notch. The modified stereomicroscope combined with the CCD camera and system for measuring the length was used to observe the fracture behavior. Additionally, the interfacial adhesion was evaluated in the high temperature condition because the metal adhesive was affected by high temperature. Also the specimen was exposed in the furnace during several hours and then the interfacial adhesion was evaluated. Finally, the interfacial adhesion energy was quantitatively determined and compared in the each condition.

Keywords: solid oxide fuel cell (SOFC), metal adhesive, adhesion, high temperature

Procedia PDF Downloads 520

Authors: Jin-Uk Park

Abstract:

Recently, the semiconductor industry is rapidly demanding complicated structures and mass production. From the point of view of mass production, the ETCH industry is concentrating on maintaining the ER (Etch rate) of the wafer edge constant regardless of changes over time. In this study, two major thermal factors affecting process were identified and controlled. First, the filler of the thermal pad was studied. Second, the significant difference of handling the thermal pad during PM was studied.

Keywords: etcher, thermal pad, wet cleaning, thermal conductivity

Procedia PDF Downloads 191

Authors: Jin-Sup Kim, Se-Hwan Choi, Jae-Young Lee

Abstract:

A 8-bit CMOS capacitor array is designed for using in electrically steerable passive array radiator (ESPAR). The proposed capacitor array shows the fast response time in rising and falling characteristics. Compared to other works in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, it shows a comparable tuning range and switching time with low power consumption. Using the 0.18um CMOS, the capacitor array features a tuning range of 1.5 to 12.9 pF at 2.4GHz. Including the 2X4 decoder for control interface, the Chip size is 350um X 145um. Current consumption is about 80 nA at 1.8 V operation.

Keywords: CMOS capacitor array, ESPAR, SOI, SOS, switching time

Procedia PDF Downloads 588