Search results for: CMOS capacitor array

Authors: Jin-Sup Kim, Se-Hwan Choi, Jae-Young Lee

Abstract:

A 8-bit CMOS capacitor array is designed for using in electrically steerable passive array radiator (ESPAR). The proposed capacitor array shows the fast response time in rising and falling characteristics. Compared to other works in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, it shows a comparable tuning range and switching time with low power consumption. Using the 0.18um CMOS, the capacitor array features a tuning range of 1.5 to 12.9 pF at 2.4GHz. Including the 2X4 decoder for control interface, the Chip size is 350um X 145um. Current consumption is about 80 nA at 1.8 V operation.

Keywords: CMOS capacitor array, ESPAR, SOI, SOS, switching time

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Authors: Ki-Jin Kim, Suk-Hui LEE, Sanghoon Park, K. H. Ahn

Abstract:

A high power, low loss asymmetric single pole double through(SPDT) antenna switch for LTE-A Front-End Module(FEM) is presented in this paper by using CMOS technology. For the usage of LTE-A applications, low loss and high linearity are the key features which are very challenging works under CMOS process. To enhance insertion loss(IL) and power handling capability, this paper adopts asymmetric Transmitter (TX) and RX (Receiver) structure, floating body technique, multi-stacked structure, and feed forward capacitor technique. The designed SPDT switch shows TX IL 0.34 dB, RX IL 0.73 dB, P1dB 38.9 dBm at 0.9 GHz and TX IL 0.37 dB, RX IL 0.95 dB, P1dB 39.1 dBm at 2.5 GHz respectively.

Keywords: CMOS switch, SPDT switch, high power CMOS switch, LTE-A FEM

Procedia PDF Downloads 335

Authors: Anuja Askhedkar, G. H. Agrawal, Madhu Gudgunti

Abstract:

Direct Charge Transfer Switched Capacitor (DCT-SC) DAC is the internal DAC used in Delta-Sigma (∆∑) DAC which works on Over-Sampling concept. The Switched Capacitor DAC mainly suffers from mismatch among capacitors. Mismatch among capacitors in DAC, causes non linearity between output and input. Dynamic Element Matching (DEM) technique is used to match the capacitors. According to element selection logic there are many types. In this paper, Data Weighted Averaging (DWA) technique is used for mismatch shaping. In this paper, the 4 bit DCT-SC-DAC with DWA-DEM technique is implemented using WINSPICE simulation software in 180nm CMOS technology. DNL for DAC with DWA is ±0.03 LSB and INL is ± 0.02LSB.

Keywords: ∑-Δ DAC, DCT-SC-DAC, mismatch shaping, DWA, DEM

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Authors: Tribhuvan N. Soorya

Abstract:

Charging and discharging of a capacitor through a resistor can be shown as exponential curve. Theoretically, it takes infinite time to fully charge or discharge a capacitor. The flow of charge is due to electrons having finite and fixed value of charge. If we carefully examine the charging and discharging process after several time constants, the points on q vs t graph become discrete and curve become discontinuous. Moreover for all practical purposes capacitor with charge (q0-e) can be taken as fully charged, as it introduces an error less than one part per million. Similar is the case for discharge of a capacitor, where the capacitor with the last electron (charge e) can be taken as fully discharged. With this, we can estimate the finite value of time for fully charging and discharging a capacitor.

Keywords: charging, discharging, RC Circuit, capacitor

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Authors: R. K. Saket, K. S. Anand Kumar

Abstract:

This paper presents an innovative 3-wire capacitor circuit system used to increase the efficiency and comfort improvement of permanent split-capacitor ceiling fan. In this innovative circuit, current has been reduced to save electrical power. The system could be used to replace standard single phase motor 2-wire capacitor configuration by cost effective split value X rated of optimized AC capacitors with the auxiliary winding to provide reliable ceiling fan operation and improved machine performance to save power. In basic system operations, comparisons with conventional ceiling fan are described.

Keywords: permanent split-capacitor motor, innovative 3-wire capacitor circuit system, standard 2-wire capacitor circuit system, metalized film X-rated capacitor

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Authors: Chhavi Saxena

Abstract:

FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM cell, leakage current, delay

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Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA

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Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

Abstract:

This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

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Authors: Hooman Kaabi, Raziyeh Karkoub

Abstract:

This work proposes a structure of AMOS-varactors. A 5GHz LC-VCO designed in TSMC 0.18μm CMOS to improve phase noise and tuning range performance. The tuning range is from 5.05GHZ to 5.88GHz.The phase noise is -154.9dBc/Hz at 1MHz offset from the carrier. It meets the requirements for IEEE 802.11a WLAN standard.

Keywords: CMOS LC VCO, spiral inductor, varactor, phase noise, tuning range

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Authors: Muhammad Saiful Fadhil Reyhan, Yusnita Rahayu, Fadhel Muhammadsyah

Abstract:

This paper proposed a design of 16 elements, 8x2 linear fed patch antenna array with 16 ports, for 28 GHz, mm-wave band 5G for base station. The phased array covers along the azimuth plane to provide the coverage to the users in omnidirectional. The proposed antenna is designed RT Duroid 5880 substrate with the overall size of 85x35.6x0.787 mm³. The array is operating from 27.43 GHz to 28.34 GHz with a 910 MHz impedance bandwidth. The gain of the array is 18.3 dB, while the suppression of the side lobes is -1.0 dB. The main lobe direction of the array is 15 deg. The array shows a high array gain throughout the impedance bandwidth with overall of VSWR is below 1.12. The design will be proposed in single element and 16 elements antenna.

Keywords: 5G antenna, 28 GHz, MIMO, omnidirectional, phased array, base station, broadband

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Ghoname Abdullah, Hidekazu Nishimura

Abstract:

Dust accumulation on the photovoltaic module's surface results in appreciable loss and negatively affects the generated power. Hence, in this paper, the design of a photovoltaic array cleaning system is presented. The cleaning system utilizes one drive motor, two guide rails, and four sweepers during the cleaning process. The cleaning system was experimentally implemented for one month to investigate its efficiency on PV array energy output. The energy capture over a month for PV array cleaned using the proposed cleaning system is compared with that of the energy capture using soiled PV array. The results show a 15% increase in energy generation from PV array with cleaning. From the results, investigating the optimal scheduling of the PV array cleaning could be an interesting research topic.

Keywords: cleaning system, dust accumulation, PV array, PV module, soiling

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Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, phase shifter, backhaul, 802.11ac

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS process sensor, PVT sensor, threshold extractor circuit, Vth extractor circuit

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Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter

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Authors: D. J. Dahigaonkar, D. G. Wakde

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The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper.

Keywords: Operational Transconductance Amplifier, Total Harmonic Distortions, low voltage/low power, power dissipation

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Authors: Lei Hou, Xinli Du, Nikolaos Boulgouris

Abstract:

A cochlear implant, referred to as a CI, is a small electronic device that can provide direct electrical stimulation to the auditory nerve. During cochlear implant surgery, atraumatic electrode array insertion is considered to be a crucial step. However, during implantation, the mechanical behaviour of an electrode array inside the cochlea is not known. The behaviour of an electrode array inside of the cochlea is hardly identified by regular methods. In this study, a CI electrode array capacitive sensor system is proposed. It is able to automatically determine the array state as a result of the capacitance variations. Instead of applying sensors to the electrode array, the capacitance information from the electrodes will be gathered and analysed. Results reveal that this sensing method is capable of recognising different states when fed into a pre-shaped model.

Keywords: cochlear implant, electrode, hearing preservation, insertion force, capacitive sensing

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Authors: Mohamed Adel Abdallah

Abstract:

A high voltage magnetic pulse is designed by applying an electrical pulse to the coil. Capacitor banks are developed to generate a pulse current. Switching circuit consisting of DPDT switches, thyristor, and triggering circuit is built and tested. The coil current is measured using a Hall-effect current sensor. The magnetic pulse created is measured and tabulated in the graph. Simulation using FEMM is done to compare the results obtained between experiment and simulation. This technology can be applied to area such as medical equipment, measuring instrument, and military equipment.

Keywords: high voltage, magnetic pulse, capacitor discharge, coil

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Authors: Rajesh Bera, Durbadal Mandal, Rajib Kar, Sakti P. Ghoshal

Abstract:

This paper describes optimal thinning of an Elliptical Cylindrical Array (ECA) of uniformly excited isotropic antennas which can generate directive beam with minimum relative Side Lobe Level (SLL). The Particle Swarm Optimization (PSO) method, which represents a new approach for optimization problems in electromagnetic, is used in the optimization process. The PSO is used to determine the optimal set of ‘ON-OFF’ elements that provides a radiation pattern with maximum SLL reduction. Optimization is done without prefixing the value of First Null Beam Width (FNBW). The variation of SLL with element spacing of thinned array is also reported. Simulation results show that the number of array elements can be reduced by more than 50% of the total number of elements in the array with a simultaneous reduction in SLL to less than -27dB.

Keywords: thinned array, Particle Swarm Optimization, Elliptical Cylindrical Array, Side Lobe Label.

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Authors: S. Oladoyinbo, A. A. Tijani

Abstract:

Multilevel inverters (MLI) are used at high power application based on their operation. There are 3 main types of multilevel inverters (MLI); diode clamped, flying capacitor and cascaded MLI. A cascaded MLI requires the least number of components to achieve same number of voltage levels when compared to other types of MLI while the flying capacitor has the minimum harmonic distortion. However, maximizing the advantage of cascaded H-bridge MLI and flying capacitor MLI, an improved MLI can be achieved with fewer components and better performance. In this paper an improved MLI is presented by asymmetrically integrating a flying capacitor to a cascaded H-bridge MLI also integrating an auxiliary transformer to the main transformer to decrease the total harmonics distortion (THD) with increased number of output voltage levels. Furthermore, the system is incorporated with a hybrid time and climate based solar panel cleaner and power selector which intelligently manage the input of the MLI and clean the solar panel weekly ensuring the environmental factor effect on the panel is reduced to minimum.

Keywords: multilevel inverter, total harmonics distortion, cascaded h-bridge inverter, flying capacitor

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Authors: Hafez Fouad

Abstract:

Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %.

Keywords: energy harvesting, embedded system, IoT telemedicine system, threshold voltage minimization, differential drive cmos rectifier, full-wave fully gate cross-coupled rectifiers CMOS rectifier

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Authors: Mohammad Arif Sobhan Bhuiyan, Mamun Bin Ibne Reaz

Abstract:

The rapid advancement of CMOS technology, in the recent years, has led the scientists to fabricate wireless transceivers fully on-chip which results in smaller size and lower cost wireless communication devices with acceptable performance characteristics. Moreover, the performance of the wireless transceivers rigorously depends on the performance of its first block T/R switch. This article proposes a design of a high performance T/R switch for 2.4 GHz RF wireless transceivers in 0.13 µm CMOS technology. The switch exhibits 1- dB insertion loss, 37.2-dB isolation in transmit mode and 1.4-dB insertion loss, 25.6-dB isolation in receive mode. The switch has a power handling capacity (P1dB) of 30.9-dBm. Besides, by avoiding bulky inductors and capacitors, the size of the switch is drastically reduced and it occupies only (0.00296) mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit will trim down the cost of fabrication as well as the whole transceiver.

Keywords: CMOS, ISM band, SPDT, t/r switch, transceiver

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Authors: Yasunori Kobori, Li Quan, Shu Wu, Nizam Mohyar, Zachary Nosker, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi

Abstract:

This paper proposes an electrolytic capacitor-less transformer-less AC-DC LED driver with a current ripple canceller. The proposed LED driver includes a diode bridge, a buck-boost converter, a negative feedback controller and a current ripple cancellation circuit. The current ripple canceller works as a bi-directional current converter using a sub-inductor, a sub-capacitor and two switches for controlling current flow. LED voltage is controlled in order to regulate LED current by the negative feedback controller using a current sense resistor. There are two capacitors which capacitance of 5 uF. We describe circuit topologies, operation principles and simulation results for our proposed circuit. In addition, we show the line regulation for input voltage variation from 85V to 130V. The output voltage ripple is 2V and the LED current ripple is 65 mA which is less than 20% of the typical current of 350 mA. We are now making the proposed circuit on a universal board in order to measure the experimental characteristics.

Keywords: LED driver, electrolytic, capacitor-less, AC-DC converter, buck-boost converter, current ripple canceller

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Authors: Bachir Belmadani, Rachid Taleb, Zinelaabidine Boudjema, Adil Yahdou

Abstract:

Carrier-based methods have been used widely for switching of multilevel inverters due to their simplicity, flexibility and reduced computational requirements compared to space vector modulation (SVM). This paper focuses on Multicarrier Sinusoidal Pulse Width Modulation (MCSPWM) strategy for the three phase Five-Level Flying Capacitor Inverter (5LFCI). The inverter is simulated for Induction Motor (IM) load and Total Harmonic Distortion (THD) for output waveforms is observed for different controlling schemes.

Keywords: flying capacitor inverter, multicarrier sinusoidal pulse width modulation, space vector modulation, total harmonic distortion, induction motor

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Authors: Yo-Sheng Lin, Jen-How Lee, Chien-Chin Wang

Abstract:

A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA), and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential (STD) converter, an LO Marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4 GHz to 65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are -33.1 dBm and -23.3 dBm, respectively, at 60 GHz. These results demonstrate the proposed receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications.

Keywords: CMOS, 60 GHz, direct-conversion transceiver, LNA, down-conversion mixer, marchand balun, current-reused

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Authors: Madina Hamiane

Abstract:

Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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Authors: N. Ojaroudi Parchin, H. Jahanbakhsh Basherlou, Y. Al-Yasir, A. M. Abdulkhaleq, R. A. Abd-Alhameed, P. S. Excell

Abstract:

A compact design of multi-sector patch antenna array for 60 GHz applications is presented and discussed in details. The proposed design combines five 1×8 linear patch antenna arrays, referred to as sectors, in a multi-sector configuration. The coaxial-fed radiation elements of the multi-sector array are designed on 0.2 mm Rogers RT5880 dielectrics. The array operates in the frequency range of 58-62 GHz and provides switchable directional/omnidirectional radiation beams with high gain and high directivity characteristics. The designed multi-sector array exhibits good performances and could be used in the fifth generation (5G) cellular networks.

Keywords: mm-wave communications, multi-sector array, patch antenna, small cell networks

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, Shivesh Tripathi, V. S. Tripathi

Abstract:

In this paper, a patch antenna array design is proposed for vehicular communication. The antenna consists of 2-element patch array. The antenna array is operating at multiple frequency bands. The multiband operation is achieved by use of slots at proper locations at the patch. The array is made reconfigurable by use of two PIN-diodes. The antenna is simulated and measured in four states of diodes i.e. ON-ON, ON-OFF, OFF-ON, and OFF-OFF. In ON-ON state of diodes, the resonant frequencies are 4.62-4.96, 6.50-6.75, 6.90-7.01, 7.34-8.22, 8.89-9.09 GHz. In ON-OFF state of diodes, the measured resonant frequencies are 4.63-4.93, 6.50-6.70 and 7.81-7.91 GHz. In OFF-ON states of diodes the resonant frequencies are 1.24-1.46, 3.40-3.75, 5.07-5.25 and 6.90-7.20 GHz and in the OFF-OFF state of diodes 4.49-4.75 and 5.61-5.98 GHz. The maximum bandwidth of the proposed antenna is 16.29%. The peak gain of the antenna is 3.4 dB at 5.9 GHz, which makes it suitable for vehicular communication.

Keywords: antenna, array, reconfigurable, vehicular

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Authors: Somayeh Komeylian

Abstract:

The antenna arrays for the entire 3D spherical coverage have been developed for their potential use in variety of applications such as radars and body-worn devices of the body area networks. In this study, we have rigorously revamped the hybrid antenna array using the optimum geometry of bowtie elements for achieving a significant improvement in the angular discrimination capability as well as in separating two adjacent targets. In this scenario, we have analogously investigated the effectiveness of increasing the virtual array length in fostering and enhancing the directivity and angular resolution in the 10 GHz frequency. The simulation results have extensively verified that the proposed antenna array represents a drastic enhancement in terms of size, directivity, side lobe level (SLL) and, especially resolution compared with the other available geometries. We have also verified that the maximum directivities of the proposed hybrid antenna array represent the robustness to the all  variations, which is accompanied by the uniform 3D scanning characteristic.

Keywords: bowtie antenna, hybrid antenna array, array signal processing, body area networks

Procedia PDF Downloads 123