Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 65

Search results for: sapphire wafer

65 Property of Diamond Coated Tools for Lapping Single-Crystal Sapphire Wafer

Authors: Feng Wei, Lu Wenzhuang, Cai Wenjun, Yu Yaping, Basnet Rabin, Zuo Dunwen


Diamond coatings were prepared on cemented carbide by hot filament chemical vapor deposition (HFCVD) method. Lapping experiment of single-crystal sapphire wafer was carried out using the prepared diamond coated tools. The diamond coatings and machined surface of the sapphire wafer were evaluated by SEM, laser confocal microscope and Raman spectrum. The results indicate that the lapping sapphire chips are small irregular debris and long thread-like debris. There is graphitization of diamond crystal during the lapping process. A low surface roughness can be obtained using a spherical grain diamond coated tool.

Keywords: lapping, nano-micro crystalline diamond coating, Raman spectrum, sapphire

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64 Study of Fork Marks on Sapphire Wafers in Plasma Enhanced Chemical Vapor Deposition Tool

Authors: Qiao Pei Wen, Ng Seng Lee, Sae Tae Veera, Chiu Ah Fong, Loke Weng Onn


Thin film thickness uniformity is crucial to get consistent film etch rate and device yield across the wafer. In the capacitive-coupled parallel plate PECVD system; the film thickness uniformity can be affected by many factors such as the heater temperature uniformity, the spacing between top and bottom electrode, RF power, pressure, gas flows and etc. In this paper, we studied how the PECVD SiN film thickness uniformity is affected by the substrate electrical conductivity and the RF power coupling efficiency. PECVD SiN film was deposited on 150-mm sapphire wafers in 200-mm Lam Sequel tool, fork marks were observed on the wafers. On the fork marks area SiN film thickness is thinner than that on the non-fork area. The forks are the wafer handler inside the process chamber to move the wafers from one station to another. The sapphire wafers and the ceramic forks both are insulator. The high resistivity of the sapphire wafers and the forks inhibits the RF power coupling efficiency during PECVD deposition, thereby reducing the deposition rate. Comparing between the high frequency and low frequency RF power (HFRF and LFRF respectively), the LFRF power coupling effect on the sapphire wafers is more dominant than the HFRF power on the film thickness. This paper demonstrated that the SiN thickness uniformity on sapphire wafers can be improved by depositing a thin TiW layer on the wafer before the SiN deposition. The TiW layer can be on the wafer surface, bottom or any layer before SiN deposition.

Keywords: PECVD SiN deposition, sapphire wafer, substrate electrical conductivity, RF power coupling, high frequency RF power, low frequency RF power, film deposition rate, thickness uniformity

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63 N-Type GaN Thinning for Enhancing Light Extraction Efficiency in GaN-Based Thin-Film Flip-Chip Ultraviolet (UV) Light Emitting Diodes (LED)

Authors: Anil Kawan, Soon Jae Yu, Jong Min Park


GaN-based 365 nm wavelength ultraviolet (UV) light emitting diodes (LED) have various applications: curing, molding, purification, deodorization, and disinfection etc. However, their usage is limited by very low output power, because of the light absorption in the GaN layers. In this study, we demonstrate a method utilizing removal of 365 nm absorption layer buffer GaN and thinning the n-type GaN so as to improve the light extraction efficiency of the GaN-based 365 nm UV LED. The UV flip chip LEDs of chip size 1.3 mm x 1.3 mm were fabricated using GaN epilayers on a sapphire substrate. Via-hole n-type contacts and highly reflective Ag metal were used for efficient light extraction. LED wafer was aligned and bonded to AlN carrier wafer. To improve the extraction efficiency of the flip chip LED, sapphire substrate and absorption layer buffer GaN were removed by using laser lift-off and dry etching, respectively. To further increase the extraction efficiency of the LED, exposed n-type GaN thickness was reduced by using inductively coupled plasma etching.

Keywords: extraction efficiency, light emitting diodes, n-GaN thinning, ultraviolet

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62 The Grinding Influence on the Strength of Fan-Out Wafer-Level Packages

Authors: Z. W. Zhong, C. Xu, W. K. Choi


To build a thin fan-out wafer-level package, the package had to be ground to a thin level. In this work, the influence of the grinding processes on the strength of the fan-out wafer-level packages was investigated. After different grinding processes, all specimens were placed on a three-point-bending fixture installed on a universal tester for three-point-bending testing, and the strength of the fan-out wafer-level packages was measured. The experiments revealed that the average flexure strength increased with the decreasing surface roughness height of the fan-out wafer-level package tested. The grinding processes had a significant influence on the strength of the fan-out wafer-level packages investigated.

Keywords: FOWLP strength, surface roughness, three-point bending, grinding

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61 Experimental Study on Slicing of Sapphire with Fixed Abrasive Diamond Wire Saw

Authors: Mengjun Zhang, Yuli Sun, Dunwen Zuo, Chunxiang Xie, Chunming Zhang


Experimental study on slicing of sapphire with fixed abrasive diamond wire saw was conducted in this paper. The process parameters were optimized through orthogonal experiment of three factors and four levels. The effects of wire speed, feed speed and tension pressure on the surface roughness were analyzed. Surface roughness in cutting direction and feed direction were both detected. The results show that feed speed plays the most significant role on the surface roughness of sliced sapphire followed by wire speed and tension pressure. The optimized process parameters are as follows: wire speed 1.9 m/s, feed speed 0.187 mm/min and tension pressure 0.18 MPa. In the end, the results were verified by analysis of variance.

Keywords: fixed abrasive, diamond wire saw, slicing, sapphire, orthogonal experiment

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60 Optimal Designof Brush Roll for Semiconductor Wafer Using CFD Analysis

Authors: Byeong-Sam Kim, Kyoungwoo Park


This research analyzes structure of flat panel display (FPD) such as LCD as quantitative through CFD analysis and modeling change to minimize the badness rate and rate of production decrease by damage of large scale plater at wafer heating chamber at semi-conductor manufacturing process. This glass panel and wafer device with atmospheric pressure or chemical vapor deposition equipment for transporting and transferring wafers, robot hands carry these longer and wider wafers can also be easily handled. As a contact handling system composed of several problems in increased potential for fracture or warping. A non-contact handling system is required to solve this problem. The panel and wafer warping makes it difficult to carry out conventional contact to analysis. We propose a new non-contact transportation system with combining air suction and blowout. The numerical analysis and experimental is, therefore, should be performed to obtain compared to results achieved with non-contact solutions. This wafer panel noncontact handler shows its strength in maintaining high cleanliness levels for semiconductor production processes.

Keywords: flat panel display, non contact transportation, heat treatment process, CFD analysis

Procedia PDF Downloads 339
59 Preparation of CuAlO2 Thin Films on Si or Sapphire Substrate by Sol-Gel Method Using Metal Acetate or Nitrate

Authors: Takashi Ehara, Takayoshi Nakanishi, Kohei Sasaki, Marina Abe, Hiroshi Abe, Kiyoaki Abe, Ryo Iizaka, Takuya Sato


CuAlO2 thin films are prepared on Si or sapphire substrate by sol-gel method using two kinds of sols. One is combination of Cu acetate and Al acetate basic, and the other is Cu nitrate and Al nitrate. In the case of acetate sol, XRD peaks of CuAlO2 observed at annealing temperature of 800-950 ºC on both Si and sapphire substrates. In contrast, in the case of the films prepared using nitrate on Si substrate, XRD peaks of CuAlO2 have been observed only at the annealing temperature of 800-850 ºC. At annealing temperature of 850ºC, peaks of other species have been observed beside the CuAlO2 peaks, then, the CuAlO2 peaks disappeared at annealing temperature of 900 °C with increasing in intensity of the other peaks. Intensity of the other peaks decreased at annealing temperature of 950 ºC with appearance of broad SiO2 peak. In the present, we ascribe these peaks as metal silicide.

Keywords: CuAlO2, silicide, thin Films, transparent conducting oxide

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58 Two-Dimensional WO₃ and TiO₂ Semiconductor Oxides Developed by Atomic Layer Deposition with Controllable Nano-Thickness on Wafer-Scale

Authors: S. Zhuiykov, Z. Wei


Conformal defect-free two-dimensional (2D) WO₃ and TiO₂ semiconductors have been developed by the atomic layer deposition (ALD) technique on wafer scale with unique approach to the thickness control with precision of ± 10% from the monolayer of nanomaterial (less than 1.0 nm thick) to the nano-layered 2D structures with thickness of ~3.0-7.0 nm. Developed 2D nanostructures exhibited unique, distinguishable properties at nanoscale compare to their thicker counterparts. Specifically, 2D TiO₂-Au bilayer demonstrated improved photocatalytic degradation of palmitic acid under UV and visible light illumination. Improved functional capabilities of 2D semiconductors would be advantageous to various environmental, nano-energy and bio-sensing applications. The ALD-enabled approach is proven to be versatile, scalable and applicable to the broader range of 2D semiconductors.

Keywords: two-dimensional (2D) semiconductors, ALD, WO₃, TiO₂, wafer scale

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57 Development of 420 mm Diameter Silicon Crystal Growth Using Continuous Czochralski Process

Authors: Ilsun Pang, Kwanghun Kim, Sungsun Baik


Large diameter Si wafer is used as semiconductor substrate. Large diameter Si crystal ingot should be needed in order to increase wafer size. To make convection of large silicon melt stable, magnetic field is normally applied, but magnetic field is expensive and it is not proper to stabilize the large Si melt. To solve the problem, we propose a continuous Czochralski process which can be applied to small melt without magnetic field. We used granule poly, which has size distribution of 1~3 mm and is easily supplied in double crucible during silicon ingot growth. As the result, we produced 420 mm diameter ingot. In this paper, we describe an experimental study on crystal growth of large diameter silicon by Continuous Czochralski process.

Keywords: Czochralski, ingot, silicon crystal, wafer

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56 Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim


Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: fast vs slow BTI, fast wafer level reliability (FWLR), negative bias temperature instability (NBTI), NBTI measurement system, metal-oxide-semiconductor field-effect transistor (MOSFET), NBTI recovery, reliability

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55 A Spatial Point Pattern Analysis to Recognize Fail Bit Patterns in Semiconductor Manufacturing

Authors: Youngji Yoo, Seung Hwan Park, Daewoong An, Sung-Shick Kim, Jun-Geol Baek


The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.

Keywords: semiconductor, wafer bin map, feature extraction, spatial point patterns, contour map

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54 Controlled Nano Texturing in Silicon Wafer for Excellent Optical and Photovoltaic Properties

Authors: Deb Kumar Shah, M. Shaheer Akhtar, Ha Ryeon Lee, O-Bong Yang, Chong Yeal Kim


The crystalline silicon (Si) solar cells are highly renowned photovoltaic technology and well-established as the commercial solar technology. Most of the solar panels are globally installed with the crystalline Si solar modules. At the present scenario, the major photovoltaic (PV) market is shared by c-Si solar cells, but the cost of c-Si panels are still very high as compared with the other PV technology. In order to reduce the cost of Si solar panels, few necessary steps such as low-cost Si manufacturing, cheap antireflection coating materials, inexpensive solar panel manufacturing are to be considered. It is known that the antireflection (AR) layer in c-Si solar cell is an important component to reduce Fresnel reflection for improving the overall conversion efficiency. Generally, Si wafer exhibits the 30% reflection because it normally poses the two major intrinsic drawbacks such as; the spectral mismatch loss and the high Fresnel reflection loss due to the high contrast of refractive indices between air and silicon wafer. In recent years, researchers and scientists are highly devoted to a lot of researches in the field of searching effective and low-cost AR materials. Silicon nitride (SiNx) is well-known AR materials in commercial c-Si solar cells due to its good deposition and interaction with passivated Si surfaces. However, the deposition of SiNx AR is usually performed by expensive plasma enhanced chemical vapor deposition (PECVD) process which could have several demerits like difficult handling and damaging the Si substrate by plasma when secondary electrons collide with the wafer surface for AR coating. It is very important to explore new, low cost and effective AR deposition process to cut the manufacturing cost of c-Si solar cells. One can also be realized that a nano-texturing process like the growth of nanowires, nanorods, nanopyramids, nanopillars, etc. on Si wafer can provide a low reflection on the surface of Si wafer based solar cells. The above nanostructures might be enhanced the antireflection property which provides the larger surface area and effective light trapping. In this work, we report on the development of crystalline Si solar cells without using the AR layer. The Silicon wafer was modified by growing nanowires like Si nanostructures using the wet controlled etching method and directly used for the fabrication of Si solar cell without AR. The nanostructures over Si wafer were optimized in terms of sizes, lengths, and densities by changing the etching conditions. Well-defined and aligned wires like structures were achieved when the etching time is 20 to 30 min. The prepared Si nanostructured displayed the minimum reflectance ~1.64% at 850 nm with the average reflectance of ~2.25% in the wavelength range from 400-1000 nm. The nanostructured Si wafer based solar cells achieved the comparable power conversion efficiency in comparison with c-Si solar cells with SiNx AR layer. From this study, it is confirmed that the reported method (controlled wet etching) is an easy, facile method for preparation of nanostructured like wires on Si wafer with low reflectance in the whole visible region, which has greater prospects in developing c-Si solar cells without AR layer at low cost.

Keywords: chemical etching, conversion efficiency, silicon nanostructures, silicon solar cells, surface modification

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53 Laser-Dicing Modeling: Implementation of a High Accuracy Tool for Laser-Grooving and Cutting Application

Authors: Jeff Moussodji, Dominique Drouin


The highly complex technology requirements of today’s integrated circuits (ICs), lead to the increased use of several materials types such as metal structures, brittle and porous low-k materials which are used in both front end of line (FEOL) and back end of line (BEOL) process for wafer manufacturing. In order to singulate chip from wafer, a critical laser-grooving process, prior to blade dicing, is used to remove these layers of materials out of the dicing street. The combination of laser-grooving and blade dicing allows to reduce the potential risk of induced mechanical defects such micro-cracks, chipping, on the wafer top surface where circuitry is located. It seems, therefore, essential to have a fundamental understanding of the physics involving laser-dicing in order to maximize control of these critical process and reduce their undesirable effects on process efficiency, quality, and reliability. In this paper, the study was based on the convergence of two approaches, numerical and experimental studies which allowed us to investigate the interaction of a nanosecond pulsed laser and BEOL wafer materials. To evaluate this interaction, several laser grooved samples were compared with finite element modeling, in which three different aspects; phase change, thermo-mechanical and optic sensitive parameters were considered. The mathematical model makes it possible to highlight a groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat affected zone, and thermo-mechanical stress can be also predicted as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a satisfying correlation between experiment and modeling, results have been observed in terms of groove depth, width and heat affected zone. The study proposed in this work is a first step toward implementing a quick assessment tool for design and debug of multiple laser grooving conditions with limited experiments on hardware in industrial application. More correlations and validation tests are in progress and will be included in the full paper.

Keywords: laser-dicing, nano-second pulsed laser, wafer multi-stack, multiphysics modeling

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52 Modeling and Simulation of Pad Surface Topography by Diamond Dressing in Chemical-Mechanical Polishing Process

Authors: A.Chen Chao-Chang, Phong Pham-Quoc


Chemical-mechanical polishing (CMP) process has been widely applied on fabricating integrated circuits (IC) with a soft polishing pad combined with slurry composed of micron or nano-scaled abrasives for generating chemical reaction to remove substrate or film materials from wafer. During CMP process, pad uniformity usually works as a datum surface of wafer planarization and pad asperities can dominate the microscopic pad-slurry-wafer interaction. However, pad topography can be changed by related mechanism factors of CMP and it needs to be re-conditioned or dressed by a diamond dresser of well-distributed diamond grits on a disc surface. It is still very complicated to analyze and understand kinematic of diamond dressing process under the effects of input variables including oscillatory of diamond dresser and rotation speed ratio between the pad and the diamond dresser. This paper has developed a generic geometric model to clarify the kinematic modeling of diamond dressing processes such as dresser/pad motion, pad cutting locus, the relative velocity of the diamond abrasive grits on pad surface, and overlap of cutting for prediction of pad surface topography. Simulation results focus on comparing and analysis kinematics of the diamond dressing on certain CMP tools. Results have shown the significant parameters for diamond dressing process and also discussed. Future study can apply on diamond dresser design and experimental verification of pad dressing process.

Keywords: kinematic modeling, diamond dresser, pad cutting locus, CMP

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51 Optimum Dispatching Rule in Solar Ingot-Wafer Manufacturing System

Authors: Wheyming Song, Hung-Hsiang Lin, Scott Lian


In this research, we investigate the optimal dispatching rule for machines and manpower allocation in the solar ingot-wafer systems. The performance of the method is measured by the sales profit for each dollar paid to the operators in a one week at steady-state. The decision variables are identification-number of machines and operators when each job is required to be served in each process. We propose a rule which is a function of operator’s ability, corresponding salary, and standing location while in the factory. The rule is named ‘Multi-nominal distribution dispatch rule’. The proposed rule performs better than many traditional rules including generic algorithm and particle swarm optimization. Simulation results show that the proposed Multi-nominal distribution dispatch rule improvement on the sales profit dramatically.

Keywords: dispatching, solar ingot, simulation, flexsim

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50 Tuning the Surface Roughness of Patterned Nanocellulose Films: An Alternative to Plastic Based Substrates for Circuit Priniting in High-Performance Electronics

Authors: Kunal Bhardwaj, Christine Browne


With the increase in global awareness of the environmental impacts of plastic-based products, there has been a massive drive to reduce our use of these products. Use of plastic-based substrates in electronic circuits has been a matter of concern recently. Plastics provide a very smooth and cheap surface for printing high-performance electronics due to their non-permeability to ink and easy mouldability. In this research, we explore the use of nano cellulose (NC) films in electronics as they provide an advantage of being 100% recyclable and eco-friendly. The main hindrance in the mass adoption of NC film as a substitute for plastic is its higher surface roughness which leads to ink penetration, and dispersion in the channels on the film. This research was conducted to tune the RMS roughness of NC films to a range where they can replace plastics in electronics(310-470nm). We studied the dependence of the surface roughness of the NC film on the following tunable aspects: 1) composition by weight of the NC suspension that is sprayed on a silicon wafer 2) the width and the depth of the channels on the silicon wafer used as a base. Various silicon wafers with channel depths ranging from 6 to 18 um and channel widths ranging from 5 to 500um were used as a base. Spray coating method for NC film production was used and two solutions namely, 1.5wt% NC and a 50-50 NC-CNC (cellulose nanocrystal) mixture in distilled water, were sprayed through a Wagner sprayer system model 117 at an angle of 90 degrees. The silicon wafer was kept on a conveyor moving at a velocity of 1.3+-0.1 cm/sec. Once the suspension was uniformly sprayed, the mould was left to dry in an oven at 50°C overnight. The images of the films were taken with the help of an optical profilometer, Olympus OLS 5000. These images were converted into a ‘.lext’ format and analyzed using Gwyddion, a data and image analysis software. Lowest measured RMS roughness of 291nm was with a 50-50 CNC-NC mixture, sprayed on a silicon wafer with a channel width of 5 µm and a channel depth of 12 µm. Surface roughness values of 320+-17nm were achieved at lower (5 to 10 µm) channel widths on a silicon wafer. This research opened the possibility of the usage of 100% recyclable NC films with an additive (50% CNC) in high-performance electronics. Possibility of using additives like Carboxymethyl Cellulose (CMC) is also being explored due to the hypothesis that CMC would reduce friction amongst fibers, which in turn would lead to better conformations amongst the NC fibers. CMC addition would thus be able to help tune the surface roughness of the NC film to an even greater extent in future.

Keywords: nano cellulose films, electronic circuits, nanocrystals and surface roughness

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49 Silicon-To-Silicon Anodic Bonding via Intermediate Borosilicate Layer for Passive Flow Control Valves

Authors: Luc Conti, Dimitry Dumont-Fillon, Harald van Lintel, Eric Chappel


Flow control valves comprise a silicon flexible membrane that deflects against a substrate, usually made of glass, containing pillars, an outlet hole, and anti-stiction features. However, there is a strong interest in using silicon instead of glass as substrate material, as it would simplify the process flow by allowing the use of well controlled anisotropic etching. Moreover, specific devices demanding a bending of the substrate would also benefit from the inherent outstanding mechanical strength of monocrystalline silicon. Unfortunately, direct Si-Si bonding is not easily achieved with highly structured wafers since residual stress may prevent the good adhesion between wafers. Using a thermoplastic polymer, such as parylene, as intermediate layer is not well adapted to this design as the wafer-to-wafer alignment is critical. An alternative anodic bonding method using an intermediate borosilicate layer has been successfully tested. This layer has been deposited onto the silicon substrate. The bonding recipe has been adapted to account for the presence of the SOI buried oxide and intermediate glass layer in order not to exceed the breakdown voltage. Flow control valves dedicated to infusion of viscous fluids at very high pressure have been made and characterized. The results are compared to previous data obtained using the standard anodic bonding method.

Keywords: anodic bonding, evaporated glass, flow control valve, drug delivery

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48 Wetting Characterization of High Aspect Ratio Nanostructures by Gigahertz Acoustic Reflectometry

Authors: C. Virgilio, J. Carlier, P. Campistron, M. Toubal, P. Garnier, L. Broussous, V. Thomy, B. Nongaillard


Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real challenge in integrated circuits manufacturing. In fact, bad or non-uniform wetting during wet processes limits chemical reactions and can lead to non-complete etching or cleaning inside the patterns and device defectivity. This issue is more and more important with the transistors size shrinkage and concerns mainly high aspect ratio structures. Deep Trench Isolation (DTI) structures enabling pixels’ isolation in imaging devices are subject to this phenomenon. While low-frequency acoustic reflectometry principle is a well-known method for Non Destructive Test applications, we have recently shown that it is also well suited for nanostructures wetting characterization in a higher frequency range. In this paper, we present a high-frequency acoustic reflectometry characterization of DTI wetting through a confrontation of both experimental and modeling results. The acoustic method proposed is based on the evaluation of the reflection of a longitudinal acoustic wave generated by a 100 µm diameter ZnO piezoelectric transducer sputtered on the silicon wafer backside using MEMS technologies. The transducers have been fabricated to work at 5 GHz corresponding to a wavelength of 1.7 µm in silicon. The DTI studied structures, manufactured on the wafer frontside, are crossing trenches of 200 nm wide and 4 µm deep (aspect ratio of 20) etched into a Si wafer frontside. In that case, the acoustic signal reflection occurs at the bottom and at the top of the DTI enabling its characterization by monitoring the electrical reflection coefficient of the transducer. A Finite Difference Time Domain (FDTD) model has been developed to predict the behavior of the emitted wave. The model shows that the separation of the reflected echoes (top and bottom of the DTI) from different acoustic modes is possible at 5 Ghz. A good correspondence between experimental and theoretical signals is observed. The model enables the identification of the different acoustic modes. The evaluation of DTI wetting is then performed by focusing on the first reflected echo obtained through the reflection at Si bottom interface, where wetting efficiency is crucial. The reflection coefficient is measured with different water / ethanol mixtures (tunable surface tension) deposited on the wafer frontside. Two cases are studied: with and without PFTS hydrophobic treatment. In the untreated surface case, acoustic reflection coefficient values with water show that liquid imbibition is partial. In the treated surface case, the acoustic reflection is total with water (no liquid in DTI). The impalement of the liquid occurs for a specific surface tension but it is still partial for pure ethanol. DTI bottom shape and local pattern collapse of the trenches can explain these incomplete wetting phenomena. This high-frequency acoustic method sensitivity coupled with a FDTD propagative model thus enables the local determination of the wetting state of a liquid on real structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are then detectable with this method.

Keywords: wetting, acoustic reflectometry, gigahertz, semiconductor

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47 Hybrid Recovery of Copper and Silver from Photovoltaic Ribbon and Ag finger of End-Of-Life Solar Panels

Authors: T. Patcharawit, C. Kansomket, N. Wongnaree, W. Kritsrikan, T. Yingnakorn, S. Khumkoa


Recovery of pure copper and silver from end-of-life photovoltaic panels was investigated in this paper using an effective hybrid pyro-hydrometallurgical process. In the first step of waste treatment, solar panel waste was first dismantled to obtain a PV sheet to be cut and calcined at 500°C, to separate out PV ribbon from glass cullet, ash, and volatile while the silicon wafer containing silver finger was collected for recovery. In the second step of metal recovery, copper recovery from photovoltaic ribbon was via 1-3 M HCl leaching with SnCl₂ and H₂O₂ additions in order to remove the tin-lead coating on the ribbon. The leached copper band was cleaned and subsequently melted as an anode for the next step of electrorefining. Stainless steel was set as the cathode with CuSO₄ as an electrolyte, and at a potential of 0.2 V, high purity copper of 99.93% was obtained at 96.11% recovery after 24 hours. For silver recovery, the silicon wafer containing silver finger was leached using HNO₃ at 1-4 M in an ultrasonic bath. In the next step of precipitation, silver chloride was then obtained and subsequently reduced by sucrose and NaOH to give silver powder prior to oxy-acetylene melting to finally obtain pure silver metal. The integrated recycling process is considered to be economical, providing effective recovery of high purity metals such as copper and silver while other materials such as aluminum, copper wire, glass cullet can also be recovered to be reused commercially. Compounds such as PbCl₂ and SnO₂ obtained can also be recovered to enter the market.

Keywords: electrorefining, leaching, calcination, PV ribbon, silver finger, solar panel

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46 Nanofluidic Cell for Resolution Improvement of Liquid Transmission Electron Microscopy

Authors: Deybith Venegas-Rojas, Sercan Keskin, Svenja Riekeberg, Sana Azim, Stephanie Manz, R. J. Dwayne Miller, Hoc Khiem Trieu


Liquid Transmission Electron Microscopy (TEM) is a growing area with a broad range of applications from physics and chemistry to material engineering and biology, in which it is possible to image in-situ unseen phenomena. For this, a nanofluidic device is used to insert the nanoflow with the sample inside the microscope in order to keep the liquid encapsulated because of the high vacuum. In the last years, Si3N4 windows have been widely used because of its mechanical stability and low imaging contrast. Nevertheless, the pressure difference between the inside fluid and the outside vacuum in the TEM generates bulging in the windows. This increases the imaged fluid volume, which decreases the signal to noise ratio (SNR), limiting the achievable spatial resolution. With the proposed device, the membrane is fortified with a microstructure capable of stand higher pressure differences, and almost removing completely the bulging. A theoretical study is presented with Finite Element Method (FEM) simulations which provide a deep understanding of the membrane mechanical conditions and proves the effectiveness of this novel concept. Bulging and von Mises Stress were studied for different membrane dimensions, geometries, materials, and thicknesses. The microfabrication of the device was made with a thin wafer coated with thin layers of SiO2 and Si3N4. After the lithography process, these layers were etched (reactive ion etching and buffered oxide etch (BOE) respectively). After that, the microstructure was etched (deep reactive ion etching). Then the back side SiO2 was etched (BOE) and the array of free-standing micro-windows was obtained. Additionally, a Pyrex wafer was patterned with windows, and inlets/outlets, and bonded (anodic bonding) to the Si side to facilitate the thin wafer handling. Later, a thin spacer is sputtered and patterned with microchannels and trenches to guide the nanoflow with the samples. This approach reduces considerably the common bulging problem of the window, improving the SNR, contrast and spatial resolution, increasing substantially the mechanical stability of the windows, allowing a larger viewing area. These developments lead to a wider range of applications of liquid TEM, expanding the spectrum of possible experiments in the field.

Keywords: liquid cell, liquid transmission electron microscopy, nanofluidics, nanofluidic cell, thin films

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45 Imaging 255nm Tungsten Thin Film Adhesion with Picosecond Ultrasonics

Authors: A. Abbas, X. Tridon, J. Michelon


In the electronic or in the photovoltaic industries, components are made from wafers which are stacks of thin film layers of a few nanometers to serval micrometers thickness. Early evaluation of the bounding quality between different layers of a wafer is one of the challenges of these industries to avoid dysfunction of their final products. Traditional pump-probe experiments, which have been developed in the 70’s, give a partial solution to this problematic but with a non-negligible drawback. In fact, on one hand, these setups can generate and detect ultra-high ultrasounds frequencies which can be used to evaluate the adhesion quality of wafer layers. But, on the other hand, because of the quiet long acquisition time they need to perform one measurement, these setups remain shut in punctual measurement to evaluate global sample quality. This last point can lead to bad interpretation of the sample quality parameters, especially in the case of inhomogeneous samples. Asynchronous Optical Sampling (ASOPS) systems can perform sample characterization with picosecond acoustics up to 106 times faster than traditional pump-probe setups. This last point allows picosecond ultrasonic to unlock the acoustic imaging field at the nanometric scale to detect inhomogeneities regarding sample mechanical properties. This fact will be illustrated by presenting an image of the measured acoustical reflection coefficients obtained by mapping, with an ASOPS setup, a 255nm thin-film tungsten layer deposited on a silicone substrate. Interpretation of the coefficient reflection in terms of bounding quality adhesion will also be exposed. Origin of zones which exhibit good and bad quality bounding will be discussed.

Keywords: adhesion, picosecond ultrasonics, pump-probe, thin film

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44 The Evaluation for Interfacial Adhesion between SOFC and Metal Adhesive in the High Temperature Environment

Authors: Sang Koo Jeon, Seung Hoon Nahm, Oh Heon Kwon


The unit cell of solid oxide fuel cell (SOFC) must be stacked as several layers type to obtain the high power. The most of researcher have concerned about the performance of stacked SOFC rather than the structural stability of stacked SOFC and especially interested how to design for reducing the electrical loss and improving the high efficiency. Consequently, the stacked SOFC able to produce the electrical high power and related parts like as manifold, gas seal, bipolar plate were developed to optimize the stack design. However, the unit cell of SOFC was just layered on the interconnector without the adhesion and the hydrogen and oxygen were injected to the interfacial layer in the high temperature. On the operating condition, the interfacial layer can be the one of the weak point in the stacked SOFC. Therefore the evaluation of the structural safety for the failure is essentially needed. In this study, interfacial adhesion between SOFC and metal adhesive was estimated in the high temperature environment. The metal adhesive was used to strongly connect the unit cell of SOFC with interconnector and provide the electrical conductivity between them. The four point bending test was performed to measure the interfacial adhesion. The unit cell of SOFC and SiO2 wafer were diced and then attached by metal adhesive. The SiO2 wafer had the center notch to initiate a crack from the tip of the notch. The modified stereomicroscope combined with the CCD camera and system for measuring the length was used to observe the fracture behavior. Additionally, the interfacial adhesion was evaluated in the high temperature condition because the metal adhesive was affected by high temperature. Also the specimen was exposed in the furnace during several hours and then the interfacial adhesion was evaluated. Finally, the interfacial adhesion energy was quantitatively determined and compared in the each condition.

Keywords: solid oxide fuel cell (SOFC), metal adhesive, adhesion, high temperature

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43 A CMOS Capacitor Array for ESPAR with Fast Switching Time

Authors: Jin-Sup Kim, Se-Hwan Choi, Jae-Young Lee


A 8-bit CMOS capacitor array is designed for using in electrically steerable passive array radiator (ESPAR). The proposed capacitor array shows the fast response time in rising and falling characteristics. Compared to other works in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, it shows a comparable tuning range and switching time with low power consumption. Using the 0.18um CMOS, the capacitor array features a tuning range of 1.5 to 12.9 pF at 2.4GHz. Including the 2X4 decoder for control interface, the Chip size is 350um X 145um. Current consumption is about 80 nA at 1.8 V operation.

Keywords: CMOS capacitor array, ESPAR, SOI, SOS, switching time

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42 Two Major Methods to Control Thermal Resistance of Focus Ring for Process Uniformity Enhance

Authors: Jin-Uk Park


Recently, the semiconductor industry is rapidly demanding complicated structures and mass production. From the point of view of mass production, the ETCH industry is concentrating on maintaining the ER (Etch rate) of the wafer edge constant regardless of changes over time. In this study, two major thermal factors affecting process were identified and controlled. First, the filler of the thermal pad was studied. Second, the significant difference of handling the thermal pad during PM was studied.

Keywords: etcher, thermal pad, wet cleaning, thermal conductivity

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41 Mathematical Modeling of the AMCs Cross-Contamination Removal in the FOUPs: Finite Element Formulation and Application in FOUP’s Decontamination

Authors: N. Santatriniaina, J. Deseure, T. Q. Nguyen, H. Fontaine, C. Beitia, L. Rakotomanana


Nowadays, with the increasing of the wafer's size and the decreasing of critical size of integrated circuit manufacturing in modern high-tech, microelectronics industry needs a maximum attention to challenge the contamination control. The move to 300 mm is accompanied by the use of Front Opening Unified Pods for wafer and his storage. In these pods an airborne cross contamination may occur between wafers and the pods. A predictive approach using modeling and computational methods is very powerful method to understand and qualify the AMCs cross contamination processes. This work investigates the required numerical tools which are employed in order to study the AMCs cross-contamination transfer phenomena between wafers and FOUPs. Numerical optimization and finite element formulation in transient analysis were established. Analytical solution of one dimensional problem was developed and the calibration process of physical constants was performed. The least square distance between the model (analytical 1D solution) and the experimental data are minimized. The behavior of the AMCs intransient analysis was determined. The model framework preserves the classical forms of the diffusion and convection-diffusion equations and yields to consistent form of the Fick's law. The adsorption process and the surface roughness effect were also traduced as a boundary condition using the switch condition Dirichlet to Neumann and the interface condition. The methodology is applied, first using the optimization methods with analytical solution to define physical constants, and second using finite element method including adsorption kinetic and the switch of Dirichlet to Neumann condition.

Keywords: AMCs, FOUP, cross-contamination, adsorption, diffusion, numerical analysis, wafers, Dirichlet to Neumann, finite elements methods, Fick’s law, optimization

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40 Radiation Hardness Materials Article Review

Authors: S. Abou El-Azm, U. Kruchonak, M. Gostkin, A. Guskov, A. Zhemchugov


Semiconductor detectors are widely used in nuclear physics and high-energy physics experiments. The application of semiconductor detectors could be limited by their ultimate radiation resistance. The increase of radiation defects concentration leads to significant degradation of the working parameters of semiconductor detectors. The investigation of radiation defects properties in order to enhance the radiation hardness of semiconductor detectors is an important task for the successful implementation of a number of nuclear physics experiments; we presented some information about radiation hardness materials like diamond, sapphire and CdTe. Also, the results of measurements I-V characteristics, charge collection efficiency and its dependence on the bias voltage for different doses of high resistivity (GaAs: Cr) and Si at LINAC-200 accelerator and reactor IBR-2 are presented.

Keywords: semiconductor detectors, radiation hardness, GaAs, Si, CCE, I-V, C-V

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39 Influence of Wavelengths on Photosensitivity of Copper Phthalocyanine Based Photodetectors

Authors: Lekshmi Vijayan, K. Shreekrishna Kumar


We demonstrated an organic field effect transistor based photodetector using phthalocyanine as the active material that exhibited high photosensitivity under varying light wavelengths. The thermally grown SiO₂ layer on silicon wafer act as a substrate. The critical parameters, such as photosensitivity, responsivity and detectivity, are comparatively high and were 3.09, 0.98AW⁻¹ and 4.86 × 10¹⁰ Jones, respectively, under a bias of 5 V and a monochromatic illumination intensity of 4mW cm⁻². The photodetector has a linear I-V curve with a low dark current. On comparing photoresponse of copper phthalocyanine at four different wavelengths, 560 nm shows better photoresponse and the highest value of photosensitivity is also obtained.

Keywords: photodetector, responsivity, photosensitivity, detectivity

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38 Virtual Metrology for Copper Clad Laminate Manufacturing

Authors: Misuk Kim, Seokho Kang, Jehyuk Lee, Hyunchang Cho, Sungzoon Cho


In semiconductor manufacturing, virtual metrology (VM) refers to methods to predict properties of a wafer based on machine parameters and sensor data of the production equipment, without performing the (costly) physical measurement of the wafer properties (Wikipedia). Additional benefits include avoidance of human bias and identification of important factors affecting the quality of the process which allow improving the process quality in the future. It is however rare to find VM applied to other areas of manufacturing. In this work, we propose to use VM to copper clad laminate (CCL) manufacturing. CCL is a core element of a printed circuit board (PCB) which is used in smartphones, tablets, digital cameras, and laptop computers. The manufacturing of CCL consists of three processes: Treating, lay-up, and pressing. Treating, the most important process among the three, puts resin on glass cloth, heat up in a drying oven, then produces prepreg for lay-up process. In this process, three important quality factors are inspected: Treated weight (T/W), Minimum Viscosity (M/V), and Gel Time (G/T). They are manually inspected, incurring heavy cost in terms of time and money, which makes it a good candidate for VM application. We developed prediction models of the three quality factors T/W, M/V, and G/T, respectively, with process variables, raw material, and environment variables. The actual process data was obtained from a CCL manufacturer. A variety of variable selection methods and learning algorithms were employed to find the best prediction model. We obtained prediction models of M/V and G/T with a high enough accuracy. They also provided us with information on “important” predictor variables, some of which the process engineers had been already aware and the rest of which they had not. They were quite excited to find new insights that the model revealed and set out to do further analysis on them to gain process control implications. T/W did not turn out to be possible to predict with a reasonable accuracy with given factors. The very fact indicates that the factors currently monitored may not affect T/W, thus an effort has to be made to find other factors which are not currently monitored in order to understand the process better and improve the quality of it. In conclusion, VM application to CCL’s treating process was quite successful. The newly built quality prediction model allowed one to reduce the cost associated with actual metrology as well as reveal some insights on the factors affecting the important quality factors and on the level of our less than perfect understanding of the treating process.

Keywords: copper clad laminate, predictive modeling, quality control, virtual metrology

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37 Control of Oxide and Silicon Loss during Exposure of Silicon Waveguide

Authors: Gu Zhonghua


Control method of bulk silicon dioxide etching process to approach then expose silicon waveguide has been developed. It has been demonstrated by silicon waveguide of photonics devices. It is also able to generalize other applications. Use plasma dry etching to etch bulk silicon dioxide and approach oxide-silicon interface accurately, then use dilute HF wet etching to etch silicon dioxide residue layer to expose the silicon waveguide as soft landing. Plasma dry etch macro loading effect and endpoint technology was used to determine dry etch time accurately with a low wafer expose ratio.

Keywords: waveguide, etch, control, silicon loss

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36 Solar Cell Using Chemical Bath Deposited PbS:Bi3+ Films as Electron Collecting Layer

Authors: Melissa Chavez Portillo, Mauricio Pacio Castillo, Hector Juarez Santiesteban, Oscar Portillo Moreno


Chemical bath deposited PbS:Bi3+ as an electron collection layer is introduced between the silicon wafer and the Ag electrode the performance of the PbS heterojunction thin film solar thin film solar cells with 1 cm2 active area. We employed Bi-doping to transform it into an n-type semiconductor. The experimental results reveal that the cell response parameters depend critically on the deposition procedures in terms of bath temperature, deposition time. The device achieves an open-circuit voltage of 0.4 V. The simple and low-cost deposition method of PbS:Bi3+ films is promising for the fabrication.

Keywords: Bi doping, PbS, thin films, solar cell

Procedia PDF Downloads 413