Commenced in January 2007
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Edition: International
Paper Count: 8

Search results for: silicide

8 Low-Temperature Poly-Si Nanowire Junctionless Thin Film Transistors with Nickel Silicide

Authors: Yu-Hsien Lin, Yu-Ru Lin, Yung-Chun Wu

Abstract:

This work demonstrates the ultra-thin poly-Si (polycrystalline Silicon) nanowire junctionless thin film transistors (NWs JL-TFT) with nickel silicide contact. For nickel silicide film, this work designs to use two-step annealing to form ultra-thin, uniform and low sheet resistance (Rs) Ni silicide film. The NWs JL-TFT with nickel silicide contact exhibits the good electrical properties, including high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this work also compares the electrical characteristics of NWs JL-TFT with nickel silicide and non-silicide contact. Nickel silicide techniques are widely used for high-performance devices as the device scaling due to the source/drain sheet resistance issue. Therefore, the self-aligned silicide (salicide) technique is presented to reduce the series resistance of the device. Nickel silicide has several advantages including low-temperature process, low silicon consumption, no bridging failure property, smaller mechanical stress, and smaller contact resistance. The junctionless thin-film transistor (JL-TFT) is fabricated simply by heavily doping the channel and source/drain (S/D) regions simultaneously. Owing to the special doping profile, JL-TFT has some advantages such as lower thermal the budget which can integrate with high-k/metal-gate easier than conventional MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), longer effective channel length than conventional MOSFETs, and avoidance of complicated source/drain engineering. To solve JL-TFT has turn-off problem, JL-TFT needs ultra-thin body (UTB) structure to reach fully depleted channel region in off-state. On the other hand, the drive current (Iᴅ) is declined as transistor features are scaled. Therefore, this work demonstrates ultra thin poly-Si nanowire junctionless thin film transistors with nickel silicide contact. This work investigates the low-temperature formation of nickel silicide layer by physical-chemical deposition (PVD) of a 15nm Ni layer on the poly-Si substrate. Notably, this work designs to use two-step annealing to form ultrathin, uniform and low sheet resistance (Rs) Ni silicide film. The first step was promoted Ni diffusion through a thin interfacial amorphous layer. Then, the unreacted metal was lifted off after the first step. The second step was annealing for lower sheet resistance and firmly merged the phase.The ultra-thin poly-Si nanowire junctionless thin film transistors NWs JL-TFT with nickel silicide contact is demonstrated, which reveals high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In silicide film analysis, the second step of annealing was applied to form lower sheet resistance and firmly merge the phase silicide film. In short, the NWs JL-TFT with nickel silicide contact has exhibited a competitive short-channel behavior and improved drive current.

Keywords: poly-Si, nanowire, junctionless, thin-film transistors, nickel silicide

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7 Preparation of Nb Silicide-Based Alloy Powder by Hydrogenation-Dehydrogenation (HDH) Reaction

Authors: Gi-Beom Park, Hyong-Gi Park, Seong-Yong Lee, Jaeho Choi, Seok Hong Min, Tae Kwon Ha

Abstract:

The Nb silicide-based alloy has the excellent high-temperature strength and relatively lower density than the Ni-based superalloy; therefore, it has been receiving a lot of attention for the next generation high-temperature material. To enhance the high temperature creep property and oxidation resistance, Si was added to the Nb-based alloy, resulting in a multi-phase microstructure with metal solid solution and silicide phase. Since the silicide phase has a low machinability due to its brittle nature, it is necessary to fabricate components using the powder metallurgy. However, powder manufacturing techniques for the alloys have not yet been developed. In this study, we tried to fabricate Nb-based alloy powder by the hydrogenation-dehydrogenation reaction. The Nb-based alloy ingot was prepared by vacuum arc melting and it was annealed in the hydrogen atmosphere for the hydrogenation. After annealing, the hydrogen concentration was increased from 0.004wt% to 1.22wt% and Nb metal phase was transformed to Nb hydride phase. The alloy after hydrogenation could be easily pulverized into powder by ball milling due to its brittleness. For dehydrogenation, the alloy powders were annealed in the vacuum atmosphere. After vacuum annealing, the hydrogen concentration was decreased to 0.003wt% and Nb hydride phase was transformed back to Nb metal phase.

Keywords: Nb alloy, Nb metal and silicide composite, powder, hydrogenation-dehydrogenation reaction

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6 Preparation of CuAlO2 Thin Films on Si or Sapphire Substrate by Sol-Gel Method Using Metal Acetate or Nitrate

Authors: Takashi Ehara, Takayoshi Nakanishi, Kohei Sasaki, Marina Abe, Hiroshi Abe, Kiyoaki Abe, Ryo Iizaka, Takuya Sato

Abstract:

CuAlO2 thin films are prepared on Si or sapphire substrate by sol-gel method using two kinds of sols. One is combination of Cu acetate and Al acetate basic, and the other is Cu nitrate and Al nitrate. In the case of acetate sol, XRD peaks of CuAlO2 observed at annealing temperature of 800-950 ºC on both Si and sapphire substrates. In contrast, in the case of the films prepared using nitrate on Si substrate, XRD peaks of CuAlO2 have been observed only at the annealing temperature of 800-850 ºC. At annealing temperature of 850ºC, peaks of other species have been observed beside the CuAlO2 peaks, then, the CuAlO2 peaks disappeared at annealing temperature of 900 °C with increasing in intensity of the other peaks. Intensity of the other peaks decreased at annealing temperature of 950 ºC with appearance of broad SiO2 peak. In the present, we ascribe these peaks as metal silicide.

Keywords: CuAlO2, silicide, thin Films, transparent conducting oxide

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5 Microstructure and Oxidation Behaviors of Al, Y Modified Silicide Coatings Prepared on an Nb-Si Based Ultrahigh Temperature Alloy

Authors: Xiping Guo, Jing Li

Abstract:

The microstructure of an Si-Al-Y co-deposition coating prepared on an Nb-Si based ultra high temperature alloy by pack cementation process at 1250°C for eight hours was studied. The results showed that the coating was composed of a (Nb,X)Si₂ (X represents Ti, Cr and Hf elements) outer layer, a (Ti,Nb)₅Si₄ middle layer and an Al, Cr-rich inner layer. For comparison, the oxidation behaviors of the coating at 800, 1050 and 1350°C were investigated respectively. Linear oxidation kinetics was found with the parabolic rate constants of 5.29×10⁻², 9×10⁻²and 5.81 mg² cm⁻⁴ h⁻¹, respectively. Catastrophic pesting oxidation has not been found at 800°C even for 100 h. The surface of the scale was covered by compact glassy SiO₂ film. The coating was able to effectively protect the Nb-Si based alloy from oxidation at 1350°C for at least 100 h. The formation process of the scale was testified following an epitaxial growth mechanism. The mechanism responsible for the oxidation behavior of the Si-Al-Y co-deposition coating at 800, 1050 and 1350°C was proposed.

Keywords: Nb-Si based ultra high temperature alloy, oxidation resistance, pack cementation, silicide coating, Al and Y modified

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4 Theoretical Investigation of Electronic, Structural and Thermoelectric Properties of Mg₂SiSn (110) Surface

Authors: M. Ramesh, Manish K. Niranjan

Abstract:

The electronic, structural and thermoelectric properties of Mg₂SiSn (110) surface are investigated within the framework of first principle density functional theory and semi classical Boltzmann approach. In particular, directional dependent thermoelectric properties such as electrical conductivity, thermal conductivity, Seebeck coefficient and figure of merit are explored. The (110)-oriented Mg₂SiSn surface exhibits narrow indirect band gap of ~0.17 eV. The thermoelectric properties are found to be significant along the y-axis at 300 K and along x-axis at 500 K. The figure of merit (ZT) for hole carrier concentration is found to be significantly large having magnitude 0.83 (along x-axis) at 500 K and 0.26 (y-axis) at 300 K. Our results suggest that Mg₂SiSn (110) surface is promising for various thermoelectric applications due to its overall good thermoelectric properties.

Keywords: thermoelectric, surface science, semiconducting silicide, first principles calculations

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3 Formation of Protective Silicide-Aluminide Coating on Gamma-TiAl Advanced Material

Authors: S. Nouri

Abstract:

In this study, the Si-aluminide coating was prepared on gamma-TiAl [Ti-45Al-2Nb-2Mn-1B (at. %)] via liquid-phase slurry procedure. The high temperature oxidation resistance of this diffusion coating was evaluated at 1100 °C for 400 hours. The results of the isothermal oxidation showed that the formation of Si-aluminide coating can remarkably improve the high temperature oxidation of bare gamma-TiAl alloy. The identification of oxide scale microstructure showed that the formation of protective Al2O3+SiO2 mixed oxide scale along with a continuous, compact and uniform layer of Ti5Si3 beneath the surface oxide scale can act as an oxygen diffusion barrier during the high temperature oxidation. The other possible mechanisms related to the formation of Si-aluminide coating and oxide scales were also discussed.

Keywords: Gamma-TiAl alloy, high temperature oxidation, Si-aluminide coating, slurry procedure

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2 Effect of Annealing Temperature on Microstructural Evolution of Nanoindented Cu/Si Thin Films

Authors: Woei-Shyan Lee, Yu-Liang Chuang

Abstract:

The nano-mechanical properties of as-deposited Cu/Si thin films indented to a depth of 2000 nm are investigated using a nanoindentation technique. The nanoindented specimens are annealed at a temperature of either 160 °C or 210°C, respectively. The microstructures of the as-deposited and annealed samples are then examined via transmission electron microscopy (TEM). The results show that both the loading and the unloading regions of the load-displacement curve are smooth and continuous, which suggests that no debonding or cracking occurs during nanoindentation. In addition, the hardness and Young’s modulus of the Cu/Si thin films are found to vary with the nanoindentation depth, and have maximum values of 2.8 GPa and 143 GPa, respectively, at the maximum indentation depth of 2000 nm. The TEM observations show that the region of the Cu/Si film beneath the indenter undergoes a phase transformation during the indentation process. In the case of the as-deposited specimens, the indentation pressure induces a completely amorphous phase within the indentation zone. For the specimens annealed at a temperature of 160°C, the amorphous nature of the microstructure within the indented zone is maintained. However, for the specimens annealed at a higher temperature of 210°C, the indentation affected zone consists of a mixture of amorphous phase and nanocrystalline phase. Copper silicide (η-Cu3Si) precipitates are observed in all of the annealed specimens. The density of the η-Cu3Si precipitates is found to increase with an increasing annealing temperature.

Keywords: nanoindentation, Cu/Si thin films, microstructural evolution, annealing temperature

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1 Fabrication of High-Aspect Ratio Vertical Silicon Nanowire Electrode Arrays for Brain-Machine Interfaces

Authors: Su Yin Chiam, Zhipeng Ding, Guang Yang, Danny Jian Hang Tng, Peiyi Song, Geok Ing Ng, Ken-Tye Yong, Qing Xin Zhang

Abstract:

Brain-machine interfaces (BMI) is a ground rich of exploration opportunities where manipulation of neural activity are used for interconnect with myriad form of external devices. These research and intensive development were evolved into various areas from medical field, gaming and entertainment industry till safety and security field. The technology were extended for neurological disorders therapy such as obsessive compulsive disorder and Parkinson’s disease by introducing current pulses to specific region of the brain. Nonetheless, the work to develop a real-time observing, recording and altering of neural signal brain-machine interfaces system will require a significant amount of effort to overcome the obstacles in improving this system without delay in response. To date, feature size of interface devices and the density of the electrode population remain as a limitation in achieving seamless performance on BMI. Currently, the size of the BMI devices is ranging from 10 to 100 microns in terms of electrodes’ diameters. Henceforth, to accommodate the single cell level precise monitoring, smaller and denser Nano-scaled nanowire electrode arrays are vital in fabrication. In this paper, we would like to showcase the fabrication of high aspect ratio of vertical silicon nanowire electrodes arrays using microelectromechanical system (MEMS) method. Nanofabrication of the nanowire electrodes involves in deep reactive ion etching, thermal oxide thinning, electron-beam lithography patterning, sputtering of metal targets and bottom anti-reflection coating (BARC) etch. Metallization on the nanowire electrode tip is a prominent process to optimize the nanowire electrical conductivity and this step remains a challenge during fabrication. Metal electrodes were lithographically defined and yet these metal contacts outline a size scale that is larger than nanometer-scale building blocks hence further limiting potential advantages. Therefore, we present an integrated contact solution that overcomes this size constraint through self-aligned Nickel silicidation process on the tip of vertical silicon nanowire electrodes. A 4 x 4 array of vertical silicon nanowires electrodes with the diameter of 290nm and height of 3µm has been successfully fabricated.

Keywords: brain-machine interfaces, microelectromechanical systems (MEMS), nanowire, nickel silicide

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