Search results for: reconfigurable hardware

Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

Abstract:

The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: B. Kirubakaran, C. Rajasekaran

Abstract:

Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner.

Keywords: field programmable gate array, peripheral interrupt controller, runtime reconfigurable techniques, wireless sensor networks

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Authors: Roscoe McLean, Jared Padayachee, Glen Bright

Abstract:

There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm.

Keywords: intelligent systems, middleware, reconfigurable manufacturing, management system

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Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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Authors: D. Rama Krishna, Y. Pandu Rangaiah

Abstract:

This paper presents the design of multiband reconfigurable antenna using PIN diodes for four iterations and all the four iterations have been validated by measuring return loss and pattern measurements of developed prototype antenna. The simulated and experimental data have demonstrated the concepts of a multiband reconfigurable antenna by switching OFF and ON of PIN diodes for multiple band frequencies. The technique has taken the advantage of a different number of radiating lengths with the use of PIN diode switches, each configuration resonating at multiband frequencies.

Keywords: frequency reconfigurable, meandered line multiband antenna, PIN diode, multiband frequencies

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Authors: Sudhina H. K, Ravi M. Yadahalli, N. M. Shetti

Abstract:

Reconfigurable antennas represent a recent innovation in antenna design that changes from classical fixed-form, Fixed function antennas to modifiable structures that can be adapted to fit the requirements of a time varying system. The ability to control the operating band of an antenna system can have many useful applications. Systems that operate in an acquire-and-track configuration would see a benefit from active bandwidth control. In such systems a wide band search mode is first employed to find a desired signal, Then a narrow band track mode is used to follow only that signal. Utilizing active antenna bandwidth control, A single antenna would function for both the wide band and narrow band configurations providing the rejection of unwanted signals with the antenna hardware. This ability to move a portion of the RF filtering out of the receiver and onto the antenna itself will also aid in reducing the complexity of the often expensive RF processing subsystems.

Keywords: designing methods, mems, stack, reconfigurable elements

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Authors: Mohsin Raza, Arne Bilberg, Thomas Ditlev Brunø, Ann-Louise Andersen, Filip SKärin

Abstract:

Shifting from a dedicated or flexible manufacturing system to a reconfigurable manufacturing system (RMS) requires a significant amount of time, money, and effort. Therefore, it is vital to verify beforehand that the potential reconfigurable solution will be able to achieve the organizational objectives. Discrete event simulation offers the opportunity of assessing several reconfigurable alternatives against the set objectives. This study signifies the importance of using discrete-event simulation as a tool to verify several reconfiguration options. Two different industrial cases have been presented in the study to elaborate on the role of discrete event simulation in the implementation methodology of RMSs. The study concluded that discrete event simulation is one of the important tools to consider in the RMS implementation methodology.

Keywords: reconfigurable manufacturing system, discrete event simulation, Tecnomatix plant simulation, RMS

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Authors: M. Srilatha, R. Hemalatha, T. Sri Aditya

Abstract:

Communication of today world is dominated by wireless technology. This is mainly due to the revolutionary development of new wireless communication system generations. The evolving new generations of wireless systems are accommodating the demand through better resource management including improved transmission technologies with optimized communication devices. To keep up with the evolution of technologies, the communication systems must be designed to optimize transparent insertion of newly evolved technologies virtually at all stages of their life cycle. After the insertion of new technologies, the upgraded devices should continue the communication without squalor in quality. The concern of improving spectrum access and spectrum efficiency combined with both the introduction of Software Defined Radios (SDR) and the possibility of the software application to radios has led to an evolution of wireless radio research. The software defined radio term was coined in the 1970s to overcome the problems in the application of software to wireless radios which eliminates the requirement of hardware changes. SDR has become the prime theme of research since it eliminates the drawbacks associated with conventional wireless communication systems implementation. This paper identifies and discusses key enabling technologies and possibility of research and development in SDRs. In addition transmitter and receiver architectures of SDR are also discussed along with their feasibility for reconfigurable radio application.

Keywords: software defined radios, wireless communication, reconfigurable, reconfigurable transmitter, reconfigurable receivers, FPGA, DSP

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Authors: Roukaya Dalbouchi, Abdelkrin Zitouni

Abstract:

In this paper, we propose a novel design methodology for Dynamic Partial Reconfigurable (DPR) system. This type of system has the property of being able to be modified after its design and during its execution. The suggested design methodology is generic in terms of granularity, number of modules, and reconfigurable region and suitable for any type of modern application. It is based on the interconnection between several design stages. The recommended methodology represents a guide for the design of DPR architectures that meet compromise reconfiguration/performance. To validate the proposed methodology, we use as an application a video watermarking. The comparison result shows that the proposed methodology supports all stages of DPR architecture design and characterized by a high abstraction level. It provides a dynamic/partial reconfigurable architecture; it guarantees material efficiency, the flexibility of reconfiguration, and superior performance in terms of frequency and power consumption.

Keywords: dynamically reconfigurable system, block matching algorithm, partial reconfiguration, motion vectors, video watermarking

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Authors: Manpreet Singh, V. P. Agrawal, Gurmanjot Singh Bhatti

Abstract:

From the last decades, there is a significant technological advancement in the field of robotics, and a number of modular self-reconfigurable robots were introduced that can help in space exploration, bucket to stuff, search, and rescue operation during earthquake, etc. As there are numbers of self-reconfigurable robots, choosing the optimum one is always a concern for robot user since there is an increase in available features, facilities, complexity, etc. The objective of this research work is to present a multiple attribute decision making based methodology for coding, evaluation, comparison ranking and selection of modular self-reconfigurable robots using a technique for order preferences by similarity to ideal solution approach. However, 86 attributes that affect the structure and performance are identified. A database for modular self-reconfigurable robot on the basis of different pertinent attribute is generated. This database is very useful for the user, for selecting a robot that suits their operational needs. Two visual methods namely linear graph and spider chart are proposed for ranking of modular self-reconfigurable robots. Using five robots (Atron, Smores, Polybot, M-Tran 3, Superbot), an example is illustrated, and raking of the robots is successfully done, which shows that Smores is the best robot for the operational need illustrated, and this methodology is found to be very effective and simple to use.

Keywords: self-reconfigurable robots, MADM, TOPSIS, morphogenesis, scalability

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Authors: Ting Gao, Mingyue He

Abstract:

Reconfigurable intelligent surfaces (RISs) are expected to be an important part of next-generation wireless communication networks due to their potential to reduce the hardware cost and energy consumption of millimeter Wave (mmWave) massive multiple-input multiple-output (MIMO) technology. However, owing to the lack of signal processing abilities of the RIS, the perfect channel state information (CSI) in RIS-assisted communication systems is difficult to acquire. In this paper, the uplink channel estimation for mmWave systems with a hybrid active/passive RIS architecture is studied. Specifically, a deep learning-based estimation scheme is proposed to estimate the channel between the RIS and the user. In particular, the sparse structure of the mmWave channel is exploited to formulate the channel estimation as a sparse reconstruction problem. To this end, the proposed approach is derived to obtain the distribution of non-zero entries in a sparse channel. After that, the channel is reconstructed by utilizing the least-squares (LS) algorithm and compressed sensing (CS) theory. The simulation results demonstrate that the proposed channel estimation scheme is superior to existing solutions even in low signal-to-noise ratio (SNR) environments.

Keywords: channel estimation, reconfigurable intelligent surface, wireless communication, deep learning

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, V. S. Tripathi, Shivesh Tripathi

Abstract:

A frequency reconfigurable multiband antenna for intelligent transportation system (ITS) applications is proposed in this paper. A PIN-diode is used for reconfigurability. Centre frequencies are 1.38, 1.98, 2.89, 3.86, and 4.34 GHz in “ON” state of Diode and 1.56, 2.16, 2.88, 3.91 and 4.45 GHz in “OFF” state. Achieved maximum bandwidth is 18%. The maximum gain of the proposed antenna is 2.7 dBi in “ON” state and 3.95 dBi in “OFF” state of the diode. The antenna is simulated, fabricated, and tested in the lab. Measured and simulated results are in good confirmation.

Keywords: ITS, multiband antenna, PIN-diode, reconfigurable

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Authors: André Lages, Victor Dmitriev, Juliano Bazzo, Gianni Portela

Abstract:

This work evaluates the feasibility of the graphene application to perform as a wideband reconfigurable material for lens antennas in 5G/6G and satellite applications. Based on transformation optics principles, the electromagnetic waves can be efficiently guided by modifying the effective refractive index. Graphene behavior can range between a lossy dielectric and a good conductor due to the variation of its chemical potential bias, thus arising as a promising solution for electromagnetic devices. The graphene properties and a lens antenna comprising multiples layers and periodic arrangements of graphene patches were analyzed using full-wave simulations. A dipole directivity was improved from 7 to 18.5 dBi at 29 GHz. In addition, the realized gain was enhanced 7 dB across a 14 GHz bandwidth within the Ka/5G band.

Keywords: 5G/6G, graphene, lens, reconfigurable, satellite

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Authors: Rehab Abdullah Shendi

Abstract:

The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: customisation, FPGA, MIPS, partial reconfiguration, PR

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, Shivesh Tripathi, V. S. Tripathi

Abstract:

In this paper, a patch antenna array design is proposed for vehicular communication. The antenna consists of 2-element patch array. The antenna array is operating at multiple frequency bands. The multiband operation is achieved by use of slots at proper locations at the patch. The array is made reconfigurable by use of two PIN-diodes. The antenna is simulated and measured in four states of diodes i.e. ON-ON, ON-OFF, OFF-ON, and OFF-OFF. In ON-ON state of diodes, the resonant frequencies are 4.62-4.96, 6.50-6.75, 6.90-7.01, 7.34-8.22, 8.89-9.09 GHz. In ON-OFF state of diodes, the measured resonant frequencies are 4.63-4.93, 6.50-6.70 and 7.81-7.91 GHz. In OFF-ON states of diodes the resonant frequencies are 1.24-1.46, 3.40-3.75, 5.07-5.25 and 6.90-7.20 GHz and in the OFF-OFF state of diodes 4.49-4.75 and 5.61-5.98 GHz. The maximum bandwidth of the proposed antenna is 16.29%. The peak gain of the antenna is 3.4 dB at 5.9 GHz, which makes it suitable for vehicular communication.

Keywords: antenna, array, reconfigurable, vehicular

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Authors: Peter Tabatt, Christian Siemers

Abstract:

Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs.

Keywords: reconfigurable FPGA, cellular automata, partitioning, metrics, parallel computing

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Qinghua Zhang, Yanhe Zhu, Xiang Zhao, Yeqin Yang, Hongwei Jing, Guoan Zhang, Jie Zhao

Abstract:

This paper presents a wearable reconfigurable supernumerary robotic limb with differential actuated joints, which is lightweight, compact and comfortable for the wearers. Compared to the existing supernumerary robotic limbs which mostly adopted series structure with large movement space but poor carrying capacity, a prototype with the series-parallel configuration to better adapt to different task requirements has been developed in this design. To achieve a compact structure, two kinds of cable-driven mechanical structures based on guide pulleys and differential actuated joints were designed. Moreover, two different tension devices were also designed to ensure the reliability and accuracy of the cable-driven transmission. The proposed device also employed self-designed bearings which greatly simplified the structure and reduced the cost.

Keywords: cable-driven, differential actuated joints, reconfigurable, supernumerary robotic limb

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Authors: Meena Agrawal, Chaitanya P. Agrawal

Abstract:

The power systems are transforming and becoming smarter with innovations in technologies to enable embark simultaneously upon the sustainable energy needs, rising environmental concerns, economic benefits and quality requirements. The advantages provided by inter-connection of renewable energy resources are becoming more viable and dependable with the smart controlling technologies. The limitation of most renewable resources have their diversity and intermittency causing problems in power quality, grid stability, reliability, security etc. is being cured by these efforts. A necessitate of optimal energy management by intelligent Micro-Grids at the distribution end of the power system has been accredited to accommodate sustainable renewable Distributed Energy Resources on large scale across the power grid. All over the world Smart Grids are emerging now as foremost concern infrastructure upgrade programs. The hardware setup includes NI cRIO 9022, Compact Reconfigurable Input Output microcontroller board connected to the PC on a LAN router with three hardware modules. The Real-Time Embedded Controller is reconfigurable controller device consisting of an embedded real-time processor controller for communication and processing, a reconfigurable chassis housing the user-programmable FPGA, Eight hot-swappable I/O modules, and graphical LabVIEW system design software. It has been employed for signal analysis, controls and acquisition and logging of the renewable sources with the LabVIEW Real-Time applications. The employed cRIO chassis controls the timing for the module and handles communication with the PC over the USB, Ethernet, or 802.11 Wi-Fi buses. It combines modular I/O, real-time processing, and NI LabVIEW programmable. In the presented setup, the Analog Input Module NI 9205 five channels have been used for input analog voltage signals from renewable energy sources and NI 9227 four channels have been used for input analog current signals of the renewable sources. For switching actions based on the programming logic developed in software, a module having Electromechanical Relays (single-pole single throw) with 4-Channels, electrically isolated and LED indicating the state of that channel have been used for isolating the renewable Sources on fault occurrence, which is decided by the logic in the program. The module for Ethernet based Data Acquisition Interface ENET 9163 Ethernet Carrier, which is connected on the LAN Router for data acquisition from a remote source over Ethernet also has the module NI 9229 installed. The LabVIEW platform has been employed for efficient data acquisition, monitoring and control. Control logic utilized in program for operation of the hardware switching Related to Fault Relays has been portrayed as a flowchart. A communication system has been successfully developed amongst the sources and loads connected on different computers using Hypertext transfer protocol, HTTP or Ethernet Local Stacked area Network TCP/IP protocol. There are two main I/O interfacing clients controlling the operation of the switching control of the renewable energy sources over internet or intranet. The paper presents experimental results of the briefed setup for intelligent control of the micro-grid for renewable energy sources, besides the control of Micro-Grid with data acquisition and control hardware based on a microcontroller with visual program developed in LabVIEW.

Keywords: data acquisition and control, LabVIEW, microcontroller cRIO, Smart Micro-Grid

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Authors: Jun Young Moon, Hyeonggeon Lee, Jong Tae Kim

Abstract:

In this paper, we present Cortex-M3 based virtual platform which can virtualize wearable hardware platform and evaluate hardware performance. Cortex-M3 is very popular microcontroller in wearable devices, hardware sensors and display devices. This platform can be used to implement software layer for specific hardware architecture. By using the proposed platform the software development process can be parallelized with hardware development process. We present internal mechanism to implement the proposed virtual platform and describe how to use the proposed platform to develop software by using case study which is low cost wearable device that uses Cortex-M3.

Keywords: electronic system level design, software development, virtual platform, wearable device

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Authors: Getaneh Berie Tarekegn

Abstract:

Wireless communication via unmanned aerial vehicles (UAVs) has drawn a great deal of attention due to its flexibility in establishing line-of-sight (LoS) communications. However, in complex urban and dynamic environments, the movement of UAVs can be blocked by trees and high-rise buildings that obstruct directional paths. With reconfigurable intelligent surfaces (RIS), this problem can be effectively addressed. To achieve this goal, accurate channel estimation in RIS-assisted UAV-enabled wireless communications is crucial. This paper proposes an accurate channel estimation model using long short-term memory (LSTM) for a multi-user RIS-assisted UAV-enabled wireless communication system. According to simulation results, LSTM can improve the channel estimation performance of RIS-assisted UAV-enabled wireless communication.

Keywords: channel estimation, reconfigurable intelligent surfaces, long short-term memory, unmanned aerial vehicles

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Authors: Yang Luo, Beibei Wang

Abstract:

In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Fariborz Ahmadi, Reza Tati

Abstract:

Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only do not this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.

Keywords: hardware, genetic algorithm, computer science, engineering

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Authors: Shi Yu Wang, Qian Wei Zhang, He Li, Hao Han He, Yun Bo Li

Abstract:

The spatial controls of electromagnetic (EM) waves have always been a research hot spot in recent years. And the rapid development of metasurface-based technologies has provided more freedoms for manipulating the EM waves. Here we propose the design of reconfigurable and non-reciprocal metasurface with independent controls of transmission gain, attenuation and phase. The proposed meta-atom mainly consists of the cascaded textures including the receiving antenna, the middle layer in which the power amplifiers (PAs), programmable attenuator and phase shifter locate, and the transmitting antenna. The programmable attenuator and phase shifter can realize the dynamic controls of transmission amplitude and phase independently, and the PA devices in the meta-atom can actualize the performance of non-reciprocal transmission. The proposed meta-atom is analyzed applying field-circuit co-simulation and a sample of the meta-atom is fabricated and measured under using two standard waveguides. The measured results verify the ability of the independent manipulation for transmission amplitude and phase of the proposed the meta-atom and the design method has been verified very well correspondingly.

Keywords: active circuits, independent controls of multiple electromagnetic features, non-reciprocal electromagnetic transmission, reconfigurable and programmable

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Authors: Ziyuan Wu, Yulong Jia, Xiang Zhang, Wanting Zhou, Lei Li

Abstract:

The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method.

Keywords: IoT, security, SoC, bus architecture, lightweight hardware firewall, FPGA

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Authors: Tarek El-Derini, Ahmed El-Shenawy

Abstract:

This paper presents the hardware implemented and validation for a special system to assist the unprofessional users of car with back trailers. The system consists of two platforms; the front car platform (C) and the trailer platform (T). The main objective is to control the Trailer platform using the actuators found in the front platform (c). The mobility of the platform (C) is investigated and inverse and forward kinematics model is obtained for both platforms (C) and (T). The system is simulated using Matlab M-file and the simulation examples results illustrated the system performance. The system is constructed with a hardware setup for the front and trailer platform. The hardware experimental results and the simulated examples outputs showed the validation of the hardware setup.

Keywords: kinematics, modeling, robot, MATLAB

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Authors: Nikolaos Georgoulopoulos, Alkis Hatzopoulos, Konstantinos Karamitsios, Konstantinos Kotrotsios, Alexandros I. Metsai

Abstract:

In modern server systems, business critical applications run in different types of infrastructure, such as cloud systems, physical machines and virtualization. Often, due to high load and over time, various hardware faults occur in servers that translate to errors, resulting to malfunction or even server breakdown. CPU, RAM and hard drive (HDD) are the hardware parts that concern server administrators the most regarding errors. In this work, selected RAM, HDD and CPU errors, that have been observed or can be simulated in kernel ring buffer log files from two groups of Linux servers, are investigated. Moreover, a severity characterization is given for each error type. Better understanding of such errors can lead to more efficient analysis of kernel logs that are usually exploited for fault diagnosis and prediction. In addition, this work summarizes ways of simulating hardware errors in RAM and HDD, in order to test the error detection and correction mechanisms of a Linux server.

Keywords: hardware errors, Kernel logs, Linux servers, RAM, hard disk, CPU

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Authors: Qingqing Gai, Junxing Shen, Yu Luo

Abstract:

Due to the hardware architecture characteristics, some operators tend to acquire better performance if the input/output tensor dimensions are aligned to a certain minimum granularity, such as convolution and deconvolution commonly used in deep learning. Furthermore, if the requirements are not met, the general strategy is to pad with 0 to satisfy the requirements, potentially leading to the under-utilization of the hardware resources. Therefore, for the convolution and deconvolution whose input and output channels do not meet the minimum granularity alignment, we propose to transfer the W-dimensional data to the C-dimension for computation (W2C) to enable the C-dimension to meet the hardware requirements. This scheme also reduces the number of computations in the W-dimension. Although this scheme substantially increases computation, the operator’s speed can improve significantly. It achieves remarkable speedups on multiple hardware accelerators, including Nvidia Tensor cores, Qualcomm digital signal processors (DSPs), and Huawei neural processing units (NPUs). All you need to do is modify the network structure and rearrange the operator weights offline without retraining. At the same time, for some operators, such as the Reducemax, we observe that transferring the Cdimensional data to the W-dimension(C2W) and replacing the Reducemax with the Maxpool can accomplish acceleration under certain circumstances.

Keywords: convolution, deconvolution, W2C, C2W, alignment, hardware accelerator

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Authors: S. Padmapriya, V. Lakshmi Prabha

Abstract:

In this paper, an efficient reconfigurable fixed-point Least Mean Square Adaptive FIR filter is proposed. The proposed architecture has two methods of operation: one is area efficient design and the other is optimized power. Pipelining of the adder blocks and partial product generator are used to achieve low area and reversible logic is used to obtain low power design. Depending upon the input samples and filter coefficients, one of the techniques is chosen. Least-Mean-Square adaptation is performed to update the weights. The architecture is coded using Verilog and synthesized in cadence encounter 0.18μm technology. The synthesized results show that the area reduction ratio of the proposed when compared with conventional technique is about 1.2%.

Keywords: adaptive filter, carry select adder, least mean square algorithm, reversible logic

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