Search results for: open loop voltage gain
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 6151

Search results for: open loop voltage gain

6121 A High Linear and Low Power with 71dB 35.1MHz/4.38GHz Variable Gain Amplifier in 180nm CMOS Technology

Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

Abstract:

This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

Procedia PDF Downloads 60
6120 Design of 900 MHz High Gain SiGe Power Amplifier with Linearity Improved Bias Circuit

Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

Procedia PDF Downloads 301
6119 Modeling SET Effect on Charge Pump Phase Locked Loop

Authors: Varsha Prasad, S. Sandya

Abstract:

Cosmic Ray effects in microelectronics such as single event effect (SET) and total dose ionization (TID) have been of major concern in space electronics since 1970. Advanced CMOS technologies have demonstrated reduced sensitivity to TID effect. However, charge pump Phase Locked Loop is very much vulnerable to single event transient effect. This paper presents an SET analysis model, where the SET is modeled as a double exponential pulse. The time domain analysis reveals that the settling time of the voltage controlled oscillator (VCO) depends on the SET pulse strength, setting the time constant and the damping factor. The analysis of the proposed SET analysis model is confirmed by the simulation results.

Keywords: charge pump, phase locked loop, SET, VCO

Procedia PDF Downloads 408
6118 MPC of Single Phase Inverter for PV System

Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive (UI) single phase inverter (SPI) for a photovoltaic (PV) system at residential/distribution level. The proposed model uses single-phase phase locked loop (PLL) to synchronize SPI with the grid and performs MPC control in a dq reference frame. SPI model consists of boost converter (BC), maximum power point tracking (MPPT) control, and a full bridge (FB) voltage source inverter (VSI). No PI regulators to tune and carrier and modulating waves are required to produce switching sequence. Instead, the operational model of VSI is used to synthesize sinusoidal current and track the reference. Model is validated using a three kW PV system at the input of UI-SPI in Matlab/Simulink. Implementation and results demonstrate simplicity and accuracy, as well as reliability of the model.

Keywords: phase locked loop, voltage source inverter, single phase inverter, model predictive control, Matlab/Simulink

Procedia PDF Downloads 493
6117 3D Shape Knitting: Loop Alignment on a Surface with Positive Gaussian Curvature

Authors: C. T. Cheung, R. K. P. Ng, T. Y. Lo, Zhou Jinyun

Abstract:

This paper aims at manipulating loop alignment in knitting a three-dimensional (3D) shape by its geometry. Two loop alignment methods are introduced to handle a surface with positive Gaussian curvature. As weft knitting is a two-dimensional (2D) knitting mechanism that the knitting cam carrying the feeders moves in two directions only, left and right, the knitted fabric generated grows in width and length but not in depth. Therefore, a 3D shape is required to be flattened to a 2D plane with surface area preserved for knitting. On this flattened plane, dimensional measurements are taken for loop alignment. The way these measurements being taken derived two different loop alignment methods. In this paper, only plain knitted structure was considered. Each knitted loop was taken as a basic unit for loop alignment in order to achieve the required geometric dimensions, without the inclusion of other stitches which give textural dimensions to the fabric. Two loop alignment methods were experimented and compared. Only one of these two can successfully preserve the dimensions of the shape.

Keywords: 3D knitting, 3D shape, loop alignment, positive Gaussian curvature

Procedia PDF Downloads 316
6116 Reduction of Biofilm Formation in Closed Circuit Cooling Towers

Authors: Irfan Turetgen

Abstract:

Closed-circuit cooling towers are cooling units that operate according to the indirect cooling principle. Unlike the open-loop cooling tower, the filler material includes a closed-loop water-operated heat exchanger. The main purpose of this heat exchanger is to prevent the cooled process water from contacting with the external environment. In order to ensure that the hot water is cooled, the water is cooled by the air flow and the circulation water of the tower as it passes through the pipe. They are now more commonly used than open loop cooling towers that provide cooling with plastic filling material. As with all surfaces in contact with water, there is a biofilm formation on the outer surface of the pipe. Although biofilm has been studied very well on plastic surfaces in open loop cooling towers, studies on biofilm layer formed on the heat exchangers of the closed circuit tower have not been found. In the recent study, natural biofilm formation was observed on the heat exchangers of the closed loop tower for 6 months. At the same time, nano-silica coating, which is known to reduce the formation of the biofilm layer, a comparison was made between the two different surfaces in terms of biofilm formation potential. Test surfaces were placed into biofilm reactor along with the untreated control coupons up to 6-months period for biofilm maturation. Natural bacterial communities were monitored to analyze the impact to mimic the real-life conditions. Surfaces were monthly analyzed in situ for their microbial load using epifluorescence microscopy. Wettability is known to play a key role in biofilm formation on surfaces, because characteristics of surface properties affect the bacterial adhesion. Results showed that surface-conditioning with nano-silica significantly reduce (up to 90%) biofilm formation. Easy coating process is a facile and low-cost method to prepare hydrophobic surface without any kinds of expensive compounds or methods.

Keywords: biofilms, cooling towers, fill material, nano silica

Procedia PDF Downloads 103
6115 Near Optimal Closed-Loop Guidance Gains Determination for Vector Guidance Law, from Impact Angle Errors and Miss Distance Considerations

Authors: Karthikeyan Kalirajan, Ashok Joshi

Abstract:

An optimization problem is to setup to maximize the terminal kinetic energy of a maneuverable reentry vehicle (MaRV). The target location, the impact angle is given as constraints. The MaRV uses an explicit guidance law called Vector guidance. This law has two gains which are taken as decision variables. The problem is to find the optimal value of these gains which will result in minimum miss distance and impact angle error. Using a simple 3DOF non-rotating flat earth model and Lockheed martin HP-MARV as the reentry vehicle, the nature of solutions of the optimization problem is studied. This is achieved by carrying out a parametric study for a range of closed loop gain values and the corresponding impact angle error and the miss distance values are generated. The results show that there are well defined lower and upper bounds on the gains that result in near optimal terminal guidance solution. It is found from this study, that there exist common permissible regions (values of gains) where all constraints are met. Moreover, the permissible region lies between flat regions and hence the optimization algorithm has to be chosen carefully. It is also found that, only one of the gain values is independent and that the other dependent gain value is related through a simple straight-line expression. Moreover, to reduce the computational burden of finding the optimal value of two gains, a guidance law called Diveline guidance is discussed, which uses single gain. The derivation of the Diveline guidance law from Vector guidance law is discussed in this paper.

Keywords: Marv guidance, reentry trajectory, trajectory optimization, guidance gain selection

Procedia PDF Downloads 394
6114 SCR-Based Advanced ESD Protection Device for Low Voltage Application

Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

Procedia PDF Downloads 536
6113 Improvement of Piezoresistive Pressure Sensor Accuracy by Means of Current Loop Circuit Using Optimal Digital Signal Processing

Authors: Peter A. L’vov, Roman S. Konovalov, Alexey A. L’vov

Abstract:

The paper presents the advanced digital modification of the conventional current loop circuit for pressure piezoelectric transducers. The optimal DSP algorithms of current loop responses by the maximum likelihood method are applied for diminishing of measurement errors. The loop circuit has some additional advantages such as the possibility to operate with any type of resistance or reactance sensors, and a considerable increase in accuracy and quality of measurements to be compared with AC bridges. The results obtained are dedicated to replace high-accuracy and expensive measuring bridges with current loop circuits.

Keywords: current loop, maximum likelihood method, optimal digital signal processing, precise pressure measurement

Procedia PDF Downloads 499
6112 Design and Development of Compact 1KW Floating Battery Discharge Regulator

Authors: A. Sreedevi, G. Anantaramu

Abstract:

The present space research organizations are striving towards the development of lighter, smaller, more efficient, low cost, and highly reliable power supply. Switch mode power supplies (SMPS) overcome the demerits of linear power supplies such as low efficiency, difficulties in thermal management, and in boosting the output voltage. Space applications require a constant DC voltage to supply its load. As the load varies, the battery terminal voltage tends to vary accordingly. To avoid this variation in the load terminal voltage, a DC-DC regulator is required. The conventional regulator for space applications is isolated boost topology. The proposed topology uses an interleaved push-pull converter with a current doubler secondary to reduce the EMI issues and increase efficiency. The proposed topology uses a floating technique where the converter derives power from the battery and generates only the voltage that is required to fill the gap between the bus and the battery voltage. The direct voltage sense and current loop provide tight regulation of output and better stability. Converter is designed with 50 kHz switching frequency using UC 1825 PWM controller employing both voltage and peak current mode control. Experimental tests have been carried out on the converter under different input and load conditions to validate the design. The experimental results showed that the efficiency was greater than 91%. Stability analysis is done using venable stability analyzer.

Keywords: push pull converter, current doubler, converter, PWM control

Procedia PDF Downloads 70
6111 DG Power Plants Placement and Evaluation of its Effect on Improving Voltage Security Margin in Radial Distribution Networks

Authors: Atabak Faramarzpour, Mohsen Mohammadian

Abstract:

In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

Procedia PDF Downloads 628
6110 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 491
6109 H∞robust Control Law for a Speed Dc Motor in Both Directions of Rotation

Authors: Ben Abdallah Aicha

Abstract:

In this work we show a H∞ synthesis method which enables us to calculate a feedback controller according to considerations of stability robustness and disturbance rejection translated on to the open loop response. However, it may happen that we have an additional specification on the closed loop response relating to tracking of the reference trajectory. The H∞ synthesis has the advantage of offering increased specifications in robustness stability. Implemented for a DC motor, it offers invaluable performance in speed control in both directions of rotation.

Keywords: H∞ synthesis, DC motor, robustness stability, performance conditions

Procedia PDF Downloads 43
6108 Voltage Controlled Ring Oscillator for RF Applications in 0.18 µm CMOS Technology

Authors: Mohammad Arif Sobhan Bhuiyan, Zainal Abidin Nordin, Mamun Bin Ibne Reaz

Abstract:

A compact and power efficient high performance Voltage Controlled Oscillator (VCO) is a must in analog and digital circuits especially in the communication system, but the best trade-off among the performance parameters is a challenge for researchers. In this paper, a design of a compact 3-stage differential voltage controlled ring oscillator (VCRO) with low phase noise, low power and higher tuning bandwidth is proposed in 0.18 µm CMOS technology. The VCRO is designed with symmetric load and positive feedback techniques to achieve higher gain and minimum delay. The proposed VCRO can operate at tuning range of 3.9-5.0 GHz at 1.6 V supply voltage. The circuit consumes only 1.0757 mW of power and produces -129 dbc/Hz. The total active area of the proposed VCRO is only 11.74 x 37.73 µm2. Such a VCO can be the best choice for compact and low-power RF applications.

Keywords: CMOS, VCO, VCRO, oscillator

Procedia PDF Downloads 438
6107 Design of IMC-PID Controller Cascaded Filter for Simplified Decoupling Control System

Authors: Le Linh, Truong Nguyen Luan Vu, Le Hieu Giang

Abstract:

In this work, the IMC-PID controller cascaded filter based on Internal Model Control (IMC) scheme is systematically proposed for the simplified decoupling control system. The simplified decoupling is firstly introduced for multivariable processes by using coefficient matching to obtain a stable, proper, and causal simplified decoupler. Accordingly, transfer functions of decoupled apparent processes can be expressed as a set of n equivalent independent processes and then derived as a ratio of the original open-loop transfer function to the diagonal element of the dynamic relative gain array. The IMC-PID controller in series with filter is then directly employed to enhance the overall performance of the decoupling control system while avoiding difficulties arising from properties inherent to simplified decoupling. Some simulation studies are considered to demonstrate the simplicity and effectiveness of the proposed method. Simulations were conducted by tuning various controllers of the multivariate processes with multiple time delays. The results indicate that the proposed method consistently performs well with fast and well-balanced closed-loop time responses.

Keywords: coefficient matching method, internal model control (IMC) scheme, PID controller cascaded filter, simplified decoupler

Procedia PDF Downloads 414
6106 A Study on Unidirectional Analog Output Voltage Inverter for Capacitive Load

Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

Abstract:

For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

Procedia PDF Downloads 352
6105 Study of the Hysteretic I-V Characteristics in a Polystyrene/ZnO-Nanorods Stack Layer

Authors: You-Lin Wu, Yi-Hsing Sung, Shih-Hung Lin, Jing-Jenn Lin

Abstract:

Performance improvement in optoelectronic devices such as solar cells and photodetectors has been reported when a polymer/ZnO nanorods stack is used. Resistance switching of polymer/ZnO nanocrystals (or nanorods) hybrid has also gained a lot of research interests recently. It has been reported that high- and low-resistance states of a metal/insulator/metal (MIM) structure diode with a polystyrene (PS) and ZnO hybrid as the insulator layer can be switched by applied bias after a high-voltage forming process, while the same device structure merely with a PS layer does not show any forming behavior. In this work, we investigated the current-voltage (I-V) characteristics of an MIM device with a PS/ZnO nanorods stack deposited on fluorine-doped tin oxide (FTO) glass substrate. The ZnO nanorods were grown by a hydrothermal method using a mixture of zinc nitrate, hexamethylenetetramine, and DI water. Following that, a PS layer was deposited by spin coating. Finally, the device with a structure of Ti/ PS/ZnO nanorods/FTO was completed by e-gun evaporated Ti layer on top of the PS layer. Semiconductor parameters analyzer Agilent 4156C was then used to measure the I-V characteristics of the device by applying linear ramp sweep voltage with sweep sequence of 0V → 4V → 0V → 3V → 0V → 2V → 0V → 1V → 0V in both positive and negative directions. It is interesting to find that the I-V characteristics are bias dependent and hysteretic, indicating that the device Ti/PS/ZnO nanorods/FTO structure has ferroelectricity. Our results also show that the maximum hysteresis loop height of the I-V characteristics as well as the voltage at which the maximum hysteresis loop height of each scan occurs increase with increasing maximum sweep voltage. It should be noticed that, although ferroelectricity has been found in ZnO at its melting temperature (1975℃) and in Li- or Co-doped ZnO, neither PS nor ZnO has ferroelectricity at room temperature. Using the same structure but with a PS or ZnO layer only as the insulator does not give and hysteretic I-V characteristics. It is believed that a charge polarization layer is induced near the PS/ZnO nanorods stack interface and thus causes the ferroelectricity in the device with Ti/PS/ZnO nanorods/FTO structure. Our results show that the PS/ZnO stack can find a potential application in a resistive switching memory device with MIM structure.

Keywords: ferroelectricity, hysteresis, polystyrene, resistance switching, ZnO nanorods

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6104 Hidden Oscillations in the Mathematical Model of the Optical Binary Phase Shift Keying (BPSK) Costas Loop

Authors: N. V. Kuznetsov, O. A. Kuznetsova, G. A. Leonov, M. V. Yuldashev, R. V. Yuldashev

Abstract:

Nonlinear analysis of the phase locked loop (PLL)-based circuits is a challenging task. Thus, the simulation is widely used for their study. In this work, we consider a mathematical model of the optical Costas loop and demonstrate the limitations of simulation approach related to the existence of so-called hidden oscillations in the phase space of the model.

Keywords: optical Costas loop, mathematical model, simulation, hidden oscillation

Procedia PDF Downloads 400
6103 Study of Dermatoglyphics Pattern in Patient with Hypertension

Authors: Ajeevan Gautam, Gulam Anwer Khan, Pratibha Pokhrel

Abstract:

Introduction: Dermatoglyphics is the science which deals with the study of dermal ridge configuration on the digits, palms and soles. It is grooved by ridges and forms variety of configurations. The aim of the study was to identify dermal ridge patterns on fingertip of hypertensive patients and in normal population and to compare patterns among them. Methods: The subjects of the study were 130 hypertensives and 130 non-hypertensives cases of Kathmandu Valley aged between 40 to 80 years. Case history was recorded after consent finger prints were taken. Different parameters as whorl, loop, arch and composite patterns were studied and analysed. Result: It revealed, increased whorl pattern in hypertensive. It showed 65.69% whorl, 29.23% loop and 5.07% arch patterns in right hand of hypertensive people. In control, it was found to be 34.46% whorl, 58.15% loop and 5.38% arch patterns respectively. Similarly in left hand 63.69% whorl, 32% loop and 4.30% arch in hypertensive group. In control group it was 60.15% as loop, 35.69% as whorl and 15% as arch. Discussion: Based on findings of the result, it was concluded that the whorl, loop and arch patterns observed as 65.69%, 29.23% and 5.07% respectively in hypertensive cases in right hand. Similarly in left hand, it was found to be 4.30% as arch, 32% as loop and 63.69% as whorl patterns, but in normotensive subjects these patterns were recorded as 36.43%, 58.15%, 5.38% in right hand and 35.69%, 60.15%, 4.15% in left hand as whorl, loop and arch respectively.

Keywords: arch, dermatoglyphics, hypertension, loop, whorl

Procedia PDF Downloads 265
6102 SCR-Stacking Structure with High Holding Voltage for IO and Power Clamp

Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

Procedia PDF Downloads 527
6101 Dynamics of Mach Zehnder Modulator in Open and Closed Loop Bias Condition

Authors: Ramonika Sengupta, Stuti Kachhwaha, Asha Adhiya, K. Satya Raja Sekhar, Rajwinder Kaur

Abstract:

Numerous efforts have been done in the past decade to develop the methods of secure communication that are free from interception and eavesdropping. In fiber optic communication, chaotic optical carrier signals are used for data encryption in secure data transmission. Mach-Zehnder Modulators (MZM) are the key components for generating the chaotic signals to be used as optical carriers. This paper presents the dynamics of a lithium niobate MZM modulator under various biasing conditions. The chaotic fluctuations of the intensity of a laser diode have been generated using the electro-optic MZM modulator operating in a highly nonlinear regime. The modulator is driven in closed loop by its own output at an earlier time. When used as an electro-optic oscillator employing delayed feedback, the MZM displays a wide range of output waveforms of varying complexity. The dynamical behavior of the system ranges from periodic to nonlinear oscillations. The nonlinearity displayed by the system is reproducible and is easily controllable. In this paper, we demonstrate a wide variety of optical signals generated by MZM using easily controllable device parameters in both open and close loop bias conditions.

Keywords: chaotic carrier, fiber optic communication, Mach-Zehnder modulator, secure data transmission

Procedia PDF Downloads 238
6100 Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

Procedia PDF Downloads 344
6099 Numerical Investigation of Nanofluid Based Thermosyphon System

Authors: Kiran Kumar K., Ramesh Babu Bejjam, Atul Najan

Abstract:

A thermosyphon system is a heat transfer loop which operates on the basis of gravity and buoyancy forces. It guarantees a good reliability and low maintenance cost as it does not involve any mechanical pump. Therefore it can be used in many industrial applications such as refrigeration and air conditioning, electronic cooling, nuclear reactors, geothermal heat extraction, etc. But flow instabilities and loop configuration are the major problems in this system. Several previous researchers studied that stabilities can be suppressed by using nanofluids as loop fluid. In the present study a rectangular thermosyphon loop with end heat exchangers are considered for the study. This configuration is more appropriate for many practical applications such as solar water heater, geothermal heat extraction, etc. In the present work, steady-state analysis is carried out on thermosyphon loop with parallel flow coaxial heat exchangers at heat source and heat sink. In this loop nano fluid is considered as the loop fluid and water is considered as the external fluid in both hot and cold heat exchangers. For this analysis one-dimensional homogeneous model is developed. In this model, conservation equations like conservation of mass, momentum, energy are discretized using finite difference method. A computer code is written in MATLAB to simulate the flow in thermosyphon loop. A comparison in terms of heat transfer is made between water and nano fluid as working fluids in the loop.

Keywords: heat exchanger, heat transfer, nanofluid, thermosyphon loop

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6098 Robust Control of a Dynamic Model of an F-16 Aircraft with Improved Damping through Linear Matrix Inequalities

Authors: J. P. P. Andrade, V. A. F. Campos

Abstract:

This work presents an application of Linear Matrix Inequalities (LMI) for the robust control of an F-16 aircraft through an algorithm ensuring the damping factor to the closed loop system. The results show that the zero and gain settings are sufficient to ensure robust performance and stability with respect to various operating points. The technique used is the pole placement, which aims to put the system in closed loop poles in a specific region of the complex plane. Test results using a dynamic model of the F-16 aircraft are presented and discussed.

Keywords: F-16 aircraft, linear matrix inequalities, pole placement, robust control

Procedia PDF Downloads 277
6097 A High Step-Up DC-DC Converter for Renewable Energy System Applications

Authors: Sopida Vacharasukpo, Sudarat Khwan-On

Abstract:

This paper proposes a high step-up DC-DC converter topology for renewable energy system applications. The proposed converter employs only a single power switch instead of using several switches. Compared to the conventional DC-DC step-up converters the higher voltage gain with small output ripples can be achieved by using the proposed high step-up DC-DC converter topology. It can step up the low input voltage (20-50Vdc) generated from the photovoltaic modules to the high output voltage level approximately 600Vdc in order to supply the three-phase inverter fed the three-phase motor drive. In this paper, the operating principle of the proposed converter topology and its control strategy under the continuous conduction mode (CCM) are described. Finally, simulation results are shown to demonstrate the effectiveness of the proposed high step-up DC-DC converter with its control strategy to increase the voltage step-up conversion ratio.

Keywords: DC-DC converter, high step-up ratio, renewable energy, single switch

Procedia PDF Downloads 1154
6096 Hybrid MIMO-OFDM Detection Scheme for High Performance

Authors: Young-Min Ko, Dong-Hyun Ha, Chang-Bin Ha, Hyoung-Kyu Song

Abstract:

In recent years, a multi-antenna system is actively used to improve the performance of the communication. A MIMO-OFDM system can provide multiplexing gain or diversity gain. These gains are obtained in proportion to the increase of the number of antennas. In order to provide the optimal gain of the MIMO-OFDM system, various transmission and reception schemes are presented. This paper aims to propose a hybrid scheme that base station provides both diversity gain and multiplexing gain at the same time.

Keywords: DFE, diversity gain, hybrid, MIMO, multiplexing gain.

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6095 A Silicon Controlled Rectifier-Based ESD Protection Circuit with High Holding Voltage and High Robustness Characteristics

Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 368
6094 Comparative Study of Line Voltage Stability Indices for Voltage Collapse Forecasting in Power Transmission System

Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

Abstract:

At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

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6093 New Series Input Parallel Output LLC DC/DC Converter with the Input Voltage Balancing Capacitor for the Electric System of Electric Vehicles

Authors: Kang Hyun Yi

Abstract:

This paper presents a new parallel output LLC DC/DC converter for electric vehicle. The electric vehicle has two batteries. One is a high voltage battery for the powertrain of the vehicle and the other is a low voltage battery for the vehicle electric system. The low voltage is charged from the high voltage battery and the high voltage input and the high current output DC/DC converter is needed. Therefore, the new LLC converter with the input voltage compensation is proposed for the high voltage input and the low voltage output DC/DC converter. The proposed circuit has two LLC converters with the series input voltage from the battery for the powertrain and the parallel output low battery voltage for the vehicle electric system because the battery voltage for the powertrain and the electric power for the vehicle become high. Also, the input series voltage compensation capacitor is used for balancing the input current in the two LLC converters. The proposed converter has an equal electric stress of the semiconductor parts and the reactive components, high efficiency and good heat dissipation.

Keywords: electric vehicle, LLC DC/DC converter, input voltage balancing, parallel output

Procedia PDF Downloads 1018
6092 A Low-Voltage Synchronous Command for JFET Rectifiers

Authors: P. Monginaud, J. C. Baudey

Abstract:

The synchronous, low-voltage command for JFET Rectifiers has many applications: indeed, replacing the traditional diodes by these components allows enhanced performances in gain, linearity and phase shift. We introduce here a new bridge, including JFET associated with pull-down, bipolar command systems, and double-purpose logic gates.

Keywords: synchronous, rectifier, MOSFET, JFET, bipolar command system, push-pull circuits, double-purpose logic gates

Procedia PDF Downloads 333