Search results for: circuit analysis

Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

Procedia PDF Downloads 402

Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

Procedia PDF Downloads 251

Authors: B. G. Sheeparamatti, J. S. Kadadevarmath

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Microcantilevers are the basic MEMS devices, which can be used as sensors, actuators, and electronics can be easily built into them. The detection principle of microcantilever sensors is based on the measurement of change in cantilever deflection or change in its resonance frequency. The objective of this work is to explore the analogies between the mechanical and electrical equivalent of microcantilever beams. Normally scientists and engineers working in MEMS use expensive software like CoventorWare, IntelliSuite, ANSYS/Multiphysics, etc. This paper indicates the need of developing the electrical equivalent of the MEMS structure and with that, one can have a better insight on important parameters, and their interrelation of the MEMS structure. In this work, considering the mechanical model of the microcantilever, the equivalent electrical circuit is drawn and using a force-voltage analogy, it is analyzed with circuit simulation software. By doing so, one can gain access to a powerful set of intellectual tools that have been developed for understanding electrical circuits. Later the analysis is performed using ANSYS/Multiphysics - software based on finite element method (FEM). It is observed that both mechanical and electrical domain results for a rectangular microcantilevers are in agreement with each other.

Keywords: electrical equivalent circuit analogy, FEM analysis, micro cantilevers, micro sensors

Procedia PDF Downloads 370

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Huai-Cong Liu，Tae Chul Jeong，Ju Lee

Abstract:

This paper describes characteristic analysis of a synchronous reluctance motor (SynRM)’s rotor with the Multi-segment and Multi-layer structure. The magnetic-saturation phenomenon in SynRM is often appeared. Therefore, when modeling analysis of SynRM the calculation of nonlinear magnetic field needs to be considered. An important influence factor on the convergence process is how to determine the relative permeability. An improved method, which ensures the calculation, is convergence by linear iterative method for saturated magnetic field. If there are inflection points on the magnetic curve,an optimum convergence method of solution for nonlinear magnetic field was provided. Then the equivalent magnetic circuit is calculated, and d,q-axis inductance can be got. At last, this process is applied to design a 7.5Kw SynRM and its validity is verified by comparing with the result of finite element method (FEM) and experimental test data.

Keywords: SynRM, magnetic-saturation, magnetic circuit, analytical modeling

Procedia PDF Downloads 473

Authors: J.Das, Gyan Wrat

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Leakage is the main gradual failure in the fluid power system, which is usually caused by the impurity in the oil and wear of matching surfaces between parts and lead to the change of the gap value. When leakage occurs in the system, the oil will flow from the high pressure chamber into the low pressure chamber through the gap, causing the reduction of system flow as well as the loss of system pressure, resulting in the decreasing of system efficiency. In the fluid power system, internal leakage may occur in various components such as gear pump, reversing valve and hydraulic cylinder, and affect the system work performance. Therefore, component leakage in the fluid power system is selected as the study to characterize the leakage and the effect of leakage on the system. Effect of leakage on system pressure and cylinder displacement can be obtained using pressure sensors and the displacement sensor. The leakage can be varied by changing the orifice using a flow control valve. Hydraulic circuit for leakage will be developed in Matlab/Simulink environment and simulations will be done by changing different parameters.

Keywords: leakage causes, effect, analysis, MATLAB simulation, hydraulic circuit

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Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

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This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver

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Authors: Zhiguo Shi, Cheng Ning Loong, Jiazeng Shan, Weichao Wu

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This study proposes an equivalent circuit model to simulate the eddy current damping force with shaking table tests and finite element modeling. The model is firstly proposed and applied to a simple eddy current damper, which is modelled in ANSYS, indicating that the proposed model can simulate the eddy current damping force under different types of excitations. Then, a non-contact and friction-free eddy current damper is designed and tested, and the proposed model can reproduce the experimental observations. The excellent agreement between the simulated results and the experimental data validates the accuracy and reliability of the equivalent circuit model. Furthermore, a more complicated model is performed in ANSYS to verify the feasibility of the equivalent circuit model in complex eddy current damper, and the higher-order fractional model and viscous model are adopted for comparison.

Keywords: equivalent circuit model, eddy current damping, finite element model, shake table test

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Authors: Amit Kumar Sinha

Abstract:

A coal preparation plant typically operates with multiple beneficiation circuits to process individual size fractions of coal obtained from mine so that the targeted overall plant efficiency in terms of yield and ash is achieved. Conventional coal beneficiation plant in India or overseas operates generally in two methods of processing; coarse beneficiation with treatment in dense medium cyclones or in baths and fines beneficiation with treatment in flotation cell. This paper seeks to address the proven application of intermediate circuit along with coarse and fines circuit in Jamadoba New Coal Preparation Plant of capacity 2 Mt/y to treat -0.5 mm+0.25 mm size particles in reflux classifier. Previously this size of particles was treated directly in Flotation cell which had operational and metallurgical limitations which will be discussed in brief in this paper. The paper also details test work results performed on the representative samples of TSL coal washeries to determine the top size of intermediate and fines circuit and discusses about the overlapping process of intermediate circuit and how it is process wise suitable to beneficiate misplaced particles from coarse circuit and fines circuit. This paper also compares the separation efficiency (Ep) of various intermediate circuit process equipment and tries to validate the use of reflux classifier over fine coal DMC or spirals. An overview of Modern coal preparation plant treating Indian coal especially Washery Grade IV coal with reference to Jamadoba New Coal Preparation Plant which was commissioned in 2018 with basis of selection of equipment and plant profile, application of reflux classifier in intermediate circuit and process design criteria is also outlined in this paper.

Keywords: intermediate circuit, overlapping process, reflux classifier

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Authors: Ali Mustafa Elshawesh, Mohamed Abdulali

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The paper presents an approach to dimension circuit switched networks and find the relationship between the parameters of the circuit switched networks on the condition of specific probability of call blocking. Our work is creating a Simulation code based on Erlang (B) formula to draw graphs which show two curves for each graph; one of simulation and the other of calculated. These curves represent the relationships between average number of calls and average call duration with the probability of call blocking. This simulation code facilitates to select the appropriate parameters for circuit switched networks.

Keywords: Erlang B formula, call blocking, telephone system dimension, Markov model, link capacity

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Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

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A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

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Authors: Kouider Bendine, Zouaoui Satla, Boukhoulda Farouk Benallel, Shun-Qi Zhang

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Turbine blades are subjected to a variety of loads, lead to an undesirable vibration. Such vibration can cause serious damages or even lead to a total failure of the blade. The present paper addresses the vibration control of turbine blade. The study aims to propose a passive vibration control using piezoelectric material. the passive control is effectuated by shunting an RL circuit to the piezoelectric patch in a parallel configuration. To this end, a Finite element model for the blade with the piezoelectric patch is implemented in ANSYS APDL. The model is then subjected to a harmonic frequency-based analysis for the case of control on and off. The results show that the proposed methodology was able to reduce blade vibration by 18%.

Keywords: blade, active piezoelectric vibration control, finite element., shunt circuit

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Authors: A. Kojah, A. Nacaroğlu

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Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase

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Authors: Mesbah Tarek, Kelaiaia Samia, Chiheb Sofien, Kelaiaia Mounia Samira, Labar Hocine

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Short circuit causes important damage in power systems. The aim of this paper is the investigation of the effect of short circuit at the AC side inverter in HVDC transmission line. The cutoff of HVDC transmission line implies important economic losses. In this paper it is proposed an efficient procedure which can protect and eliminate the fault quickly. The theoretical development and simulation are well detailed and illustrated.

Keywords: AC inverter, HVDC, short circuit, switcher gate, power system

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Authors: Debabrata Das

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This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

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Authors: Loubna Tani, Nabih Elouzzani

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Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in high-speed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Keywords: multiconductor transmission line, crosstalk, finite difference time domain (FDTD), printed-circuit board (PCB), rise time, statistical analysis

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

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A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: bridgeless boost (BLB), boost converter, power factor correction (PFC), hold-up time

Procedia PDF Downloads 384

Authors: Mesbah Tarek, Kelaiaia Samia, Chiheb Sofien, Kelaiaia Mounia Samira, Labar Hocine

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As every power systems short circuit failure can occur for HVDC at the DC link. So, the power devices should be protected against over heath produced by this over-current. This can be achieved through the power switchers or fast breaker. After short circuit the system is unable to restart, only after a time delay, because of the potential distribution along the DC link line. An appropriate fast and safety control is proposed and tested successfully. The detailed development and discussion of these faults is presented in this paper.

Keywords: HVDC, DC link, switchers, short circuit, faults

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Authors: Ahmed Nouainia, Mohamed Hajji, Taoufik Aguili

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In this paper, an electromagnetic analysis is presented for describing the influence of shielding in a rectangular waveguide. A hybridization based on the method of moments combined to the generalized equivalent circuit MoM-GEC is used to model the problem. This is validated by applying the MoM-GEC hybridization to investigate a diffraction structure. It consists of electromagnetic diffraction by an iris in a rectangular waveguide. Numerical results are shown and discussed and a comparison with FEM and Marcuvitz methods is achieved.

Keywords: method MoM-GEC, waveguide, shielding, equivalent circuit

Procedia PDF Downloads 332

Authors: Ahmed Hamida Boudinar, Noureddine Benouzza, Azeddine Bendiabdellah, Mohamed El Amine Khodja

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This paper describes a new diagnosis approach for identification of the progressive stator winding inter-turn short-circuit fault in induction motor. This approach is based on a simple monitoring of the combined information related to both magnitude and phase-angle obtained from the fundamental by the three line currents frequency analysis. In addition, to simplify the interpretation and analysis of the data; a new graphical tool based on a triangular representation is suggested. This representation, depending on its size, enables to visualize in a simple and clear manner, the existence of the stator inter-turn short-circuit fault and its discrimination with respect to a healthy stator. Experimental results show well the benefit and effectiveness of the proposed approach.

Keywords: induction motor, magnitude, phase-angle, spectral analysis, stator fault

Procedia PDF Downloads 334

Authors: Liew Hui Fang, Syed Idris Syed Hassan, Mohd Fareq Abd. Malek, Yufridin Wahab, Norshafinash Saudin

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The paper implementation new approach method applied into transforming lumped element circuit into microstrip line form for Butterworth low pass filter which is operating at LC band. The filter’s lumped element circuits and microstrip line form were first designed and simulated using Advanced Design Software (ADS) to obtain the best filter characteristic based on S-parameter and implemented on FR4 substrate for order N=3,4,5,6,7,8 and 9. The importance of a new approach of transforming method as a correction factor has been considered into designed microstrip line. From ADS simulation results proved that the response of microstrip line circuit of Butterworth low pass filter with fringing correction factor has an excellent agreement with its lumped circuit. This shows that the new approach of transforming lumped element circuit into microstrip line is able to solve the conventional design of complexity size of circuit of Butterworth low pass filter (LPF) into microstrip line.

Keywords: Butterworth low pass filter, number of order, microstrip line, microwave filter, maximally flat

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Authors: Zbigniew Olczykowski

Abstract:

The paper presents the impact of work on the electric arc furnace power grid. The arc furnace operating will be modeled at different power conditions of steelworks. The paper will describe how to determine the increase in voltage fluctuations caused by working in parallel arc furnaces. The analysis of indicators characterizing the quality of electricity recorded during several cycles of measurement made at the same time at three points grid, with different power and different short-circuit rated voltage, will be carried out. The measurements analysis presented in this paper were conducted in the mains of one of the Polish steel. The indicators characterizing the quality of electricity was recorded during several cycles of measurement while making measurements at three points of different power network short-circuit power and various voltage ratings. Measurements of power quality indices included the one-week measurement cycles in accordance with the EN-50160. Data analysis will include the results obtained during the simultaneous measurement of three-point grid. This will determine the actual propagation of interference generated by the device. Based on the model studies and measurements of quality indices of electricity we will establish the effect of a specific arc on the mains. The short-circuit power network’s minimum value will also be estimated, this is necessary to limit the voltage fluctuations generated by arc furnaces.

Keywords: arc furnaces, long-term flicker, measurement and modeling of power quality, voltage fluctuations

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Authors: Wirat Sonchan, Pratoom Moungmee, Anek Sootmongkol

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This study aimed to examine the effects of a circuit training program on muscle strength, agility, anaerobic performance and cardiovascular endurance. The study involved 24 freshmen (age 18.87+0.68 yr.) male students of the Faculty of Sport Science, Burapha University. They sample study were randomly divided into two groups: Circuit Training group (CT; n=12) and a Control group (C; n=12). Baseline data on height, weight, muscle strength (hand grip dynamometer and leg strength dynamometer), agility (agility T-Test), and anaerobic performance (Running-based Anaerobic Sprint Test) and cardiovascular endurance (20 m Endurance Shuttle Run Test) were collected. The circuit training program included one circuit of eight stations of 30/60 seconds of work/rest interval with two cycles in Week 1-4, and 60/90 seconds of work/rest interval with three cycles in Week 5-8, performed three times per week. Data were analyzed using paired t-tests and independent sample t-test. Statistically significance level was set at 0.05. The results show that after 8 weeks of a training program, muscle strength, agility, anaerobic capacity and cardiovascular endurance increased significantly in the CT Group (p < 0.05), while significant increase was not observed in the C Group (p < 0.05). The results of this study suggest that the circuit training program improved muscle strength, agility, anaerobic capacity and cardiovascular endurance of the study subjects. This program may be used as a guideline for selecting a set of exercise to improve physical fitness.

Keywords: circuit training, physical fitness, cardiovascular endurance, anaerobic performance

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Authors: Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu

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This paper proposed a high resolution Vernier Delay Line (VDL) measurement circuit with coarse and fine detection mechanism, which improved the trade-off problem between high resolution and less delay cells in traditional VDL circuits. And the measuring time of proposed measurement circuit is also under the high resolution requests. At first, the testing range of input signal which proposed high resolution delay line is detected by coarse detection VDL. Moreover, the delayed input signal is transmitted to fine detection VDL for measuring value with better accuracy. This paper is implemented at 0.18μm process, operating frequency is 100 MHz, and the resolution achieved 2.0 ps with only 16-stage delay cells. The test range is 170ps wide, and 17% stages saved compare with traditional single delay line circuit.

Keywords: vernier delay line, D-type flip-flop, DFF, metastable phenomenon

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm

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Authors: D. Touil, L. Ouadah

Abstract:

An industrial model of cement grinding circuit is proposed on the basis of sampling surveys undertaken in the Meftah cement plant in Algiers, Algeria. The ball mill is described by a series of equal fully mixed stages that incorporates the effect of air sweeping. The kinetic parameters of this material in the energy normalized form obtained using the data of batch dry ball milling are taken into account in developing the present scale-up procedure. The dynamic separator is represented by the air classifier selectivity equation corrected by empirical factors. The model is incorporated in computer program that predict full size distributions and mass flow rates for all streams in a circuit under a particular set of operating conditions.

Keywords: grinding circuit, clinker, cement, modeling, population balance, energy

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Authors: Madina Hamiane

Abstract:

Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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Authors: Aragorn Joaquin Pineda Dela Cruz

Abstract:

Road traffic congestion is continually deteriorating in Hong Kong. The largest contributing factor is the increase in vehicle fleet size, resulting in higher competition over the utilisation of road space. This study proposes a project that can process closed-circuit television images and videos to provide real-time traffic detection and prediction capabilities. Specifically, a deep-learning model involving computer vision techniques for video and image-based vehicle counting, then a separate model to detect and predict traffic congestion levels based on said data. State-of-the-art object detection models such as You Only Look Once and Faster Region-based Convolutional Neural Networks are tested and compared on closed-circuit television data from various major roads in Hong Kong. It is then used for training in long short-term memory networks to be able to predict traffic conditions in the near future, in an effort to provide more precise and quicker overviews of current and future traffic conditions relative to current solutions such as navigation apps.

Keywords: intelligent transportation system, vehicle detection, traffic analysis, deep learning, machine learning, computer vision, traffic prediction

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Authors: Yasunori Kobori, Li Quan, Shu Wu, Nizam Mohyar, Zachary Nosker, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi

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This paper proposes an electrolytic capacitor-less transformer-less AC-DC LED driver with a current ripple canceller. The proposed LED driver includes a diode bridge, a buck-boost converter, a negative feedback controller and a current ripple cancellation circuit. The current ripple canceller works as a bi-directional current converter using a sub-inductor, a sub-capacitor and two switches for controlling current flow. LED voltage is controlled in order to regulate LED current by the negative feedback controller using a current sense resistor. There are two capacitors which capacitance of 5 uF. We describe circuit topologies, operation principles and simulation results for our proposed circuit. In addition, we show the line regulation for input voltage variation from 85V to 130V. The output voltage ripple is 2V and the LED current ripple is 65 mA which is less than 20% of the typical current of 350 mA. We are now making the proposed circuit on a universal board in order to measure the experimental characteristics.

Keywords: LED driver, electrolytic, capacitor-less, AC-DC converter, buck-boost converter, current ripple canceller

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Authors: Maninder Kaur Gill, Alpana Agarwal

Abstract:

It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device Under Test (DUT), open loop voltage gain, operational amplifier, test circuit

Procedia PDF Downloads 404