Search results for: xor gate

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

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Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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Authors: Nelson Lujara

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The paper presents a practical three-phase PWM inverter suitable for low voltage, low rating energy efficient systems. The work in the paper is conducted with the view to establishing the significance of the loss contribution from the PWM inverter in the determination of the complete losses of a photovoltaic (PV) array-powered induction motor drive water pumping system. Losses investigated include; conduction and switching loss of the devices and gate drive losses. It is found that the PWM inverter operates at a reasonable variable efficiency that does not fall below 92% depending on the load. The results between the simulated and experimental results for the system with or without a maximum power tracker (MPT) compares very well, within an acceptable range of 2% margin.

Keywords: energy, inverter, losses, photovoltaic

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Authors: Dede Basturk, Metin Kaya, Halil Taskin, Nurtekin Erkmen

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In total, 29 students studying in Selçuk University Physical Training and Sports School who are recreationally active participated voluntarilyin this study which was carried out in order to examine effects of Vertimax trainings on agility, quickness and acceleration. 3 groups took their parts in this study as Vertimax training group (N=10), Ordinary training group (N=10) and Control group (N=9). Measurements were carried out in performance laboratory of Selçuk University Physical Training and Sports School. A training program for quickness and agility was followed up for subjects 3 days a week (Monday, Wednesday, Friday) for 8 weeks. Subjects taking their parts in vertimax training group and ordinary training group participated in the training program for quickness and agility. Measurements were applied as pre-test and post-test. Subjects of vertimax training group followed the training program with vertimax device and subjects of ordinary training group followed the training program without vertimax device. As to control group who are recreationally active, they did not participate in any program. 4 gate photocells were used for measuring and measurement of distances was carried out in m. Furthermore, single gate photocell and honi were used for agility test. Measurements started with 15 minutes of warm-up. Acceleration, quickness and agility tests were applied on subjects. 3 measurements were made for each subject at 3 minutes resting intervals. The best rating of three measurements was recorded. 5 m quickness pre-test value of vertimax training groups has been determined as 1,11±0,06 s and post-test value has been determined as 1,06 ± 0,08 s (P<0,05). 5 m quickness pre-test value of ordinary training group has been determined as 1,11±0,06 s and post-test value has been determined as 1,07±0,07 s (P<0,05).5 m quickness pre-test value of control group has been determined as 1,13±0,08 s and post-test value has been determined as 1,10 ± 0,07 s (P>0,05). Upon examination of 10 m acceleration value before and after the training, 10 m acceleration pre-test value of vertimax training group has been determined as 1,82 ± 0,07 s and post-test value has been determined as 1,76±0,83 s (P>0,05). 10 m acceleration pre-test value of ordinary training group has been determined as 1,83±0,05 s and post-test value has been determined as 1,78 ± 0,08 s (P>0,05).10 m acceleration pre-test value of control group has been determined as 1,87±0,11 s and post-test value has been determined as 1,83 ± 0,09 s (P>0,05). Upon examination of 15 m acceleration value before and after the training, 15 m acceleration pre-test value of vertimax training group has been determined as 2,52±0,10 s and post-test value has been determined as 2,46 ± 0,11 s (P>0,05).15 m acceleration pre-test value of ordinary training group has been determined as 2,52±0,05 s and post-test value has been determined as 2,48 ± 0,06 s (P>0,05). 15 m acceleration pre-test value of control group has been determined as 2,55 ± 0,11 s and post-test value has been determined as 2,54 ± 0,08 s (P>0,05).Upon examination of agility performance before and after the training, agility pre-test value of vertimax training group has been determined as 9,50±0,47 s and post-test value has been determined as 9,66 ± 0,47 s (P>0,05). Agility pre-test value of ordinary training group has been determined as 9,99 ± 0,05 s and post-test value has been determined as 9,86 ± 0,40 s (P>0,05). Agility pre-test value of control group has been determined as 9,74 ± 0,45 s and post-test value has been determined as 9,92 ± 0,49 s (P>0,05). Consequently, it has been observed that quickness and acceleration features were developed significantly following 8 weeks of vertimax training program and agility features were not developed significantly. It is suggested that training practices used for the study may be used for situations which may require sudden moves and in order to attain the maximum speed in a short time. Nevertheless, it is also suggested that this training practice does not make contribution in development of moves which may require sudden direction changes. It is suggested that productiveness and innovation may come off in terms of training by using various practices of vertimax trainings.

Keywords: vertimax, training, quickness, agility, acceleration

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Authors: Temitayo Abayomi Ewemoje, Oluwamayowa Oluwafemi Oluwaniyi

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Agriculture and food processing, industry are among the largest industrial sectors that uses large amount of energy. Thus, a larger amount of gases from their fuel combustion technologies is being released into the environment. The choice of input energy supply not only directly having affects the environment, but also poses a threat to human health. The study was therefore designed to assess each unit production processes in order to identify hotspots using life cycle assessments (LCA) approach in South-western Nigeria. Data such as machine power rating, operation duration, inputs and outputs of shea butter materials for unit processes obtained at site were used to modelled Life Cycle Impact Analysis on GaBi6 (Holistic Balancing) software. Four scenarios were drawn for the impact assessments. Material sourcing from Kaiama, Scenarios 1, 3 and Minna Scenarios 2, 4 but different heat supply sources (Liquefied Petroleum Gas ‘LPG’ Scenarios 1, 2 and 10.8 kW Diesel Heater, scenarios 3, 4). Modelling of shea butter production on GaBi6 was for 1kg functional unit of shea butter produced and the Tool for the Reduction and Assessment of Chemical and other Environmental Impacts (TRACI) midpoint assessment was tool used to was analyse the life cycle inventories of the four scenarios. Eight categories in all four Scenarios were observed out of which three impact categories; Global Warming Potential (GWP) (0.613, 0.751, 0.661, 0.799) kg CO2¬-Equiv., Acidification Potential (AP) (0.112, 0.132, 0.129, 0.149) kg H+ moles-Equiv., and Smog (0.044, 0.059, 0.049, 0.063) kg O3-Equiv., categories had the greater impacts on the environment in Scenarios 1-4 respectively. Impacts from transportation activities was also seen to contribute more to these environmental impact categories due to large volume of petrol combusted leading to releases of gases such as CO2, CH4, N2O, SO2, and NOx into the environment during the transportation of raw shea kernel purchased. The ratio of transportation distance from Minna and Kaiama to production site was approximately 3.5. Shea butter unit processes with greater impacts in all categories was the packaging, milling and with the churning processes in ascending order of magnitude was identified as hotspots that may require attention. From the 1kg shea butter functional unit, it was inferred that locating production site at the shortest travelling distance to raw material sourcing and combustion of LPG for heating would reduce all the impact categories assessed on the environment.

Keywords: GaBi6, Life cycle assessment, shea butter production, TRACI

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Authors: Abdelghafour Galadi

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In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: power MOSFET, drift layer, quasi-saturation effect, SPICE model

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Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

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In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: analytical analysis, hybrid resonant inverter, reactive transformer, response surface method

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Authors: Yiqiang Ni, Xuanlong Chen, Enliang Li, Linting Zheng, Shizheng Yang

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Bipolar ICs are playing an important role in military applications, mainly used in logic gates, such as inverter and NAND gate. The defect of metal break located on the step is one of the main failure mechanisms of bipolar ICs, resulting in open-circuit or functional failure. In this situation, general failure localization methods like optical beam-induced resistance change (OBIRCH) and photon emission microscopy (PEM) might not be fully effective. However, active voltage contrast (AVC) can be used as a voltage probe, which may pinpoint the incorrect potential and thus locate the failure position. Two case studies will be present in this paper on how to implement AVC for failure localization, and the detailed failure mechanism will be discussed.

Keywords: bipolar IC, failure localization, metal break, open failure, voltage contrast

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Authors: Nagaraju Jarugu, B. R. Narendra

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This paper focused on boost rectification by Single Phase Matrix Converter with fewer numbers of switches. The conventional matrix converter consists of 4 bidirectional switches, i.e. 8 set of IGBT/MOSFET with anti-parallel diodes. In this proposed matrix converter, only six switches are used. The switch commutation arrangements are also carried out in this work. The SPMC topology has many advantages as a minimal passive device use. It is very flexible and it can be used as a lot of converters. The gate pulses to the switches are provided by the PWM techniques. The duty ratio of the switches based on Pulse Width Modulation (PWM) technique was used to produce the output waveform of the circuit, simply by turning ON and OFF the switches. The simulation results using MATLAB/Simulink were provided to validate the feasibility of this proposed method.

Keywords: single phase matrix converter, reduced switches, AC voltage regulators, boost rectifier operation

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Authors: Kuan Yu Lin, Shih Chih Chen

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This study focuses on the Al/HfO₂/Si/Al structure to explore the electrical properties of the structure. This experiment uses a radio frequency magnetron sputtering system to deposit high dielectric materials on p-type silicon substrates of 1~10 Ω-cm (100). Consider the hafnium dioxide film as a dielectric layer. Post-deposition annealing at 750°C in nitrogen atmosphere. Electron beam evaporation of metallic aluminum is then used to complete the top/bottom electrodes. The metal is post-annealed at 450°C for 20 minutes in a nitrogen environment to complete the MOS component. Its dielectric constant, equivalent oxide layer thickness, oxide layer defects, and leakage current mechanism are discussed. At PDA 750°C-5s, the maximum k value was found to be 21.2, and the EOT was 3.68nm.

Keywords: high-k gate dielectrics, HfO₂, post deposition annealing, RF magnetic

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Authors: Ahmed Nassim Moulai Khatir

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Fin field effect transistors (FinFETs) deliver superior levels of scalability than the classical structure of MOSFETs by offering the elimination of short channel effects. Modern FinFETs are 3D structures that rise above the planar substrate, but some of these structures have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections usually used. Fin cross section shape of FinFETs results in some device issues, like potential distribution performance. This work analyzes that impact with three-dimensional numeric simulation of several triple-gate FinFETs with various top and bottom widths of fin. Results of the simulation show that the potential distribution and the electrical field in the fin depend on the sidewall inclination angle.

Keywords: FinFET, cross section shape, SILVACO, trapezoidal FinFETs

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Authors: S. Belhour, A. K. Ferouani, C. Azizi

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In recent years, a considerable effort (experience, numerical simulation, and theoretical prediction models) has characterised by high efficiency and low cost. Then an improved physics analytical model for simulating is proposed. The performance of GaAs MESFETs has been developed for use in device design for high frequency. This model is based on mathematical analysis, and a new approach for the standard model is proposed, this approach allowed to conceive applicable model for MESFET’s operating in the turn-one or pinch-off region and valid for the short-channel and the long channel MESFET’s in which the two dimensional potential distribution contributed by the depletion layer under the gate is obtained by conventional approximation. More ever, comparisons between the analytical models with different values of mobility are proposed, and a good agreement is obtained.

Keywords: analytical, gallium arsenide, MESFET, mobility, models

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Authors: Peter Tabatt, Christian Siemers

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Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs.

Keywords: reconfigurable FPGA, cellular automata, partitioning, metrics, parallel computing

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Authors: Edward J. Kansa, Pavel Holoborodko

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Continuously differentiable radial basis functions (RBFs) are meshfree, converge faster as the dimensionality increases, and is theoretically spectrally convergent. When implemented on current single and double precision computers, such RBFs can suffer from ill-conditioning because the systems of equations needed to be solved to find the expansion coefficients are full. However, the Advanpix extended precision software package allows computer mathematics to resemble asymptotically ideal Platonic mathematics. Additionally, full systems with extended precision execute faster graphical processors units and field-programmable gate arrays because no branching is needed. Sparse equation systems are fast for iterative solvers in a very limited number of cases.

Keywords: partial differential equations, Meshfree radial basis functions, , no restrictions on spatial dimensions, Extended arithmetic precision.

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Authors: Semih Demir, Anil Celebi

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Circuit switched networks widely used until the end of the 20^th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.

Keywords: clock recovery on TDMoIP, FPGA, MATLAB reference model, clock synchronization

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Authors: F. Lhafiane, A. Elbyed, M. Bouchoum

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The design of Reverse logistics Network has attracted growing attention with the stringent pressures from both environmental awareness and business sustainability. Reverse logistical activities include return, remanufacture, disassemble and dispose of products can be quite complex to manage. In addition, demand can be difficult to predict, and decision making is one of the challenges tasks. This complexity has amplified the need to develop an integrated architecture for product return as an enterprise system. The main purpose of this paper is to design Multi agent system (MAS) architecture using the Prometheus methodology to efficiently manage reverse logistics processes. The proposed MAS architecture includes five types of agents: Gate keeping Agent, Collection Agent, Sorting Agent, Processing Agent and Disposal Agent which act respectively during the five steps of reverse logistics Network.

Keywords: reverse logistics, multi agent system, prometheus methodology

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Authors: Nafiseh Ebrahimi, Gautham Muthukumaran, Amir Jafari

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Human walking gait is considered to be the most efficient biped walking gait. There are various types of gait human follows during locomotion and arm swing is one of the most important factors which controls and differentiates human gaits. Earlier studies declared a 7% reduction in the metabolic cost due to the arm swing. In this research, we compared different types of arm swings in terms of metabolic cost reduction and then suggested, designed, fabricated and tested a quasi-passive upper body exoskeleton to study the metabolic cost reduction in the folded arm walking gate scenarios. Our experimental results validate a 10% reduction in the metabolic cost of walking aided by the application of the proposed exoskeleton.

Keywords: arm swing, MET (metabolic equivalent of a task), calorimeter, oxygen consumption, upper body quasi-passive exoskeleton

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: Long Kim Vu

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The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

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Authors: T. Angeline Priyanka, R. Ganesan

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Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Mahmoud Owais

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Public Transit (P.T) is very important means to reduce traffic congestion, to improve urban environmental conditions and consequently affects people social lives. Planning, designing and management of P.T are the key issues for offering a competitive mode that can compete with the private transportation. These transportation planning, designing and management issues are addressed in the Transit Network Design Problem (TNDP). It deals with a complete hierarchy of decision making process. It includes strategic, tactical and operational decisions. The main body of TNDP is two stages, namely; route design stage and frequency setting. The TNDP is extensively studied in the last five decades; however the research gate is still widely open due to its many practical and modeling challenges. In this paper, a comprehensive background is given to illustrate the issues and challenges related to the TNDP to help in directing the incoming researches towards the untouched areas of the problem.

Keywords: frequency setting, network design, transit planning, urban planning

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Q. R. Cheah, Y. F. Tan

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In modern times, the push for a low carbon footprint entails achieving carbon neutrality as a goal for future generations. One possible step towards carbon footprint reduction is the use of more durable materials with longer lifespans, for example, silicone data cableswhich show at least double the lifespan of similar plastic products. By having greater durability and longer lifespans, silicone data cables can reduce the amount of trash produced as compared to plastics. Furthermore, silicone products don’t produce micro contamination harmful to the ocean. Every year the electronics industry produces an estimated 5 billion data cables for USB type C and lightning data cables for tablets and mobile phone devices. Material usage for outer jacketing is 6 to 12 grams per meter. Tests show that the product lifespan of a silicone data cable over plastic can be doubled due to greater durability. This can save at least 40,000 tonnes of material a year just on the outer jacketing of the data cable. The facility in this study specialises in compounding of liquid silicone rubber (LSR) material for the extrusion process in jacketing for the silicone data cable. This study analyses the carbon emissions from the facility, which is presently capable of producing more than 1,000 tonnes of LSR annually. This study uses guidelines from the World Business Council for Sustainable Development (WBCSD) and World Resources Institute (WRI) to define the boundaries of the scope. The scope of emissions is defined as 1. Emissions from operations owned or controlled by the reporting company, 2. Emissions from the generation of purchased or acquired energy such as electricity, steam, heating, or cooling consumed by the reporting company, and 3. All other indirect emissions occurring in the value chain of the reporting company, including both upstream and downstream emissions. As the study is limited to the compounding facility, the system boundaries definition according to GHG protocol is cradle-to-gate instead of cradle-to-grave exercises. Malaysia’s present electricity generation scenario was also used, where natural gas and coal constitute the bulk of emissions. Calculations show the LSR produced for the silicone data cable with high fire retardant capability has scope 1 emissions of 0.82kg CO2/kg, scope 2 emissions of 0.87kg CO2/kg, and scope 3 emissions of 2.76kg CO2/kg, with a total product carbon footprint of 4.45kg CO2/kg. This total product carbon footprint (Cradle-to-gate) is comparable to the industry and to plastic materials per tonne of material. Although per tonne emission is comparable to plastic material, due to greater durability and longer lifespan, there can be significantly reduced use of LSR material. Suggestions to reduce the calculated product carbon footprint in the scope of emissions involve 1. Incorporating the recycling of factory silicone waste into operations, 2. Using green renewable energy for external electricity sources and 3. Sourcing eco-friendly raw materials with low GHG emissions.

Keywords: carbon footprint, liquid silicone rubber, silicone data cable, Malaysia facility

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Authors: L. Giraudet, O. Simonetti, G. de Tournadre, N. Dumelié, B. Clarenc, F. Reisdorffer

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In this paper we intend to give a comprehensive view of the saturation misbehavior of thin film transistors (TFTs) based on disordered semiconductors, such as most organic TFTs, and its link to the field activation of the mobility. Experimental evidence of the field activation of the mobility is given for disordered semiconductor based TFTs, when reducing the gate length. Saturation misbehavior is observed simultaneously. Advanced transport models have been implemented in a quasi-2D numerical TFT simulation software. From the numerical simulations it is clearly established that field activation of the mobility alone cannot explain the saturation misbehavior. Evidence is given that high longitudinal field gradient at the drain end of the channel is responsible for an excess charge accumulation, preventing saturation. The two combined effects allow reproducing the experimental output characteristics of short channel TFTs, with S-shaped characteristics and saturation failure.

Keywords: mobility field activation, numerical simulation, OTFT, saturation failure

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Authors: Rabail Shafique Satti, Sidra Ejaz, Madiha Arshad, Marwa Khalid, Sadia Majeed

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The paper presents the development of an automated security system to automate the entry of visitors, providing more flexibility of managing their record and securing homes or workplaces. Face recognition is part of this system to authenticate the visitors. A cost effective and SMS based door security module has been developed and integrated with the GSM network and made part of this system to allow communication between system and owner. This system functions in real time as when the visitor’s arrived it will detect and recognizes his face and on the result of face recognition process it will open the door for authorized visitors or notifies and allows the owner’s to take further action in case of unauthorized visitor. The proposed system is developed and it is successfully ensuring security, managing records and operating gate without physical interaction of owner.

Keywords: SMS, e-mail, GSM modem, authenticate, face recognition, authorized

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Authors: Mojtaba Valinataj

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Nowadays reversible logic has received many attentions as one of the new fields for reducing the power consumption. On the other hand, the processing systems have weaknesses against different external effects. In this paper, some error detecting reversible logic serial multipliers are proposed by incorporating the parity-preserving gates. This way, the new designs are presented for signed parity-preserving serial multipliers based on the Booth's algorithm by exploiting the new arrangements of existing gates. The experimental results show that the proposed 4×4 multipliers in this paper reach up to 20%, 35%, and 41% enhancements in the number of constant inputs, quantum cost, and gate count, respectively, as the reversible logic criteria, compared to previous designs. Furthermore, all the proposed designs have been generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.

Keywords: Booth’s algorithm, error detection, multiplication, parity-preserving gates, quantum computers, reversible logic

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Authors: Florian Gschösser, Walter Purrer

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The paper shows examples for the (environmental) optimization of production processes for asphalt mixtures applied for typical road pavements in Austria and Switzerland. The conducted “from-cradle-to-gate” LCA firstly analyzes the production one cubic meter of asphalt and secondly all material production processes for exemplary highway pavements applied in Austria and Switzerland. It is shown that environmental impacts can be reduced by the application of reclaimed asphalt pavement (RAP) and by the optimization of specific production characteristics, e.g. the reduction of the initial moisture of the mineral aggregate and the reduction of the mixing temperature by the application of low-viscosity and foam bitumen. The results of the LCA study demonstrate reduction potentials per cubic meter asphalt of up to 57 % (Global Warming Potential–GWP) and 77 % (Ozone depletion–ODP). The analysis per square meter of asphalt pavement determined environmental potentials of up to 40 % (GWP) and 56 % (ODP).

Keywords: asphalt mixtures, environmental potentials, life cycle assessment, material production

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Authors: A. Boursali, A. Guen-Bouazza

Abstract:

We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

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