Search results for: high power CMOS switch

Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on instrumentation amplifier and it is useful for reducing offset in Wheatstone bridge. The obtained gain is 645 with 1 μv/°c equivalent drift and 1.58 mw power consumption. A Schmitt trigger and multiplexer circuit control output node. A high speed counter is designed in this work. The proposed circuit is designed and simulated in 0.18 μm CMOS technology with 1.8 v power supply.

Keywords: piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: Abdar Ali, Rizwan Ullah, Zahid Ullah

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This paper focuses on the study of DC-to-DC converters, which are suitable for low-voltage high-power applications. The output voltages generated by renewable energy sources such as photovoltaic arrays and fuel cell stacks are generally low and required to be increased to high voltage levels. Development of DC-to-DC converters, which provide high step-up voltage conversion ratios with high efficiencies and low voltage stresses is one of the main issues in the development of renewable energy systems. A procedure for three converters-conventional DC-to-DC converter, interleaved boost converter, and isolated flyback based converter, is illustrated for a given set of specifications. The selection among the converters for the given application is based on the voltage conversion ratio, efficiency, and voltage stresses.

Keywords: flyback converter, interleaved boost, photovoltaic array, fuel cell, switch stress, voltage conversion ratio, renewable energy

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Authors: Bernardo Cedano, Ahmed H. Eltom, Bob Hay, Jim Glass, Raga Ahmed

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The deployment of smart grid devices such as smart meters and smart switches (SS) supported by a reliable and fast communications system makes automated distribution possible, and thus, provides great benefits to electric power consumers and providers alike. However, more research is needed before the full utility of smart switch data is realized. This paper presents new automated switching techniques using SS within the electric power grid. A concise background of the SS is provided, and operational examples are shown. Organization and presentation of data obtained from SS are shown in the context of the future goal of total automation of the distribution network. The description of application techniques, the examples of success with SS, and the vision outlined in this paper serve to motivate future research pertinent to disturbance analysis automation.

Keywords: disturbance automation, electric power grid, smart grid, smart switches

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Authors: Hyungil Chae

Abstract:

This work presents a method to reduce spinning current of a Hall-effect sensor for low-power magnetic sensor applications. Spinning current of a Hall-effect sensor changes the direction of bias current periodically and can separate signals from DC-offset. The bias current is proportional to the sensor sensitivity but also increases the power consumption. To achieve both high sensitivity and low power consumption, the bias current can be pulse-width modulated. When the bias current duration Tb is reduced by a factor of N compared to the spinning current period of Tₛ/2, the total power consumption can be saved by N times. N can be large as long as the Hall-effect sensor settles down within Tb. The proposed scheme is implemented and simulated in a 0.18um CMOS process, and the power saving factor is 9.6 when N is 10. Acknowledgements: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (20160001360022003, Development of Hall Semi-conductor for Smart Car and Device).

Keywords: chopper stabilization, Hall-effect sensor, pulse width modulation, spinning current

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Authors: H. Alheeh, M. Alameri, A. Al Tarabsheh

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There has been a growing interest in CMOS-based sensors technology in cameras as they afford low-power, small-size, and cost-effective imaging systems. This article describes the CMOS image sensor pixel categories and presents the design and the simulation of the 3-Transistor (3T) Active Pixel Sensor (APS) in MATLAB/Simulink tool. The analysis investigates the conversion of the light into an electrical signal for a single pixel sensing circuit, which consists of a photodiode and three NMOS transistors. The paper also proposes three modes for the pixel operation; reset, integration, and readout modes. The simulations of the electrical signals for each of the studied modes of operation show how the output electrical signals are correlated to the input light intensities. The charging/discharging speed for the photodiodes is also investigated. The output voltage for different light intensities, including in dark case, is calculated and showed its inverse proportionality with the light intensity.

Keywords: APS, CMOS image sensor, light intensities photodiode, simulation

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Authors: Dominic Huschke, Rudolf Keil

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New driving functionalities like highly automated driving have a major impact on the electrics/electronics architecture of future vehicles and inevitably lead to higher safety requirements. Partly due to these increased requirements, the vehicle industry is increasingly looking at semiconductor switches as an alternative to conventional melting fuses. The protective functionality of semiconductor switches can be implemented in hardware as well as in software. A current approach discussed in science and industry is the implementation of a model of the protected low voltage power cable on a microcontroller to calculate its temperature. Here, the information regarding the current is provided by the continuous current measurement of the semiconductor switch. The signal to open the semiconductor switch is provided by the microcontroller when a previously defined limit for the temperature of the low voltage power cable is exceeded. A setup for the testing of the described principle for electronic fuse protection of a low voltage power cable is built and successfullyvalidated with experiments afterwards. Here, the evaluation criterion is the deviation of the measured temperature of the low voltage power cable from the specified limit temperature when the semiconductor switch is opened. The analysis is carried out with an assumed ambient temperature as well as with a measured ambient temperature. Subsequently, the experimentally performed investigations are simulated in a virtual environment. The explicit focus is on the simulation of the behavior of the microcontroller with an implemented model of a low voltage power cable in a real-time environment. Subsequently, the generated results are compared with those of the experiments. Based on this, the completely virtual design of the described approach is assumed to be valid.

Keywords: automotive wire harness, electronic fuse protection, low voltage power cable, semiconductor-based fuses, software-based validation

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Authors: Nissar Mohammad Karim, Norhayati Soin

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To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, Sol-Gel, precursor aging, aging

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Authors: Miky Lee, K. Kim, D. Lim, D. Cho

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This paper presents the planning, rationale for test specification derivation, sampling requirements, test facilities, and result analysis used to conduct lifetime expectancy endurance tests on power window switches (PWS) considering thermally induced mechanical stress under diurnal cyclic temperatures during normal operation (power cycling). The detail process of analysis and test results on the selected PWS set were discussed in this paper. A statistical approach to ‘life time expectancy’ was given to the measurement standards dealing with PWS lifetime determination through endurance tests. The approach choice, within the framework of the task, was explained. The present task was dedicated to voltage drop measurement to derive lifetime expectancy while others mostly consider contact or surface resistance. The measurements to perform and the main instruments to measure were fully described accordingly. The failure data from tests were analyzed to conclude lifetime expectancy through statistical method using Weibull cumulative distribution function. The first goal of this task is to develop realistic worst case lifetime endurance test specification because existing large number of switch test standards cannot induce degradation mechanism which makes the switches less reliable. 2nd goal is to assess quantitative reliability status of PWS currently manufactured based on test specification newly developed thru this project. The last and most important goal is to satisfy customer’ requirement regarding product reliability.

Keywords: power window switch, endurance test, Weibull function, reliability, degradation mechanism

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Authors: Nissar Mohammad Karim, Norhayati Soin

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To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, sol-gel, precursor ageing, metallurgical and materials engineering

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

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Authors: Anil Kumar Pandey

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Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: power integrity, power-aware signal integrity analysis, electromagnetic simulation, channel simulation

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Authors: Kittipong Tripetch

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This paper proposes for the first time symbolic formula of the power spectrum of cross couple oscillator and its modified circuit. Many principle existed to derived power spectrum in microwave textbook such as impedance, admittance parameters, ABCD, H parameters, etc. It can be compared by graph of power spectrum which methodology is the best from the point of view of practical measurement setup such as condition of impedance parameter which used superposition of current to derived (its current injection of the other port of the circuit is zero, which is impossible in reality). Four Graphs of impedance parameters of cross couple oscillator is proposed. After that four graphs of Scattering parameters of cross couple oscillator will be shown.

Keywords: optimization, power spectrum, impedance parameters, scattering parameter

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Authors: Atabak Rashidian

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In duplex backhaul wireless communication systems, two separate transmit and receive high-gain antennas are required if an antenna switch is not implemented. Although the switch loss, which is considerable and in the order of 1.5 dB at 60 GHz, is avoided, the large separate antenna systems make the design bulky and not cost-effective. To avoid two large reflectors for such a system, transmit and receive antenna feeds with a common phase center are required. The phase center should coincide with the focal point of the reflector to maximize the efficiency and gain. In this work, we present an ultra-compact design in which stacked patch antennas are used as the feeds for a 12-inch reflector. The transmit antenna is a 1 × 2 array and the receive antenna is a single element located in the middle of the transmit antenna elements. Antenna elements are designed as stacked patches to provide the required impedance bandwidth for four standard channels of WiGigTM applications. The design includes three metallic layers and three dielectric layers, in which the top dielectric layer is a 100 µm-thick protective layer. The top two metallic layers are specified to the main and parasitic patches. The bottom layer is basically ground plane with two circular openings (0.7 mm in diameter) having a center through via which connects the antennas to a single input/output Si-Ge Bi-CMOS transceiver chip. The reflection coefficient of the stacked patch antenna is fully investigated. The -10 dB impedance bandwidth is about 11%. Although the gap between transmit and receive antenna is very small (g = 0.525 mm), the mutual coupling is less than -12 dB over the desired frequency band. The three dimensional radiation patterns of the transmit and receive reflector antennas at 60 GHz is investigated over the impedance bandwidth. About 39 dBi realized gain is achieved. Considering over 15 dBm of output power of the silicon chip in the transmit side, the EIRP should be over 54 dBm, which is good enough for over one kilometer multi Gbps data communications. The performance of the reflector antenna over the bandwidth shows the peak gain is 39 dBi and 40 dBi for the reflector antenna with 2-element and single element feed, respectively. This type of the system design is cost-effective and efficient.

Keywords: Antenna, integrated circuit, millimeter-wave, phase center

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Authors: Tanmaya Pradhan, K. Midhun, M. Joy Thomas

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Increasing the shelf life and improving the quality are important objectives for the success of packaged liquid food industry. One of the methods by which this can be achieved is by deactivating the micro-organisms present in the liquid food through pasteurization. Pasteurization is done by heating, but some serious disadvantages such as the reduction in food quality, flavour, taste, colour, etc. were observed because of heat treatment, which leads to the development of newer methods instead of pasteurization such as treatment using UV radiation, high pressure, nuclear irradiation, pulsed electric field, etc. In recent years the use of the pulsed electric field (PEF) for inactivation of the microbial content in the food is gaining popularity. PEF uses a very high electric field for a short time for the inactivation of microorganisms, for which we require a high voltage pulsed power source. Pulsed power sources used for PEF treatments are usually in the range of 5kV to 50kV. Different pulse shapes are used, such as exponentially decaying and square wave pulses. Exponentially decaying pulses are generated by high power switches with only turn-on capacity and, therefore, discharge the total energy stored in the capacitor bank. These pulses have a sudden onset and, therefore, a high rate of rising but have a very slow decay, which yields extra heat, which is ineffective in microbial inactivation. Square pulses can be produced by an incomplete discharge of a capacitor with the help of a switch having both on/off control or by using a pulse forming network. In this work, a pulsed power-based system is designed with the help of high voltage capacitors and solid-state switches (IGBT) for the inactivation of pathogenic micro-organism in liquid food such as fruit juices. The high voltage generator is based on the Marx generator topology, which can produce variable amplitude, frequency, and pulse width according to the requirements. Liquid food is treated in a chamber where pulsed electric field is produced between stainless steel electrodes using the pulsed output voltage of the supply. Preliminary bacterial inactivation tests were performed by subjecting orange juice inoculated with Escherichia Coli bacteria. With the help of the developed pulsed power source and the chamber, the inoculated orange has been PEF treated. The voltage was varied to get a peak electric field up to 15kV/cm. For a total treatment time of 200µs, a 30% reduction in the bacterial count has been observed. The detailed results and analysis will be presented in the final paper.

Keywords: Escherichia coli bacteria, high voltage generator, microbial inactivation, pulsed electric field, pulsed forming line, solid-state switch

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Authors: Zina Saheb, Ezz El-Masry

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As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

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Authors: Madina Hamiane

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Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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Authors: David Hasurungan

Abstract:

This paper objective is to assess the power distribution reliability improvement by retrofitting obsolete vacuum contactor. The case study in Badak Liquefied Natural Gas (LNG) plant is presented in this paper. To support plant operational, Badak LNG is equipped with 4.16 kV switchgear for supplying the storage and loading facilities, utilities facilities, and train facilities. However, there is a problem in two switch gears of sixteen switch gears. The problem is the obsolescence issue in its vacuum contactor. Not only that, but the same switchgear also has suffered from electrical fault due to contact fingering misalignment. In order to improve the reliability in switchgear, the vacuum contactor retrofit project is done. The retrofit will introduce new vacuum contactor design. The comparison between existing design and the new design is presented in this paper. Meanwhile, The reliability assessment and calculation are performed using software Reliasoft 7.

Keywords: reliability, obsolescence, retrofit, vacuum contactor

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Authors: Said Rabah Azzam, Andrew Graham

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Fragmentation of packets caused by encryption applied on the network layer of the IOS model in Internet Protocol version 4 (IPv4) networks as well as the possibility of using fragmentation and Access Control Lists (ACLs) as a method of restricting network access to certain hosts or areas of a network.Using default settings, fragmentation is expected to occur and each fragment to be reassembled at the other end. If this does not occur then a high number of ICMP messages should be generated back towards the source host indicating that the packet is too large and that it needs to be made smaller. This result is also expected when the MTU is changed for certain links between devices.When using ACLs and packet fragments to restrict access to hosts or network segments it is possible that ACLs cannot be set up in this way. If ACLs cannot be setup to allow only fragments then it is a limitation of the hardware’s firmware holding back this particular method. If the ACL on the restricted switch can be set up in such a way to allow only fragments then a connection that forces packets to fragment should be allowed to pass through the ACL. This should then make a network connection to the destination machine allowing data to be sent to and from the destination machine. ICMP messages from the restricted access switch and host should also be blocked from being sent back across the link which will be shown in an SSH session into the switch.

Keywords: fragmentation, encryption, security, switch

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Authors: Bendiabdellah Azzeddine, Cherif Bilal Djamal Eddine

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The three-phase power converter voltage structure is widely used in many power applications but its failure can lead to partial or total loss of control of the phase currents and can cause serious system malfunctions or even a complete system shutdown. To ensure continuity of service in all circumstances, effective and rapid techniques of detection and location of inverter fault is to be implemented. The present paper is dedicated to open-circuit fault detection in a three-phase two-level inverter fed induction motor. For detection purpose, the proposed contribution addresses the Park’s current vectors associated to a polar coordinates calculation tool to compute the exact value of the fault angle corresponding directly to the faulty IGBT switch. The merit of the proposed contribution is illustrated by experimental results.

Keywords: diagnosis, detection, Park’s vectors, polar coordinates, open-circuit fault, inverter, IGBT switch

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Authors: Su Yin Chiam, Qing Xin Zhang, Jaehoon Chung

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Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have obtained increased attention in the biosensor community because CMOS technology provides cost-effective and high-performance signal processing at a mass-production level. In order to supply biological samples and reagents effectively to the sensing elements, there are increasing demands for seamless integration of microfluidic components on the fabricated CMOS wafers by post-processing. Although the PDMS microfluidic channels replicated from separately prepared silicon mold can be typically aligned and bonded onto the CMOS wafers, it remains challenging owing the inherently limited aligning accuracy ( > ± 10 μm) between the two layers. Here we present a new post-processing method to create three-dimensional microfluidic components using two different polarities of photoresists, an epoxy-based negative SU-8 photoresist and positive SPR220-7 photoresist. The positive photoresist serves as a sacrificial layer and the negative photoresist was utilized as a structural material to generate three-dimensional structures. Because both photoresists are patterned using a standard photolithography technology, the dimensions of the structures can be effectively controlled as well as the alignment accuracy, moreover, is dramatically improved (< ± 2 μm) and appropriately can be adopted as an alternative post-processing method. To validate the proposed processing method, we applied this technique to build cell-trapping structures. The SU8 photoresist was mainly used to generate structures and the SPR photoresist was used as a sacrificial layer to generate sub-channel in the SU8, allowing fluid to pass through. The sub-channel generated by etching the sacrificial layer works as a cell-capturing site. The well-controlled dimensions enabled single-cell capturing on each site and high-accuracy alignment made cells trapped exactly on the sensing units of CMOS biosensors.

Keywords: SU-8, microfluidic, MEMS, microfabrication

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Authors: Abdalla Mohamed Eblabla

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Due to the high increase and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E, and F are the main techniques for realizing power amplifiers. An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), gallium nitride (GaN), Agilent’s Advanced Design System (ADS), lumped elements

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Mads Kirk Larsen

Abstract:

Strict air pollution control is today high on the agenda world-wide. By reducing the particular emission, not only the mg/Nm3 will be reduced – also parts of mercury and other hazardous matters attached to the particles will be reduced. Furthermore, it is possible to catch the fine particles (PM2.5). For particulate control, the precipitators are still the preferred choice and much efforts have been done to improve the efficiencies. Many ESP’s have seen electrical upgrading by changing the traditional 1 phase power system into either 3 phase or SMPS (High Frequency) units. However, there exist a 4th type of power supply – the pulse type. This is unfortunately widely unknown, but may be of great benefit to power plants. The FLSmidth type is called COROMAX® and it is a high voltage pulse generator for precipitators using a semiconductor switch operating at medium potential. The generated high voltage pulses have rated amplitude of 80 kV and duration of 75 μs and are superimposed on a variable base voltage of 60 kV rated voltage. Hereby, achieving a peak voltage of 140 kV. COROMAX® has the ability to increase the voltage beyond the natural spark limit inside the precipitator. Voltage levels may often be twice as high after installation of COROMAX®. Hereby also the migration velocity increases and thereby the efficiency. As the collection efficiency is proportional to the voltage peak and mean values, this also increases the collection efficiency of the fine particles where test has shown 80% removal of particles less than 0.07 micron. Another great advantage is the indifference to back-corona. Simultaneously with emission reduction, the power consumption will also be reduced. Another great advantage of the COROMAX® system is that the emission can be improved without the need to change the internal parts or enlarge the ESP. Recently, more than 150 units have been installed in China, where emissions have been reduced to ultra-low levels.

Keywords: eleectrostatic precipitator, high resistivity dust, micropulse energization, particulate removal

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Authors: Tatsuya Takino, Izuru Nomura, Yuji Kageyama, Shin Nagata, Hiroyuki Kamata

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We propose a method of detecting the craters from the image of the lunar surface. This proposal assumes that it is applied to SLIM (Smart Lander for Investigating Moon) working group aiming at the pinpoint landing on the lunar surface and investigating scientific research. It is difficult to equip and use high-performance computers for the small space probe. So, it is necessary to use a small computer with an exclusive hardware such as FPGA. We have studied the crater detection using principal component analysis (PCA), In this paper, We implement detection algorithm into the FPGA, and the detection is performed on the data that was captured from the CMOS camera.

Keywords: crater detection, PCA, FPGA, image processing

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Authors: H. Akhloufi, M. Hulscher, J. M. Prins, I. H. Van Der Sijs, D. Melles, A. Verbon

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Background: A timely switch from intravenous to oral antibiotic therapy has many advantages, such as reduced incidence of IV-line related infections, a decreased hospital length of stay and less workload for healthcare professionals with equivalent patient safety. Additionally, numerous studies have demonstrated significant decreases in costs of a timely intravenous to oral antibiotic therapy switch, while maintaining efficacy and safety. However, a considerable variation in iv to oral antibiotic switch therapy criteria has been described in literature. Here, we report the development of a set of iv to oral switch criteria that are generally applicable in all hospitals. Material/methods: A RAND-modified Delphi procedure, which was composed of 3 rounds, was used. This Delphi procedure is a widely used structured process to develop consensus using multiple rounds of questionnaires within a qualified panel of selected experts. The international expert panel was multidisciplinary and composed out of clinical microbiologists, infectious disease consultants and clinical pharmacists. This panel of 19 experts appraised 6 major intravenous to oral antibiotic switch therapy criteria and operationalized these criteria using 41 measurable conditions extracted from the literature. The procedure to select a concise set of iv to oral switch criteria included 2 questionnaire rounds and a face-to-face meeting. Results: The procedure resulted in the selection of 16 measurable conditions, which operationalize 6 major intravenous to oral antibiotic switch therapy criteria. The following 6 major switch therapy criteria were selected: (1) Vital signs should be good or improving when bad. (2) Signs and symptoms related to the infection have to be resolved or improved. (3) The gastrointestinal tract has to be intact and functioning. (4) The oral route should not be compromised. (5) Absence of contra-indicated infections. (6) An oral variant of the antibiotic with good bioavailability has to exist. Conclusions: This systematic stepwise method which combined evidence and expert opinion resulted in a feasible set of 6 major intravenous to oral antibiotic switch therapy criteria operationalized by 16 measurable conditions. This set of early antibiotic iv to oral switch criteria can be used in daily practice in all adult hospital patients. Future use in audits and as rules in computer assisted decision support systems will lead to improvement of antimicrobial steward ship programs.

Keywords: antibiotic resistance, antibiotic stewardship, intravenous to oral, switch therapy

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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Authors: Christos Konstantopoulos, Thomas Ussmueller

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Digital low drop-out regulators, in contrast to analog counterparts, provide an architecture of sub-1 V regulation with low power consumption, high power efficiency, and system integration. Towards an optimized integration in the ultra-low-power system-on-chip Internet of Things architecture that is operated through a radio frequency energy harvesting scheme, the D-LDO regulator should constitute the main regulator that operates the master-clock and rest loads of the SoC. In this context, we present a D-LDO with linear search coarse regulation and asynchronous fine regulation, which incorporates an in-regulator clock generation unit that provides an autonomous, self-start-up, and power-efficient D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the frequency, this work presents a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of coarse regulation frequency. The design is implemented in a 55-nm Global Foundries CMOS process. With the purpose to validate the self-start-up capability of the presented D-LDO in the presence of ultra-low input power, an on-chip test-bench with an RF rectifier is implemented as well, which provides the RF to DC operation and feeds the D-LDO. Power efficiency and load regulation curves of the D-LDO are presented as extracted from the RF to regulated DC operation. The D-LDO regulator presents 83.6 % power efficiency during the RF to DC operation with a 3.65 uA load current and voltage regulator referred input power of -27 dBm. It succeeds 486 nA maximum quiescent current with CL 75 pF, the maximum current efficiency of 99.2%, and 1.16x power efficiency improvement compared to analog voltage regulator counterpart oriented to SoC IoT loads. Complementary, the transient performance of the D-LDO is evaluated under the transient droop test, and the achieved figure-of-merit is compared with state-of-art implementations.

Keywords: D-LDO, Internet of Things, RF energy harvesting, voltage regulators

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Authors: Spyridon Nikolaidis

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A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: Júlio Cesar Lopes de Oliveira, Carlos Henrique Gonçalves Treviso

Abstract:

The shortage of the automotive market in relation to options for sources of high power car audio systems, led to development of this work. Thus, we developed a source with stabilized voltage with 4320 W effective power. Designed to the voltage of 14.4 V and a choice of two currents: 30 A load option in battery banks and 300 A at full load. This source can also be considered as a source of general use dedicated commercial with a simple control circuit in analog form based on discrete components. The assembly of power circuit uses a methodology for higher power than the initially stipulated.

Keywords: DC-DC power converters, converters, power conversion, pulse width modulation converters

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Authors: Tlotlollo Sidwell Hlalele, Shengzhi Du

Abstract:

High voltage transmission is the most pivotal process in the electrical power industry. It requires a robust infrastructure that can last for decades without causing impairment in human life. Due to the so-called global warming, power transmission system has started to experience some challenges which could presumably escalate more in future. These challenges are earthquake resistance, transmission power losses, and high electromagnetic field. In this paper, research efforts aim to address these challenges are discussed. We focus in particular on the research in regenerative electric energy such as: wind, hydropower, biomass and sea-waves based on the energy storage and transmission possibility. We conclude by drawing attention to specific areas that we believe need more research.

Keywords: power transmission, regenerative energy, power quality, energy storage

Procedia PDF Downloads 331