Search results for: Power Amplifier (PA)

Authors: Mantas Sakalas, Paulius Sakalas

Abstract:

This paper presents an analysis and design of a ultrawideband 1.8GHz to 43GHz Low Noise Amplifier (LNA) in 0.1 μm Galium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT) technology. The feedback based bandwidth extension techniques is analyzed and based on the outcome, a two stage LNA is designed. The impedance fine tuning is implemented by using Transmission Line (TL) structures. The measured performance shows a good agreement with simulation results and an outstanding wideband noise matching. The measured small signal gain was 12 dB, whereas a 3 dB gain flatness in range from 1.8 - 43 GHz was reached. The noise figure was below 4 dB almost all over the entire frequency band of 1.8GHz to 43GHz, the output power at 1 dB compression point was 6 dBm and the DC power consumption was 95 mW. To the best knowledge of the authors the designed LNA outperforms the State of the Art (SotA) reported LNA designs in terms of combined parameters of noise figure within the addressed ultra-wide 3 dB bandwidth, linearity and DC power consumption.

Keywords: feedback amplifiers, GaAs pHEMT, monolithic microwave integrated circuit, LNA, noise matching

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Authors: Somya Ranjan Patro, Abhigna Bhatt, Arnab Banerjee

Abstract:

Inertial amplifier has recently gained increasing attention as a new mechanism for vibration control of structures. Currently, theoretical investigations are undertaken by researchers to reveal its fundamentals and to understand its underline principles in altering the structural response of structures against dynamic loadings. This paper investigates experimental and analytical studies on the dynamic characteristics of hybrid beam inertial amplifier (HBIA). The analytical formulation of the HBIA has been derived by implementing the spectral element method and rigid body dynamics. This formulation gives the relation between dynamic force and the response of the structure in the frequency domain. Further, for validation of the proposed HBIA, the experiments have been performed. The experimental setup consists of a 3D printed HBIA of polylactic acid (PLA) material screwed at the base plate of the shaker system. Two numbers of accelerometers are used to study the response, one at the base plate of the shaker second one placed at the top of the inertial amplifier. A force transducer is also placed in between the base plate and the inertial amplifier to calculate the total amount of load transferred from the base plate to the inertial amplifier. The obtained time domain response from the accelerometers have been converted into the frequency domain using the Fast Fourier Transform (FFT) algorithm. The experimental transmittance values are successfully validated with the analytical results, providing us essential confidence in our proposed methodology.

Keywords: inertial amplifier, fast fourier transform, natural frequencies, polylactic acid, transmittance, vibration absorbers

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Authors: Maninder Kaur Gill, Alpana Agarwal

Abstract:

It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device Under Test (DUT), open loop voltage gain, operational amplifier, test circuit

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Authors: Yo-Sheng Lin, Run-Chi Liu, Chien-Chu Ji, Chih-Chung Chen, Chien-Chin Wang

Abstract:

A W-band double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The mixer comprises an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation for conversion gain (CG) enhancement and current injection for power consumption reduction and linearity improvement, a Marchand balun for converting the single LO input signal to differential signal, another Marchand balun for converting the differential RF output signal to single signal, and an output buffer amplifier for loading effect suppression, power consumption reduction and CG enhancement. The mixer consumes low power of 6.9 mW and achieves LO-port input reflection coefficient of -17.8~ -38.7 dB and RF-port input reflection coefficient of -16.8~ -27.9 dB for frequencies of 90~100 GHz. The mixer achieves maximum CG of 3.6 dB at 95 GHz, and CG of 2.1±1.5 dB for frequencies of 91.9~99.4 GHz. That is, the corresponding 3 dB CG bandwidth is 7.5 GHz. In addition, the mixer achieves LO-RF isolation of 36.8 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation and power dissipation results are the best data ever reported for a 94 GHz CMOS/BiCMOS up-conversion mixer.

Keywords: CMOS, W-band, up-conversion mixer, conversion gain, negative resistance compensation, output buffer amplifier

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Authors: M. Aeysha Parvin, J. Asha, J. Jenifer

Abstract:

This letter presents a novel frequency-shift keying(FSK) receiver using PLL-based FSK demodulator, thereby achieving high sensitivity and low power consumption. The proposed receiver comprises a power amplifier, mixer, 3-stage ring oscillator, PLL based demodulator. Moreover, the proposed receiver is fabricated using 0.12µm CMOS process and consumes 0.7Mw. Measurement results demonstrate that the proposed receiver has a sensitivity of -93dbm with 1Mbps data rate in receiving a 2.4 GHz FSK signal.

Keywords: CMOS FSK receiver, phase locked loop (PLL), 3-stage ring oscillator, FSK signal

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Authors: D. J. Dahigaonkar, D. G. Wakde

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The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper.

Keywords: Operational Transconductance Amplifier, Total Harmonic Distortions, low voltage/low power, power dissipation

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Authors: Hyunwon Moon

Abstract:

It is necessary to realize new biomedical wireless communication systems which send the signals collected from various bio sensors located at human body in order to monitor our health. Also, it should seamlessly connect to the existing wireless communication systems. A 5.8 GHz ISM band low power RF front-end receiver for a biomedical wireless communication system is implemented using a 0.5 µm SiGe BiCMOS process. To achieve low power RF front-end, the current optimization technique for selecting device size is utilized. The implemented low noise amplifier (LNA) shows a power gain of 9.8 dB, a noise figure (NF) of below 1.75 dB, and an IIP3 of higher than 7.5 dBm while current consumption is only 6 mA at supply voltage of 2.5 V. Also, the performance of a down-conversion mixer is measured as a conversion gain of 11 dB and SSB NF of 10 dB.

Keywords: biomedical, LNA, mixer, receiver, RF front-end, SiGe

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Authors: Kadam Bhambri, Neena Gupta

Abstract:

All optical wavelength conversion is essential in present day optical networks for transparent interoperability, contention resolution, and wavelength routing. The incorporation of all optical wavelength convertors leads to better utilization of the network resources and hence improves the efficiency of optical networks. Wavelength convertors that can work with Dispersion Managed (DM) solitons are attractive due to their superior transmission capabilities. In this paper, wavelength conversion for dispersion managed soliton signals was demonstrated at 100 Gbps through semiconductor optical amplifier and an optical filter. The wavelength conversion was achieved for a 1550 nm input signal to1555nm output signal. The output signal was measured in terms of BER, Q factor and system margin.    

Keywords: all optical wavelength conversion, dispersion managed solitons, semiconductor optical amplifier, cross gain modultation

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Authors: Amir Mahdavi

Abstract:

In this paper a highly linear CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve second and third-order intercept points (IIP3). The linearity is cured by repealing the common-mode section of all intermodulation components from the cascade topology current with optimization of biasing current use symmetrical and asymmetrical circuits for biasing. Simulation results show that maximum gain and noise figure are 6.9dB and 3.03-4.1dB over a 3.1–10.6 GHz, respectively. Power consumption of the LNA core and IIP3 are 2.64 mW and +4.9dBm respectively. The wideband input impedance matching of LNA is obtained by employing a degenerating inductor (|S11|<-9.1 dB). The circuit proposed UWB LNA is implemented using 0.18 μm based CMOS technology.

Keywords: highly linear LNA, low-power LNA, optimal bias techniques

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Authors: Kittipong Tripetch

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This paper proposes studies of input impedance of two types of the CMOS active inductor. It derives two input impedance formulas. The first formula is the input impedance of a grounded active inductor. The second formula is an input impedance of floating active inductor. After that, these formulas can be used to simulate magnitude and phase response of input impedance as a function of current consumption with MATLAB. Common mode rejection ratio (CMRR) of a fully differential bandpass amplifier is derived based on superposition principle. CMRR as a function of input frequency is plotted as a function of current consumption

Keywords: grounded active inductor, floating active inductor, fully differential bandpass amplifier

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Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on instrumentation amplifier and it is useful for reducing offset in Wheatstone bridge. The obtained gain is 645 with 1 μv/°c equivalent drift and 1.58 mw power consumption. A Schmitt trigger and multiplexer circuit control output node. A high speed counter is designed in this work. The proposed circuit is designed and simulated in 0.18 μm CMOS technology with 1.8 v power supply.

Keywords: piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: Shreyas Srinivas Rangan, Jurgis Porins

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The internet traffic has increased exponentially due to the high demand for data rates by the users, and the constantly increasing metro networks and access networks are focused on improving the maximum transmit distance of the long-reach optical networks. One of the common methods to improve the maximum transmit distance of the long-reach optical networks at the component level is to use broadband optical amplifiers. The Erbium Doped Fiber Amplifier (EDFA) provides high amplification with low noise figure but due to the characteristics of EDFA, its operation is limited to C-band and L-band. In contrast, the Raman amplifier exhibits a wide amplification spectrum, and negative noise figure values can be achieved. To obtain such results, high powered pumping sources are required. Operating Raman amplifiers with such high-powered optical sources may cause fire hazards and it may damage the optical system. In this paper, we implement a hybrid optical amplifier configuration. EDFA and Raman amplifiers are used in this hybrid setup to combine the advantages of both EDFA and Raman amplifiers to improve the reach of the system. Using this setup, we analyze the maximum transmit distance of the network by obtaining a correlation diagram between the length of the single-mode fiber (SMF) and the Bit Error Rate (BER). This hybrid amplifier configuration is implemented in a Wavelength Division Multiplexing (WDM) system with a BER of 10⁻⁹ by using NRZ modulation format, and the gain uniformity noise ratio (signal-to-noise ratio (SNR)), the efficiency of the pumping source, and the optical signal gain efficiency of the amplifier are studied experimentally in a mathematical modelling environment. Numerical simulations were implemented in RSoft OptSim simulation software based on the nonlinear Schrödinger equation using the Split-Step method, the Fourier transform, and the Monte Carlo method for estimating BER.

Keywords: Raman amplifier, erbium doped fibre amplifier, bit error rate, hybrid optical amplifiers

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Authors: Yo-Sheng Lin, Jen-How Lee, Chien-Chin Wang

Abstract:

A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA), and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential (STD) converter, an LO Marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4 GHz to 65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are -33.1 dBm and -23.3 dBm, respectively, at 60 GHz. These results demonstrate the proposed receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications.

Keywords: CMOS, 60 GHz, direct-conversion transceiver, LNA, down-conversion mixer, marchand balun, current-reused

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Authors: Farzan Farhangian, Behnam Shakibafar, Bobda Cedric, Rene Jr. Landry

Abstract:

Among the air navigation technologies, many of them are capable of increasing aviation sustainability as well as accuracy improvement in Alternative Positioning, Navigation, and Timing (APNT), especially avionics Distance Measuring Equipment (DME), Very high-frequency Omni-directional Range (VOR), etc. The integration of these air navigation solutions could make a robust and efficient accuracy in air mobility, air traffic management and autonomous operations. Designing a proper RF front-end, power amplifier and software-defined transponder could pave the way for reaching an optimized avionics navigation solution. In this article, the possibility of reaching an optimum front-end to be used with single low-cost Software-Defined Radio (SDR) has been investigated in order to reach a software-defined DME architecture. Our software-defined approach uses the firmware possibilities to design a real-time software architecture compatible with a Multi Input Multi Output (MIMO) BladeRF to estimate an accurate time delay between a Transmission (Tx) and the reception (Rx) channels using the synchronous scheduled communication. We could design a novel power amplifier for the transmission channel of the DME to pass the minimum transmission power. This article also investigates designing proper pair pulses based on the DO-178B avionics standard. Various guidelines have been tested, and the possibility of passing the certification process for each standard term has been analyzed. Finally, the performance of the DME was tested in the laboratory environment using an IFR6000, which showed that the proposed architecture reached an accuracy of less than 0.23 Nautical mile (Nmi) with 98% probability.

Keywords: avionics, DME, software defined radio, navigation

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Authors: Ilef Ketata, Mohamed Khalil Baazaoui, Robert Fromm, Ahmad Fakhfakh, Faouzi Derbel

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The integration of wireless communication, e. g. in real-or quasi-real-time applications, is related to many challenges such as energy consumption, communication range, latency, quality of service, and reliability. To minimize the latency without increasing energy consumption, wake-up receiver (WuRx) nodes have been introduced in recent works. Low-noise amplifiers (LNAs) are introduced to improve the WuRx sensitivity but increase the supply current severely. Different WuRx approaches exist with always-on, power-gated, or duty-cycled receiver designs. This paper presents a comparative study for improving communication range and decreasing the energy consumption of wireless sensor nodes.

Keywords: wireless sensor network, wake-up receiver, duty-cycled, low-noise amplifier, envelope detector, range study

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Authors: Jangje Park, So Young Kim

Abstract:

The market demand for audio quality in mobile devices continues to increase, and audible buzz noise generated in time division communication is a chronic problem that goes against the market demand. In the case of time division type communication, the RF Power Amplifier (RF PA) is driven at the audio frequency cycle, and it makes various influences on the audio signal. In this paper, we measured the ground bounce noise generated by the peak current flowing through the ground network in the RF PA with the audio frequency; it was confirmed that the noise is the cause of the audible buzz noise during a call. In addition, a grounding method of the microphone device that can improve the buzzing noise was proposed. Considering that the level of the audio signal generated by the microphone device is -38dBV based on 94dB Sound Pressure Level (SPL), even ground bounce noise of several hundred uV will fall within the range of audible noise if it is induced by the audio amplifier. Through the grounding method of the microphone device proposed in this paper, it was confirmed that the audible buzz noise power density at the RF PA driving frequency was improved by more than 5dB under the conditions of the Printed Circuit Board (PCB) used in the experiment. A fundamental improvement method was presented regarding the buzzing noise during a mobile phone call.

Keywords: audio frequency, buzz noise, ground bounce, microphone grounding

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Authors: John Lachapelle

Abstract:

Introduction: Neural stimulation is increasingly targeted toward treatment of back pain, PTSD, Parkinson’s disease, and for sensory perception. Sensory recording during stimulation is important in order to examine neural response to stimulation. Most neural amplifiers (headstages) focus on noise efficiency factor (NEF). Conversely, neural headstages need to handle artifacts from several sources including power lines, movement (EMG), and neural stimulation itself. In this work a layered approach to artifact rejection is used to reduce corruption of the neural ENG signal by 60dBv, resulting in recovery of sensory signals in rats and primates that would previously not be possible. Methods: The approach combines analog techniques to reduce and handle unwanted signal amplitudes. The methods include optimized (1) sensory electrode placement, (2) amplifier configuration, and (3) artifact blanking when necessary. The techniques together are like concentric moats protecting a castle; only the wanted neural signal can penetrate. There are two conditions in which the headstage operates: unwanted artifact < 50mV, linear operation, and artifact > 50mV, fast-settle gain reduction signal limiting (covered in more detail in a separate paper). Unwanted Signals at the headstage input: Consider: (a) EMG signals are by nature < 10mV. (b) 60 Hz power line signals may be > 50mV with poor electrode cable conditions; with careful routing much of the signal is common to both reference and active electrode and rejected in the differential amplifier with <50mV remaining. (c) An unwanted (to the neural recorder) stimulation signal is attenuated from stimulation to sensory electrode. The voltage seen at the sensory electrode can be modeled Φ_m=I_o/4πσr. For a 1 mA stimulation signal, with 1 cm spacing between electrodes, the signal is <20mV at the headstage. Headstage ASIC design: The front end ASIC design is designed to produce < 1% THD at 50mV input; 50 times higher than typical headstage ASICs, with no increase in noise floor. This requires careful balance of amplifier stages in the headstage ASIC, as well as consideration of the electrodes effect on noise. The ASIC is designed to allow extremely small signal extraction on low impedance (< 10kohm) electrodes with configuration of the headstage ASIC noise floor to < 700nV/rt-Hz. Smaller high impedance electrodes (> 100kohm) are typically located closer to neural sources and transduce higher amplitude signals (> 10uV); the ASIC low-power mode conserves power with 2uV/rt-Hz noise. Findings: The enhanced neural processing ASIC has been compared with a commercial neural recording amplifier IC. Chronically implanted primates at MGH demonstrated the presence of commercial neural amplifier saturation as a result of large environmental artifacts. The enhanced artifact suppression headstage ASIC, in the same setup, was able to recover and process the wanted neural signal separately from the suppressed unwanted artifacts. Separately, the enhanced artifact suppression headstage ASIC was able to separate sensory neural signals from unwanted artifacts in mouse-implanted peripheral intrafascicular electrodes. Conclusion: Optimizing headstage ASICs allow observation of neural signals in the presence of large artifacts that will be present in real-life implanted applications, and are targeted toward human implantation in the DARPA HAPTIX program.

Keywords: ASIC, biosensors, biomedical signal processing, biomedical sensors

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: boost converter, current sensing, power-on protection, step-up converter, soft-start

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Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: amplifier class D, field-programmable gate array (FPGA), protective relay, tester

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The coaxial transformer-coupled push-pull circuitry has been used widely in HF and VHF amplifiers for many decades without significant changes in the topology of the transformers. Basic changes over the years concerned the construction and turns ratio of the transformers as has been imposed upon the newer technologies active devices demands. The balun transmission line transformers applied in push-pull amplifiers enable input/output impedance transformation, but are mainly used to convert the balanced output into unbalanced and the input unbalanced into balanced. A simple and affordable alternative solution over the traditional coaxial transformer is the coreless planar balun. A key advantage over the traditional approach lies in the high specifications repeatability; simplifying the amplifier construction requirements as the planar balun constitutes an integrated part of the PCB copper layout. This paper presents the performance analysis of a planar LDMOS MRFE6VP5600 Push-Pull amplifier that enables robust operation in Band III, DVB-T, DVB-T2 standards but functions equally well in Band II, for DRM+ new generation transmitters.

Keywords: amplifier, balun, complex impedance, LDMOS, planar-transformers

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Authors: Reyhaneh Hashemi, Shahrooz Saviz

Abstract:

In his study, we have survey the theory of gyrotron amplifier in a vane-loaded waveguide with inner dielectric material. Dispersion relation for electromagnetic waves emitted by a cylindrical waveguide that provided with wedge-shaped metal vanes projecting radially inward from the wall of the guide and exited in the transverse-electric mode was analysed. From numerical analysis of this dispersion relation, it is shown that the stability behavior of the fast-wave mode is dependent of the dielectric constant. With a small axial momentum spreed, a super bandwidth is shown to be attainable by a mixed mode operation. Also, with the utilization from the numeric analysis of relation dispersion. We show that in the –speed mode, the constant is independent de-electric. With the ratio of dispersion of smell, high –bandwith was obtained for the combined mode. And at the end, we were comparing the result of our work (vane-loaded) by the waveguide with a smooth wall.

Keywords: gyrotron amplifier, waveguide, vane-loaded waveguide, dielectric material, dispersion relation, cylindrical waveguide, fast-wave mode, mixed mode operation

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Authors: Selcuk Comlekci, Mohammed Aboajmaa

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Orthogonal frequency division multiplexing (OFDM) is promising technique for the modern wireless communications systems due to its robustness against multipath environment. The high peak to average power ratio (PAPR) of the transmitted signal is one of the major drawbacks of OFDM system, PAPR degrade the performance of bit error rate (BER) and effect on the linear characteristics of high power amplifier (HPA). In this paper, we proposed DHT-Clipping reduction technique to reduce the high PAPR by the combination between discrete Hartley transform (DHT) and Clipping techniques. From the simulation results, we notified that DHT-Clipping technique offers better PAPR reduction than DHT and Clipping, as well as DHT-Clipping introduce improved BER performance better than clipping.

Keywords: ISI, cyclic prefix, BER, PAPR, HPA, DHT, subcarrier

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Authors: Daniel P. Clayton, Edward A. Ball

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This paper describes an investigation into the isolation characteristics and bandwidth performance of RF combiners that are used as part of Chireix PA architectures, designed for use in the X-Band range of frequencies. Combiner designs investigated are the typical Chireix and Wilkinson configurations which also include simulation of the Wilkinson using manufacturer’s data for the isolation resistor. Another simulation was the less common approach of using a Branchline coupler to form the combiner, as well as simulation results from adding an additional stage. This paper presents the findings of this investigation and compares the bandwidth performance and isolation characteristics to determine suitability.

Keywords: bandwidth, Chireix, couplers, outphasing, power amplifiers, Wilkinson, X-Band

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

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This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, voltage transition, node stabilization, biasing circuits

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, multi-inputs, voltage transition, node stabilization, biasing circuits

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Authors: Sayyed Benyamin Alavi, Giovanni Cerri, Leila Chennaoui, Ambra Giovannelli, Stefano Mazzoni

Abstract:

Primary energy consumption and emissions of pollutants (including CO2) sustainability call to search methodologies to lower power absorption for unit of a given product. Cool production plants based on vapour compression are widely used for many applications: air conditioning, food conservation, domestic refrigerators and freezers, special industrial processes, etc. In the field of cool production, the amount of Yearly Consumed Primary Energy is enormous, thus, saving some percentage of it, leads to big worldwide impact in the energy consumption and related energy sustainability. Among various techniques to reduce power required by a Vapour Compression Cool Production Plant (VCCPP), the technique based on Power Regeneration by means of Internal Direct Cycle (IDC) will be considered in this paper. Power produced by IDC reduces power need for unit of produced Cool Power by the VCCPP. The paper contains basic concepts that lead to develop IDCs and the proposed options to use the IDC Power. Among various selections for using turbo machines, Best Economically Available Technologies (BEATs) have been explored. Based on vehicle engine turbochargers, they have been taken into consideration for this application. According to BEAT Database and similarity rules, the best turbo machine selection leads to the minimum nominal power required by VCCPP Main Compressor. Results obtained installing the prototype in “ad hoc” designed test bench will be discussed and compared with the expected performance. Forecasts for the upgrading VCCPP, various applications will be given and discussed. 4-6% saving is expected for air conditioning cooling plants and 15-22% is expected for cryogenic plants.

Keywords: Refrigeration Plant, Vapour Pressure Amplifier, Compressor, Expander, Turbine, Turbomachinery Selection, Power Saving

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Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

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This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. A single ended 38.5 kS/s 10-bit programmable reference SAR ADC was proposed and implemented in a 0.35 µm CMOS technology and consumed less than 7.5 mW power with a 3 V supply.

Keywords: successive approximation register analog-to-digital converter, SAR ADC, resistive DAC, programmable reference

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Authors: Phanumas Khumsat, Chalermchai Janmane

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Low-voltage instrumentation amplifier has been proposed for 3-lead electrocardiogram measurement system. The circuit’s interference rejection technique is based upon common-mode feed-forwarding where common-mode currents have cancelled each other at the output nodes. The common-mode current for cancellation is generated by means of common-mode sensing and emitter or source followers with resistors employing only one transistor. Simultaneously this particular transistor also provides common-mode feedback to the patient’s right/left leg to further reduce interference entering the amplifier. The proposed designs have been verified with simulations in 0.18-µm CMOS process operating under 1.0-V supply with CMRR greater than 80dB. Moreover ECG signals have experimentally recorded with the proposed instrumentation amplifiers implemented from discrete BJT (BC547, BC558) and MOSFET (ALD1106, ALD1107) transistors working with 1.5-V supply.

Keywords: electrocardiogram, common-mode feedback, common-mode feedforward, communication engineering

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Authors: Pinghe Wang

Abstract:

In this paper, we demonstrate a tunable long-cavity passive mode-locked fiber laser. The mode locker is a nonlinear amplifying loop mirror (NALM). The cavity frequency of the laser is 465 kHz because that 404m SMF is inserted in the cavity. A tunable bandpass filter with ~1nm 3dB bandwidth is inserted into the cavity to realize tunable mode locking. The passive mode-locked laser at a fixed wavelength is investigated in detail. The experimental results indicate that the laser operates in dissipative soliton resonance (DSR) region. When the pump power is 400mW, the laser generates the rectangular pulses with 10.58 ns pulse duration, 70.28nJ single-pulse energy. When the pump power is 400mW, the laser keeps stable mode locking status in the range from 1523.4nm to 1575nm. During the whole tuning range, the SNR, the pulse duration, the output power and single pulse energy have a little fluctuation because that the gain of the EDF changes with the wavelength.

Keywords: fiber laser, dissipative soliton resonance, mode locking, tunable

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Authors: Nawang Chhunid, Gagnesh Kumar

Abstract:

On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM Cell, Read Access Time, Retention Time, Average Power dissipation

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