Search results for: CMOS FSK receiver

Authors: M. Aeysha Parvin, J. Asha, J. Jenifer

Abstract:

This letter presents a novel frequency-shift keying(FSK) receiver using PLL-based FSK demodulator, thereby achieving high sensitivity and low power consumption. The proposed receiver comprises a power amplifier, mixer, 3-stage ring oscillator, PLL based demodulator. Moreover, the proposed receiver is fabricated using 0.12µm CMOS process and consumes 0.7Mw. Measurement results demonstrate that the proposed receiver has a sensitivity of -93dbm with 1Mbps data rate in receiving a 2.4 GHz FSK signal.

Keywords: CMOS FSK receiver, phase locked loop (PLL), 3-stage ring oscillator, FSK signal

Procedia PDF Downloads 459

Authors: Yo-Sheng Lin, Jen-How Lee, Chien-Chin Wang

Abstract:

A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA), and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential (STD) converter, an LO Marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4 GHz to 65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are -33.1 dBm and -23.3 dBm, respectively, at 60 GHz. These results demonstrate the proposed receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications.

Keywords: CMOS, 60 GHz, direct-conversion transceiver, LNA, down-conversion mixer, marchand balun, current-reused

Procedia PDF Downloads 419

Authors: Ki-Jin Kim, Suk-Hui LEE, Sanghoon Park, K. H. Ahn

Abstract:

A high power, low loss asymmetric single pole double through(SPDT) antenna switch for LTE-A Front-End Module(FEM) is presented in this paper by using CMOS technology. For the usage of LTE-A applications, low loss and high linearity are the key features which are very challenging works under CMOS process. To enhance insertion loss(IL) and power handling capability, this paper adopts asymmetric Transmitter (TX) and RX (Receiver) structure, floating body technique, multi-stacked structure, and feed forward capacitor technique. The designed SPDT switch shows TX IL 0.34 dB, RX IL 0.73 dB, P1dB 38.9 dBm at 0.9 GHz and TX IL 0.37 dB, RX IL 0.95 dB, P1dB 39.1 dBm at 2.5 GHz respectively.

Keywords: CMOS switch, SPDT switch, high power CMOS switch, LTE-A FEM

Procedia PDF Downloads 334

Authors: A. Anitha, M. Aishwariya

Abstract:

The realization of truly ubiquitous wireless sensor networks (WSN) demands Ultra-low power wireless communication capability. Because the radio transceiver in a wireless sensor node consumes more power when compared to the computation part it is necessary to reduce the power consumption. Hence, a low power transceiver is designed and implemented in a 120 nm CMOS technology for wireless sensor nodes. The power consumption of the transceiver is reduced still by maintaining the sensitivity. The transceiver designed combines the blocks including differential oscillator, mixer, envelope detector, power amplifiers, and LNA. RF signal modulation and demodulation is carried by On-Off keying method at 2.4 GHz which is said as ISM band. The transmitter demonstrates an output power of 2.075 mW while consuming a supply voltage of range 1.2 V-5.0 V. Here the comparison of LNA and power amplifier is done to obtain an amplifier which produces a high gain of 1.608 dB at receiver which is suitable to produce a desired sensitivity. The multistage RF amplifier is used to improve the gain at the receiver side. The power dissipation of the circuit is in the range of 0.183-0.323 mW. The receiver achieves a sensitivity of about -95 dBm with data rate of 1 Mbps.

Keywords: CMOS, envelope detector, ISM band, LNA, low power electronics, PA, wireless transceiver

Procedia PDF Downloads 473

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter

Procedia PDF Downloads 423

Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA

Procedia PDF Downloads 281

Authors: Hooman Kaabi, Raziyeh Karkoub

Abstract:

This work proposes a structure of AMOS-varactors. A 5GHz LC-VCO designed in TSMC 0.18μm CMOS to improve phase noise and tuning range performance. The tuning range is from 5.05GHZ to 5.88GHz.The phase noise is -154.9dBc/Hz at 1MHz offset from the carrier. It meets the requirements for IEEE 802.11a WLAN standard.

Keywords: CMOS LC VCO, spiral inductor, varactor, phase noise, tuning range

Procedia PDF Downloads 499

Authors: Jin-Sup Kim, Se-Hwan Choi, Jae-Young Lee

Abstract:

A 8-bit CMOS capacitor array is designed for using in electrically steerable passive array radiator (ESPAR). The proposed capacitor array shows the fast response time in rising and falling characteristics. Compared to other works in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, it shows a comparable tuning range and switching time with low power consumption. Using the 0.18um CMOS, the capacitor array features a tuning range of 1.5 to 12.9 pF at 2.4GHz. Including the 2X4 decoder for control interface, the Chip size is 350um X 145um. Current consumption is about 80 nA at 1.8 V operation.

Keywords: CMOS capacitor array, ESPAR, SOI, SOS, switching time

Procedia PDF Downloads 559

Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

Procedia PDF Downloads 311

Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, phase shifter, backhaul, 802.11ac

Procedia PDF Downloads 350

Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS process sensor, PVT sensor, threshold extractor circuit, Vth extractor circuit

Procedia PDF Downloads 142

Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter

Procedia PDF Downloads 262

Authors: Hamd Ahmed

Abstract:

During the Persian Gulf War in 1991s, The confederation forces were surprised when they were being shot at by friendly forces in Iraqi desert. As obvious was the fact that they were mislead due to the lack of proper guidance and technology resulting in unnecessary loss of life and bloodshed. This unforeseen incident along with many others led the US department of defense to open the doors of GPS. In the very beginning, this technology was for military use, but now it is being widely used and increasingly popular among the public due to its high accuracy and immeasurable significance. The GPS system simply consists of three segments, the space segment (the satellite), the control segment (ground control) and the user segment (receiver). This project work is about designing a 1.57GHZ mixer for triple conversion GPS receiver .The GPS Front-End receiver based on super heterodyne receiver which improves selectivity and image frequency. However the main principle of the super heterodyne receiver depends on the mixer. Many different types of mixers (single balanced mixer, Single Ended mixer, Double balanced mixer) can be used with GPS receiver, it depends on the required specifications. This research project will provide an overview of the GPS system and details about the basic architecture of the GPS receiver. The basic emphasis of this report in on investigating general concept of the mixer circuit some terms related to the mixer along with their definitions and present the types of mixer, then gives some advantages of using singly balanced mixer and its application. The focus of this report is on how to design mixer for GPS receiver and discussing the simulation results.

Keywords: GPS , RF filter, heterodyne, mixer

Procedia PDF Downloads 273

Authors: D. J. Dahigaonkar, D. G. Wakde

Abstract:

The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper.

Keywords: Operational Transconductance Amplifier, Total Harmonic Distortions, low voltage/low power, power dissipation

Procedia PDF Downloads 372

Authors: Hafez Fouad

Abstract:

Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %.

Keywords: energy harvesting, embedded system, IoT telemedicine system, threshold voltage minimization, differential drive cmos rectifier, full-wave fully gate cross-coupled rectifiers CMOS rectifier

Procedia PDF Downloads 114

Authors: Mohammad Arif Sobhan Bhuiyan, Mamun Bin Ibne Reaz

Abstract:

The rapid advancement of CMOS technology, in the recent years, has led the scientists to fabricate wireless transceivers fully on-chip which results in smaller size and lower cost wireless communication devices with acceptable performance characteristics. Moreover, the performance of the wireless transceivers rigorously depends on the performance of its first block T/R switch. This article proposes a design of a high performance T/R switch for 2.4 GHz RF wireless transceivers in 0.13 µm CMOS technology. The switch exhibits 1- dB insertion loss, 37.2-dB isolation in transmit mode and 1.4-dB insertion loss, 25.6-dB isolation in receive mode. The switch has a power handling capacity (P1dB) of 30.9-dBm. Besides, by avoiding bulky inductors and capacitors, the size of the switch is drastically reduced and it occupies only (0.00296) mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit will trim down the cost of fabrication as well as the whole transceiver.

Keywords: CMOS, ISM band, SPDT, t/r switch, transceiver

Procedia PDF Downloads 411

Authors: Mustafa El-Halabi

Abstract:

A general model of wiretap channel with states is considered, where the legitimate receiver and the wiretapper’s observations depend on three states S1, S2 and S3. State S1 is non-causally known to the encoder, S2 is known to the receiver, and S3 remains unknown. A secure coding scheme, based using structured-binning, is proposed, and it is shown to achieve the secrecy capacity when the signal at legitimate receiver is a deterministic function of the input.

Keywords: physical layer security, interference, side information, secrecy capacity

Procedia PDF Downloads 355

Authors: Sreenesh Shashidharan, Umesh Gaikwad

Abstract:

QI or 'Chee' which is an interface standard for inductive electrical power transfer over distances of up to 4 cm (1.6 inches). The Qi system comprises a power transmission pad and a compatible receiver in a portable device which is placed on top of the power transmission pad, which charges using the principle of electromagnetic induction. An alternating current is passed through the transmitter coil, generating a magnetic field. This, in turn, induces a voltage in the receiver coil; this can be used to power a mobile device or charge a battery. The efficiency of the power transfer depends on the coupling (k) between the inductors and their quality (Q) The coupling is determined by the distance between the inductors (z) and the relative size (D2 /D). The coupling is further determined by the shape of the coils and the angle between them. If the receiver coil is at a certain distance to the transmitter coil, only a fraction of the magnetic flux, which is generated by the transmitter coil, penetrates the receiver coil and contributes to the power transmission. The more flux reaches the receiver, the better the coils are coupled.

Keywords: inductive electric power, electromagnetic induction, magnetic flux, coupling

Procedia PDF Downloads 697

Authors: Madina Hamiane

Abstract:

Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

Procedia PDF Downloads 423

Authors: Xiaoli Zhang, Xiongfei Li, Yuncong Feng

Abstract:

ROC curves, as a widely used evaluating tool in machine learning field, are the tradeoff of true positive rate and negative rate. However, they are blamed for ignoring some vital information in the evaluation process, such as the amount of information about the target that each instance carries, predicted score given by each classification model to each instance. Hence, in this paper, a new classification performance method is proposed by extending the Receiver Operator Characteristic (ROC) curves to 3D space, which is denoted as 3D ROC Histogram. In the histogram, the

Keywords: classification, performance evaluation, receiver operating characteristic histogram, hardness prediction

Procedia PDF Downloads 284

Authors: Hung-Yuan Chang, Wen-Lung Chiang, Kuo-Liang Wu, Chen-Tsung Lin

Abstract:

National Space Organization (NSPO) has completed in 2014 the development of a space-borne GPS receiver, including design, manufacture, comprehensive functional test, environmental qualification test and so on. The main performance of this receiver include 8-meter positioning accuracy, 0.05 m/sec speed-accuracy, the longest 90 seconds of cold start time, and up to 15g high dynamic scenario. The receiver will be integrated in the autonomous FORMOSAT-7 NSPO-Built satellite scheduled to be launched in 2019 to execute pre-defined scientific missions. The flight model of this receiver manufactured in early 2015 will pass comprehensive functional tests and environmental acceptance tests, etc., which are expected to be completed by the end of 2015. The space-borne GPS receiver is a pure software design in which all GPS baseband signal processing are executed by a digital signal processor (DSP), currently only 50% of its throughput being used. In response to the booming global navigation satellite systems, NSPO will gradually expand this receiver to become a multi-mode, multi-band, high-precision navigation receiver, and even a science payload, such as the reflectometry receiver of a global navigation satellite system. The fundamental purpose of this extension study is to port some software algorithms such as signal acquisition and correlation, reused code and large amount of computation load to the FPGA whose processor is responsible for operational control, navigation solution, and orbit propagation and so on. Due to the development and evolution of the FPGA is pretty fast, the new system architecture upgraded via an FPGA should be able to achieve the goal of being a multi-mode, multi-band high-precision navigation receiver, or scientific receiver. Finally, the results of tests show that the new system architecture not only retains the original overall performance, but also sets aside more resources available for future expansion possibility. This paper will explain the detailed DSP/FPGA architecture, development, test results, and the goals of next development stage of this receiver.

Keywords: space-borne, GPS receiver, DSP, FPGA, multi-mode multi-band

Procedia PDF Downloads 339

Authors: Milad Kaboli

Abstract:

A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

Procedia PDF Downloads 439

Authors: Mohammad Arif Sobhan Bhuiyan, Zainal Abidin Nordin, Mamun Bin Ibne Reaz

Abstract:

A compact and power efficient high performance Voltage Controlled Oscillator (VCO) is a must in analog and digital circuits especially in the communication system, but the best trade-off among the performance parameters is a challenge for researchers. In this paper, a design of a compact 3-stage differential voltage controlled ring oscillator (VCRO) with low phase noise, low power and higher tuning bandwidth is proposed in 0.18 µm CMOS technology. The VCRO is designed with symmetric load and positive feedback techniques to achieve higher gain and minimum delay. The proposed VCRO can operate at tuning range of 3.9-5.0 GHz at 1.6 V supply voltage. The circuit consumes only 1.0757 mW of power and produces -129 dbc/Hz. The total active area of the proposed VCRO is only 11.74 x 37.73 µm2. Such a VCO can be the best choice for compact and low-power RF applications.

Keywords: CMOS, VCO, VCRO, oscillator

Procedia PDF Downloads 435

Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

Procedia PDF Downloads 398

Authors: Jin Sup Kim, Min Seo

Abstract:

An improved cross-shaped hall plate with high sensitivity is described in this paper. Among different geometries that have been simulated and measured using Helmholtz coil. The paper describes the physical hall plate design and implementation in a 0.18-µm CMOS technology. In this paper, the biasing is a constant voltage mode. In the voltage mode, magnetic field is converted into an output voltage. The output voltage is typically in the order of micro- to millivolt and therefore, it must be amplified before being transmitted to the outside world. The study, design and performance optimization of hall plate has been carried out with the COMSOL Multiphysics. It is used to estimate the voltage distribution in the hall plate with and without magnetic field and to optimize the geometry. The simulation uses the nominal bias current of 1mA. The applied magnetic field is in the range from 0 mT to 20 mT. Measured results of the one structure over the 10 available samples show for the best sensitivity of 2.5 %/T at 20mT.

Keywords: cross-shaped hall plate, sensitivity, CMOS technology, Helmholtz coil

Procedia PDF Downloads 164

Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. A single ended 38.5 kS/s 10-bit programmable reference SAR ADC was proposed and implemented in a 0.35 µm CMOS technology and consumed less than 7.5 mW power with a 3 V supply.

Keywords: successive approximation register analog-to-digital converter, SAR ADC, resistive DAC, programmable reference

Procedia PDF Downloads 479

Authors: O. Afshar

Abstract:

A solar receiver is designed for operation under extremely uneven heat flux distribution, cyclic weather, and cloud transient cycle conditions, which can include large thermal stress and even receiver failure. In this study, the effect of different oil velocity on convection coefficient factor and impact of wind velocity on local Nusselt number by Finite Volume Method will be analyzed. This study is organized to give an overview of the numerical modeling using a MATLAB software, as an accurate, time efficient and economical way of analyzing the heat transfer trends over stationary receiver tube for different Reynolds number. The results reveal when oil velocity is below 0.33m/s, the value of convection coefficient is negligible at low temperature. The numerical graphs indicate that when oil velocity increases up to 1.2 m/s, heat convection coefficient increases significantly. In fact, a reduction in oil velocity causes a reduction in heat conduction through the glass envelope. In addition, the different local Nusselt number is reduced when the wind blows toward the concave side of the collector and it has a significant effect on heat losses reduction through the glass envelope.

Keywords: receiver tube, heat convection, heat conduction, Nusselt number

Procedia PDF Downloads 319

Authors: Ilef Ketata, Mohamed Khalil Baazaoui, Robert Fromm, Ahmad Fakhfakh, Faouzi Derbel

Abstract:

The integration of wireless communication, e. g. in real-or quasi-real-time applications, is related to many challenges such as energy consumption, communication range, latency, quality of service, and reliability. To minimize the latency without increasing energy consumption, wake-up receiver (WuRx) nodes have been introduced in recent works. Low-noise amplifiers (LNAs) are introduced to improve the WuRx sensitivity but increase the supply current severely. Different WuRx approaches exist with always-on, power-gated, or duty-cycled receiver designs. This paper presents a comparative study for improving communication range and decreasing the energy consumption of wireless sensor nodes.

Keywords: wireless sensor network, wake-up receiver, duty-cycled, low-noise amplifier, envelope detector, range study

Procedia PDF Downloads 75

Authors: Ow Tze Weng, Suhaila Isaak, Yusmeeraz Yusof

Abstract:

The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability, especially in the most common electrocardiogram (ECG) monitoring system. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip (SoC) is increasing in exponential way, the front end ECG sensors are still suffering from flicker noise for low frequency cardiac signal acquisition, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a high performance CMOS amplifier for ECG sensors that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13 µm CMOS technology from Silterra, the simulation results show that this front end circuit can achieve a very low input referred noise of 1 pV/√Hz and high common mode rejection ratio (CMRR) of 174.05 dB. It also gives voltage gain of 75.45 dB with good power supply rejection ratio (PSSR) of 92.12 dB. The total power consumption is only 3 µW and thus suitable to be implemented with further signal processing and classification back end for low power biomedical SoC.

Keywords: CMOS, ECG, amplifier, low power

Procedia PDF Downloads 209

Authors: Sethu Lekshmi, Shahanas, Prettha P.

Abstract:

All existing protocols in wireless networks are mainly based on Carrier Sense Multiple Access with Collision avoidance. By applying collision detection in wireless networks, the time spent on collision can be reduced and thus improves system throughput. However in a real WLAN scenario due to the use of nonlinear modulation techniques only receiver can decided whether a packet loss take place, even there are multiple transmissions. In this proposed method, the receiver or Access Point detects the collision when multiple data packets are transmitted from different wireless stations. Whenever the receiver detects a collision, it transmits a jamming signal to all the transmitting stations so that they can immediately stop their on-going transmissions. We also provide preferential access to all collided packet to reduce unfairness and to increase system throughput by reducing contention. However, this preferential access will not block the channel for the long time. Here, an in-band transmission is considered in which both the data frames and control frames are transmitted in the same channel. We also provide a simple mathematical model for the proposed protocol and give the simulation result of WLAN scenario under various capture thresholds.

Keywords: 802.11, WLAN, capture effect, collision detection, collision resolution, receiver initiated

Procedia PDF Downloads 324