Search results for: CMOS capacitor array

Authors: Milad Kaboli

Abstract:

A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

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Authors: Tran Trong Thang, Nguyen Phan Kien, Trinh Quang Duc

Abstract:

The phased-array ultrasound transducer types are utilities for medical ultrasonography as well as optical imaging. However, their discontinuity characteristic limits the applications due to the artifacts contaminated into the reconstructed images. Because of the effects of the ultrasound pressure field pattern to the echo ultrasonic waves as well as the optical modulated signal, the side lobes of the focused ultrasound beam induced by discontinuity of the phased-array ultrasound transducer might the reason of the artifacts. In this paper, a simple method in approach of numerical simulation was used to investigate the limitation of discontinuity of the elements in phased-array ultrasound transducer and their effects to the ultrasound pressure field. Take into account the change of ultrasound pressure field patterns in the conditions of variation of the pitches between elements of the phased-array ultrasound transducer, the appropriated parameters for phased-array ultrasound transducer design were asserted quantitatively.

Keywords: phased-array ultrasound transducer, sound pressure pattern, discontinuous sound field, numerical visualization

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Authors: Olomon Wu, Hung Lu, Nick Wilkins, Daniel Kerr, Zekeriya Aliyazicioglu, H. K. Hwang

Abstract:

Multiple Input Multiple Output (MIMO) radar has received increasing attention in recent years. MIMO radar has many advantages over conventional phased array radar such as target detection, resolution enhancement, and interference suppression. In this paper, the results are presented from a simulation study of MIMO Uniformly-Spaced Linear Array (ULA) antennas. The performance is investigated under varied parameters, including varied array size, Pseudo Random (PN) sequence length, number of snapshots, and Signal to Noise Ratio (SNR). The results of MIMO are compared to a traditional array antenna.

Keywords: MIMO radar, phased array antenna, target detection, radar signal processing

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Authors: Shafqat Ullah Khan, Ammar Nasir

Abstract:

Using planar antenna array (PAA) in radars, Broadcasting, satellite antennas, and sonar for the detection of targets, Helps provide instant beam pattern control. High flexibility and Adaptability are achieved by multiple beam steering by using a Planar array and are particularly needed in real-life Sanrio’s where the need arises for several high-directivity beams. Faulty sensors in planar arrays generate asymmetry, which leads to service degradation, radiation pattern distortion, and increased levels of sidelobe. The POA, a nature-inspired optimization algorithm, accurately determines faulty sensors within an array, enhancing the reliability and performance of planar array antennas through extensive simulations and experiments. The analysis was done for different types of faults in 7 x 7 and 8 x 8 planar arrays in MATLAB.

Keywords: Planar antenna array, , Pelican optimisation Algorithm, , Faculty sensor, Antenna arrays

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Authors: N.Revathy, C.Gomathi

Abstract:

This work aims for a tunable capacitor as a sensor which can vary the control voltage of a voltage control oscillator in a ultra wide band (UWB) transmitter. In this paper power consumption is concentrated. The reason for choosing a capacitive sensing is it give slow temperature drift, high sensitivity and robustness. Previous works report a resistive sensing in a voltage control oscillator (VCO) not aiming at power consumption. But this work aims for power consumption of a capacitive sensing in ultra wide band transmitter. The ultra wide band transmitter to be used is a direct modulation of pulses. The VCO which is the heart of pulse generator of UWB transmitter works on the principle of voltage to frequency conversion. The VCO has and odd number of inverter stages which works on the control voltage input this input is now from a variable capacitor and the buffer stages is reduced from the previous work to maintain the oscillating frequency. The VCO is also aimed to consume low power. Then the concentration in choosing a variable capacitor is aimed. A compact model of a capacitor with the transient characteristics is to be designed with a movable dielectric and multi metal membranes. Previous modeling of the capacitor transient characteristics is with a movable membrane and a fixed membrane. This work aims at a membrane with a wide tuning suitable for ultra wide band transmitter.This is used in this work because a capacitive in a ultra wide transmitter need to be tuned in such a way that all satisfies FCC regulations.

Keywords: capacitive sensing, ultra wide band transmitter, voltage control oscillator, FCC regulation

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Authors: M. Y. Ismail, M. Inam, A. F. M. Zain, N. Misran

Abstract:

Progressive phase distribution is an important consideration in reflect array antenna design which is required to form a planar wave in front of the reflect array aperture. This paper presents a detailed mathematical model in order to determine the required reflection phase values from individual element of a reflect array designed in Ku-band frequency range. The proposed technique of obtaining reflection phase can be applied for any geometrical design of elements and is independent of number of array elements. Moreover the model also deals with the solution of reflect array antenna design with both centre and off-set feed configurations. The theoretical modeling has also been implemented for reflect arrays constructed on 0.508 mm thickness of different dielectric substrates. The results show an increase in the slope of the phase curve from 4.61°/mm to 22.35°/mm by varying the material properties.

Keywords: mathematical modeling, progressive phase distribution, reflect array antenna, reflection phase

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Authors: Ajibola O. Akinrinde, Andrew Swanson, Remy Tiako

Abstract:

There exist significant losses on transmission lines due to distance, as power generating stations could be located far from some isolated settlements. Standalone wind farms could be a good choice of alternative power generation for such settlements that are far from the grid due to factors of long distance or socio-economic problems. However, uncompensated wind farms consume reactive power since wind turbines are induction generators. Therefore, capacitor banks are used to compensate reactive power, which in turn improves the voltage profile of the network. Although capacitor banks help improving voltage profile, they also undergo switching actions due to its compensating response to the variation of various types of load at the consumer’s end. These switching activities could cause transient overvoltage on the network, jeopardizing the end-life of other equipment on the system. In this paper, the overvoltage caused by these switching activities is investigated using the IEEE bus 14-network to represent a standalone wind farm, and the simulation is done using ATP/EMTP software. Scenarios involving the use of pre-insertion resistor and pre-insertion inductor, as well as controlled switching was also carried out in order to decide the best mitigation option to reduce the overvoltage.

Keywords: capacitor banks, IEEE bus 14-network, pre-insertion resistor, standalone wind farm

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Authors: Rawad Asfour, Salam Khamas, Edward A. Ball

Abstract:

This paper is focused on the design of an mm-wave phased array. To date, linear polarization is adapted in the reported designs of phased arrays. However, linear polarization faces several well-known challenges. As such, an advanced design for phased array antennas is required that offers circularly polarized (CP) radiation. A feasible solution for achieving CP phased array antennas is proposed using open-circular loop antennas. To this end, a 3-element circular loop phased array antenna is designed to operate at 28GHz. In addition, the array ability to control the direction of the main lobe is investigated. The results show that the highest achievable field of view (FOV) is 100°, i.e., 50° to the left and 50° to the right-hand side directions. The results are achieved with a CP bandwidth of 15%. Furthermore, the results demonstrate that a high broadside gain of circa 11 dBi can be achieved for the steered beam. Besides, a radiation efficiency of 97 % can also be achieved based on the proposed design.

Keywords: loop antenna, phased array, beam steering, wide bandwidth, circular polarization, CST

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Authors: Mohammad Arif Sobhan Bhuiyan, Zainal Abidin Nordin, Mamun Bin Ibne Reaz

Abstract:

A compact and power efficient high performance Voltage Controlled Oscillator (VCO) is a must in analog and digital circuits especially in the communication system, but the best trade-off among the performance parameters is a challenge for researchers. In this paper, a design of a compact 3-stage differential voltage controlled ring oscillator (VCRO) with low phase noise, low power and higher tuning bandwidth is proposed in 0.18 µm CMOS technology. The VCRO is designed with symmetric load and positive feedback techniques to achieve higher gain and minimum delay. The proposed VCRO can operate at tuning range of 3.9-5.0 GHz at 1.6 V supply voltage. The circuit consumes only 1.0757 mW of power and produces -129 dbc/Hz. The total active area of the proposed VCRO is only 11.74 x 37.73 µm2. Such a VCO can be the best choice for compact and low-power RF applications.

Keywords: CMOS, VCO, VCRO, oscillator

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Authors: Vinay Kumar K. S., Shravani V., Spoorthi G., Udith K. S., Divya T. M., Venkatesha M.

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In this work, the mathematical modeling, design and analysis of a 2×2 microstrip patch antenna array (MSPA) antenna configuration is presented. Array utilizes a tiny strip antenna module with two vertical slots for 5G applications at an operating frequency of 5.3 GHz. The proposed array of antennas where the phased array antenna systems (PAAS) are used ubiquitously everywhere, from defense radar applications to commercial applications like 5G/6G. Microstrip patch antennae with slot arrays for linear polarisation parallel and perpendicular to the axis, respectively, are fed through transverse slots in the side wall of the circular waveguide and fed through longitudinal slots in the small wall of the rectangular waveguide. The microstrip patch antenna is developed using Ansys HFSS (High-Frequency Structure Simulator), this simulation tool. The maximum gain of 6.14 dB is achieved at 5.3 GHz for a single MSPA. For 2×2 array structure, a gain of 7.713 dB at 5.3 GHz is observed. Such antennas find many applications in 5G devices and technology.

Keywords: Ansys HFSS, gain, return loss, slot array, microstrip patch antenna, 5G antenna

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Authors: S. Farag, A. Kuperman

Abstract:

In this paper, design of solid-state battery/super capacitor emulator based on dc-dc boost converter is described. The emulator mimics charging behavior of any storage device based on a predefined behavior set by the user. The device is operated by a two-level control structure: high-level emulating controller and low-level input voltage controller. Simulation and experimental results are shown to demonstrate the emulator operation.

Keywords: battery, charger, energy, storage, super capacitor

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: N. Reichbach, A. Kuperman

Abstract:

The paper describes a design of a monitoring system for super capacitor packs in propulsion systems, allowing determining the instantaneous energy capacity under power loading. The system contains real-time recursive-least-squares identification mechanism, estimating the values of pack capacitance and equivalent series resistance. These values are required for accurate calculation of the state-of-energy.

Keywords: real-time monitoring, RLS identification algorithm, state-of-energy, super capacitor

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Authors: Noha M. Rashad, W. Swelam, M. H. Abd ElAzeem

Abstract:

A simple design of array antenna is presented in this paper, supporting millimeter wave applications which can be used in short range wireless communications such as 5G applications. This design enhances the use of V-band, according to IEEE standards, as the antenna works in the 70 GHz band with bandwidth more than 11 GHz and peak gain more than 13 dBi. The design is simulated using different numerical techniques achieving a very good agreement.

Keywords: 5G technology, array antenna, microstrip, millimeter wave

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Authors: Jin Sup Kim, Min Seo

Abstract:

An improved cross-shaped hall plate with high sensitivity is described in this paper. Among different geometries that have been simulated and measured using Helmholtz coil. The paper describes the physical hall plate design and implementation in a 0.18-µm CMOS technology. In this paper, the biasing is a constant voltage mode. In the voltage mode, magnetic field is converted into an output voltage. The output voltage is typically in the order of micro- to millivolt and therefore, it must be amplified before being transmitted to the outside world. The study, design and performance optimization of hall plate has been carried out with the COMSOL Multiphysics. It is used to estimate the voltage distribution in the hall plate with and without magnetic field and to optimize the geometry. The simulation uses the nominal bias current of 1mA. The applied magnetic field is in the range from 0 mT to 20 mT. Measured results of the one structure over the 10 available samples show for the best sensitivity of 2.5 %/T at 20mT.

Keywords: cross-shaped hall plate, sensitivity, CMOS technology, Helmholtz coil

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Authors: Ju-Hong Lee, Ching-Wei Liao, Kun-Che Lee

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This paper deals with the problem of using antenna sensors for adaptive beamforming in the presence of random steering mismatch. We present an efficient adaptive array beamformer with robustness to deal with the considered problem. The robustness of the proposed beamformer comes from the efficient designation of the steering vector. Using the received array data vector, we construct an appropriate correlation matrix associated with the received array data vector and a correlation matrix associated with signal sources. Then, the eigenvector associated with the largest eigenvalue of the constructed signal correlation matrix is designated as an appropriate estimate of the steering vector. Finally, the adaptive weight vector required for adaptive beamforming is obtained by using the estimated steering vector and the constructed correlation matrix of the array data vector. Simulation results confirm the effectiveness of the proposed method.

Keywords: adaptive beamforming, antenna array, linearly constrained minimum variance, robustness, steering vector

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Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. A single ended 38.5 kS/s 10-bit programmable reference SAR ADC was proposed and implemented in a 0.35 µm CMOS technology and consumed less than 7.5 mW power with a 3 V supply.

Keywords: successive approximation register analog-to-digital converter, SAR ADC, resistive DAC, programmable reference

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Authors: Olesya Bolkhovskaya, Alexey Davydov, Alexander Maltsev

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In this paper approach to incoherent signal detection in multi-element antenna array are researched and modeled. Two types of useful signals with unknown wavefront were considered. First one is deterministic (Barker code), the second one is random (Gaussian distribution). The derivation of the sufficient statistics took into account the linearity of the antenna array. The performance characteristics and detecting curves are modeled and compared for different useful signals parameters and for different number of elements of the antenna array. Results of researches in case of some additional conditions can be applied to a digital communications systems.

Keywords: antenna array, detection curves, performance characteristics, quadrature processing, signal detection

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Authors: Somayeh Komeylian

Abstract:

Array signal processing techniques have been recently developing in a variety application of the performance enhancement of receivers by refraining the power of jamming and interference signals. In this scenario, biases induced to the antenna array receiver degrade significantly the accurate estimation of the carrier phase. Owing to the integration of frequency becomes the carrier phase, we have obtained the unbiased doppler frequency for the high precision estimation of carrier phase. The unbiased characteristic of Doppler frequency to the power jamming and the other interference signals allows achieving the highly accurate estimation of phase carrier. In this study, we have rigorously investigated the unbiased characteristic of Doppler frequency to the variation of the antenna array geometries. The simulation results have efficiently verified that the Doppler frequency remains also unbiased and accurate to the variation of antenna array geometries.

Keywords: array signal processing, unbiased doppler frequency, GNSS, carrier phase, and slowly fluctuating point target

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Authors: Ow Tze Weng, Suhaila Isaak, Yusmeeraz Yusof

Abstract:

The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability, especially in the most common electrocardiogram (ECG) monitoring system. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip (SoC) is increasing in exponential way, the front end ECG sensors are still suffering from flicker noise for low frequency cardiac signal acquisition, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a high performance CMOS amplifier for ECG sensors that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13 µm CMOS technology from Silterra, the simulation results show that this front end circuit can achieve a very low input referred noise of 1 pV/√Hz and high common mode rejection ratio (CMRR) of 174.05 dB. It also gives voltage gain of 75.45 dB with good power supply rejection ratio (PSSR) of 92.12 dB. The total power consumption is only 3 µW and thus suitable to be implemented with further signal processing and classification back end for low power biomedical SoC.

Keywords: CMOS, ECG, amplifier, low power

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Authors: Yo-Sheng Lin, Run-Chi Liu, Chien-Chu Ji, Chih-Chung Chen, Chien-Chin Wang

Abstract:

A W-band double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The mixer comprises an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation for conversion gain (CG) enhancement and current injection for power consumption reduction and linearity improvement, a Marchand balun for converting the single LO input signal to differential signal, another Marchand balun for converting the differential RF output signal to single signal, and an output buffer amplifier for loading effect suppression, power consumption reduction and CG enhancement. The mixer consumes low power of 6.9 mW and achieves LO-port input reflection coefficient of -17.8~ -38.7 dB and RF-port input reflection coefficient of -16.8~ -27.9 dB for frequencies of 90~100 GHz. The mixer achieves maximum CG of 3.6 dB at 95 GHz, and CG of 2.1±1.5 dB for frequencies of 91.9~99.4 GHz. That is, the corresponding 3 dB CG bandwidth is 7.5 GHz. In addition, the mixer achieves LO-RF isolation of 36.8 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation and power dissipation results are the best data ever reported for a 94 GHz CMOS/BiCMOS up-conversion mixer.

Keywords: CMOS, W-band, up-conversion mixer, conversion gain, negative resistance compensation, output buffer amplifier

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Authors: Nissar Mohammad Karim, Norhayati Soin

Abstract:

To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, Sol-Gel, precursor aging, aging

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Authors: Tian-Wei Huang, Wei-Ting Bai, Yu-Tung Cheng, Jeng-Han Tsai

Abstract:

In this paper, a 1-stage 6-section conventional distributed amplifier (CDA) structure distributed power amplifier (DPA) fabricated in a 28-nm HPC+ 1P9M CMOS process is proposed. The transistor size selection is introduced to achieve broadband power matching and thus remains a high flatness output power and power added efficiency (PAE) within the bandwidth. With the inductive peaking technique, the high-frequency pole appears and the high-frequency gain is increased; the gain flatness becomes better as well. The inductive elements used to form an artificial transmission line are built up with a floating ground coplanar waveguide plane (CPWFG) rather than a microstrip line, coplanar waveguide (CPW), or spiral inductor to get better performance. The DPA achieves 12.6 dB peak gain at 52.5 GHz with 2.9 to 64.9 GHz 3-dB bandwidth. The Psat is 11.4 dBm with PAEMAX of 10.6 % at 25 GHz. The output 1-dB compression point power is 9.8 dBm.

Keywords: distributed power amplifier (DPA), gain bandwidth (GBW), floating ground CPW, inductive peaking, 28-nm, CMOS, 5G.

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Authors: J. S. Kim

Abstract:

This paper presents a 0.13-µm Complementary Metal-Oxide Semiconductor (CMOS) vector modulator for beamforming system. The vector modulator features a 360° phase and gain range of -10 dB to 10 dB with a root mean square phase and amplitude error of only 2.2° and 0.45 dB, respectively. These features make it a suitable for wireless backhaul system in the 5 GHz industrial, scientific, and medical (ISM) bands. It draws a current of 20.4 mA from a 1.2 V supply. The total chip size is 1.87x1.34 mm².

Keywords: CMOS, vector modulator, beamforming, 802.11ac

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Authors: Nissar Mohammad Karim, Norhayati Soin

Abstract:

To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, sol-gel, precursor ageing, metallurgical and materials engineering

Procedia PDF Downloads 387

Authors: Dia I. Abu-Al-Nadi, M. J. Mismar, T. H. Ismail

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A technique for estimating the direction-of-arrival (DOA) of unknown number of source signals is presented using the eigen-approach. The eigenvector corresponding to the minimum eigenvalue of the autocorrelation matrix yields the minimum output power of the array. Also, the array polynomial with this eigenvector possesses roots on the unit circle. Therefore, the pseudo-spectrum is found by perturbing the phases of the roots one by one and calculating the corresponding array output power. The results indicate that the DOAs and the number of source signals are estimated accurately in the presence of a wide range of input noise levels.

Keywords: array signal processing, direction-of-arrival, antenna arrays, Eigenvalues, Eigenvectors, Lagrange multiplier

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Authors: M. Aeysha Parvin, J. Asha, J. Jenifer

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This letter presents a novel frequency-shift keying(FSK) receiver using PLL-based FSK demodulator, thereby achieving high sensitivity and low power consumption. The proposed receiver comprises a power amplifier, mixer, 3-stage ring oscillator, PLL based demodulator. Moreover, the proposed receiver is fabricated using 0.12µm CMOS process and consumes 0.7Mw. Measurement results demonstrate that the proposed receiver has a sensitivity of -93dbm with 1Mbps data rate in receiving a 2.4 GHz FSK signal.

Keywords: CMOS FSK receiver, phase locked loop (PLL), 3-stage ring oscillator, FSK signal

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Authors: Mohamad Farhat, Bal Virdee

Abstract:

This paper present a compact Microstrip Bandpass filter exhibiting a very wide stop band and high selectivity. The filter comprises of asymmetric resonator structures, which are interconnected by an inter-digital capacitor to enable the realization of a wide bandwidth with high rejection level. High selectivity is obtained by optimizing the parameters of the interdigital capacitor. The filter has high out-of-band rejection (> 30 dB), less than 0.6 dB of insertion-loss, up to 5.5 GHz spurii free, and about 18 dB of return-loss. Full-wave electromagnetic simulator ADSTM (Mom) is used to analyze and optimize the prototype bandpass filter. The proposed technique was verified practically to validate the design methodology. The experimental results of the prototype circuit are presented and a good agreement was obtained comparing with the simulation results. The dimensions of the proposed filter are 32 x 24 mm2.The filter’s characteristics and compact size make it suitable for wireless communication systems.

Keywords: asymmetric resonator, bandpass filter, microstrip, spurious suppression, ultra-wide stop band

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Authors: Varun Kumar, Chandra Shakher

Abstract:

Micro-optical components such as microlenses and microlens array have numerous engineering and industrial applications for collimation of laser diodes, imaging devices for sensor system (CCD/CMOS, document copier machines etc.), for making beam homogeneous for high power lasers, a critical component in Shack-Hartmann sensor, fiber optic coupling and optical switching in communication technology. Also micro-optical components have become an alternative for applications where miniaturization, reduction of alignment and packaging cost are necessary. The compliance with high-quality standards in the manufacturing of micro-optical components is a precondition to be compatible on worldwide markets. Therefore, high demands are put on quality assurance. For quality assurance of these lenses, an economical measurement technique is needed. For cost and time reason, technique should be fast, simple (for production reason), and robust with high resolution. The technique should provide non contact, non-invasive and full field information about the shape of micro- optical component under test. The interferometric techniques are noncontact type and non invasive and provide full field information about the shape of the optical components. The conventional interferometric technique such as holographic interferometry or Mach-Zehnder interferometry is available for characterization of micro-lenses. However, these techniques need more experimental efforts and are also time consuming. Digital holography (DH) overcomes the above described problems. Digital holographic microscopy (DHM) allows one to extract both the amplitude and phase information of a wavefront transmitted through the transparent object (microlens or microlens array) from a single recorded digital hologram by using numerical methods. Also one can reconstruct the complex object wavefront at different depths due to numerical reconstruction. Digital holography provides axial resolution in nanometer range while lateral resolution is limited by diffraction and the size of the sensor. In this paper, Mach-Zehnder based digital holographic interferometric microscope (DHIM) system is used for the testing of transparent microlenses. The advantage of using the DHIM is that the distortions due to aberrations in the optical system are avoided by the interferometric comparison of reconstructed phase with and without the object (microlens array). In the experiment, first a digital hologram is recorded in the absence of sample (microlens array) as a reference hologram. Second hologram is recorded in the presence of microlens array. The presence of transparent microlens array will induce a phase change in the transmitted laser light. Complex amplitude of object wavefront in presence and absence of microlens array is reconstructed by using Fresnel reconstruction method. From the reconstructed complex amplitude, one can evaluate the phase of object wave in presence and absence of microlens array. Phase difference between the two states of object wave will provide the information about the optical path length change due to the shape of the microlens. By the knowledge of the value of the refractive index of microlens array material and air, the surface profile of microlens array is evaluated. The Sag of microlens and radius of curvature of microlens are evaluated and reported. The sag of microlens agrees well within the experimental limit as provided in the specification by the manufacturer.

Keywords: micro-optics, microlens array, phase map, digital holographic interferometric microscopy

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

Procedia PDF Downloads 512