Search results for: system on chip

Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

Abstract:

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: WiNoC, simulation tool, network-on-chip, SoC

Procedia PDF Downloads 498

Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

Abstract:

Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

Procedia PDF Downloads 380

Authors: J. Shiue, I. H. Chen, S. W. Y. Chiu, Y. L. Wang

Abstract:

In this work, we present a nondestructive method to characterize bacteria in a TEM system. Unlike the conventional TEM specimen preparation method, which needs to thin the specimen in a destructive way, or spread the samples on a tiny millimeter sized carbon grid, our method is easy to operate without the need of sample pretreatment. With a specially designed transparent chip that allows the electron beam to pass through, and a custom made chip holder to fit into a standard TEM sample holder, the bacteria specimen can be easily prepared on the chip without any pretreatment, and then be observed under TEM. The centimeter-sized chip is covered with Au nanoparticles in the surface as the markers which allow the bacteria to be observed easily on the chip. We demonstrate the success of our method by using E. coli as an example, and show that high-resolution TEM images of E. coli can be obtained with the method presented. Some E. coli morphology characteristics imaged using this method are also presented.

Keywords: bacteria, chip, nanoparticles, TEM

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Authors: Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum

Abstract:

3D technology can lead to a significant reduction in power and average hop-count in Networks on Chip (NoCs). It offers short and fast vertical links which copes with the long wire problem in 2D NoCs. This work proposes heuristic-based method to optimize number and placement of vertical links to achieve specified performance goals. Experiments show that significant improvement can be achieved by using a specific number of vertical interconnect.

Keywords: interconnect optimization, monolithic inter-tier vias, network on chip, system on chip, through silicon vias, three dimensional integration circuits

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Authors: Vedat Coskun, Fahri Soylemezgiller, Busra Ozdenizci, Kerem Ok

Abstract:

In recent years, several smart card solutions for transportation services of cities with different technical infrastructures and business models has emerged considerably, which triggers new business and technical opportunities. In order to create a unique system, we present a novel, promising system called Multifunctional City Smart Card System to be used in all cities that provides transportation and loyalty services based on the MasterCard M/Chip Advance standards. The proposed system provides a unique solution for transportation services of large cities over the world, aiming to answer all transportation needs of citizens. In this paper, development of the Multifunctional City Smart Card System and system requirements are briefly described. Moreover, performance analysis results of M/Chip Advance Compatible Validators which is the system's most important component are presented.

Keywords: smart card, m/chip advance standard, city transportation, performance analysis

Procedia PDF Downloads 475

Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: methodology, flip chip, bump cell, LEF, astro, calibre, SCHEME, TCL

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Authors: Long Kim Vu

Abstract:

The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

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Authors: Bhuvnesh Narayanan, Bernhard Weiss, Tvrtko Mandic, Adrijan Baric

Abstract:

This paper discusses a method to reconstruct internal high-frequency signals through subsampling techniques in an IC using an on-chip sensor. Though there are existing methods to internally probe and reconstruct high frequency signals through subsampling techniques; these methods have been applicable mainly for synchronized systems. This paper demonstrates a method for making such non-intrusive on-chip reconstructions possible also in non-synchronized systems. The TLP pulse is used to demonstrate the experimental validation of the concept. The on-chip sensor measures the voltage in an internal node. The jitter in the input pulse causes a varying pulse delay with respect to the on-chip sampling command. By measuring this pulse delay and by correlating it with the measured on-chip voltage, time domain waveforms can be reconstructed, and the influence of the pulse on the internal nodes can be better understood.

Keywords: on-chip sensor, jitter, transmission line pulse, subsampling

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Authors: Kadir Gök

Abstract:

In this study, a vacuum system was developed for orthopedic drilling processes, and the most efficient processing parameters were determined using statistical analysis of temperature rise. A reverse engineering technique was used to obtain a 3D model of the chip vacuum system, and the obtained point cloud data was transferred to Solidworks software in STL format. An experimental design method was performed by selecting different parameters and their levels, such as RPM, feed rate, and drill bit diameter, to determine the most efficient processing parameters in temperature rise using ANOVA. Additionally, the bone chip-vacuum device was developed and performed successfully to collect the whole chips and fragments in the bone drilling experimental tests, and the chip-collecting device was found to be useful in removing overheating from the drilling zone. The effects of processing parameters on the temperature levels during the chip-vacuuming were determined, and it was found that bone chips and fractures can be used as autograft and allograft for tissue engineering. Overall, this study provides significant insights into the development of a vacuum system for orthopedic drilling processes and the use of bone chips and fractures in tissue engineering applications.

Keywords: vacuum system, orthopedic drilling, temperature rise, bone chips

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Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

Abstract:

High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: integration, electrokinetic, on-chip, fluid pumping, microfluidic

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Authors: Martin Pumera

Abstract:

Graphene materials are being widely used in electrochemistry due to their versatility and excellent properties as platforms for biosensing. Here we present current trends in the electrochemical biosensing of pesticides and other toxic compounds. We explore two fundamentally different designs, (i) using graphene and other 2-D nanomaterials as an electrochemical platform and (ii) using these nanomaterials in the laboratory on chip design, together with paramagnetic beads. More specifically: (i) We explore graphene as transducer platform with very good conductivity, large surface area, and fast heterogeneous electron transfer for the biosensing. We will present the comparison of these materials and of the immobilization techniques. (ii) We present use of the graphene in the laboratory on chip systems. Laboratory on the chip had a huge advantage due to small footprint, fast analysis times and sample handling. We will show the application of these systems for pesticide detection and detection of other toxic compounds.

Keywords: graphene, 2D nanomaterials, biosensing, chip design

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Authors: Yu Qin

Abstract:

In order to tackle the ever-growing problem of the lack of parking space, this paper presents the design and implementation of a smart unmanned parking system that is based on RFID (radio frequency identification) technology and Wireless communication technology. This system uses RFID technology to achieve the identification function (transmitted by 2.4 G wireless module) and is equipped with an STM32L053 micro controller as the main control chip of the smart vehicle. This chip can accomplish automatic parking (in/out), charging and other functions. On this basis, it can also help users easily query the information that is stored in the database through the Internet. Experimental tests have shown that the system has the features of low power consumption and stable operation, among others. It can effectively improve the level of automation control of the parking lot management system and has enormous application prospects.

Keywords: RFID, embedded system, unmanned, parking management

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Authors: Mohsen Marani Barzani, Ahmed A. D. Sarhan, Saeed Farahany, Ramesh Singh

Abstract:

Surface roughness and chip morphology are important output in manufacturing product. In this paper, an experimental investigation was conducted to determine the effects of various cutting speeds and feed rates on surface roughness and chip morphology in turning the Al-Si cast alloy and Sr-containing. Experimental trials carried out using coated carbide inserts. Experiments accomplished under oblique dry cutting when various cutting speeds 70, 130 and 250 m/min and feed rates of 0.05, 0.1 and 0.15 mm/rev were used, whereas depth of cut kept constant at 0.05 mm. The results showed that Sr-containing Al-Si alloy have poor surface roughness in comparison to Al-Si alloy (base alloy). The surface roughness values reduce with cutting speed increment from 70 to 250 m/min. the size of chip changed with changing silicon shape in Al matrix. Also, the surface finish deteriorated with increase in feed rate from 0.5 mm/rev to 0.15 mm/rev.

Keywords: strontium, surface roughness, chip, morphology, turning

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Authors: M. Benghersallah, L. Boulanouar, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000 and 1200 m / min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. In these experiments, the chip shape was systematically investigated at each cutting conditions using optical microscopy. The chips produced were collected and polished to measure the thicknesses t2max and t2min, dch the distance between each segments and ɸseg the inclination angle As described in the introduction part, the shear angle f and the inclination angle of a segment ɸseg are differentiated. The angle ɸseg is actually measured on the collected chips while the shear angle f cannot be. The angle ɸ represents the initial shear similar to the one that describes the formation of a continuous chip in the primary shear zone. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: dry high speed, orthogonal turning, chip formation, cutting speed, cutting forces

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Authors: Zhuohan Li, Jing Yang, Yaoyuan Cui

Abstract:

The gut-brain axis (GBA), a communication network between gut microbiota and the brain, benefits for investigation of brain diseases. Currently, organ chips are considered one of the potential tools for GBA research. However, most of the available GBA chips have limitations in replicating the three-dimensional (3D) growth environment of cells and lack the required cell types for barrier function. In the present study, a microfluidic chip was developed for GBA interaction. Blood-brain barrier (BBB) module was prepared with HBMEC, HBVP, U87 cells and decellularized matrix (dECM). Intestinal epithelial barrier (IEB) was prepared with Caco-2 and vascular endothelial cells and dECM. GBA microfluidic device was integrated with IEB and BBB modules using 3D printing interconnecting microchannel scaffolds. BBB and IEB interaction on this GBA chip were evaluated with lipopolysaccharide (LPS) exposure. The present GBA chip achieved multicellular three-dimensional cultivation. Compared with the co-culture cell model in the transwell, fluorescein was absorbed more slowly by 5.16-fold (IEB module) and 4.69-fold (BBB module) on the GBA chip. Accumulation of Rhodamine 123 and Hoechst33342 was dramatically decreased. The efflux function of transporters on IEB and BBB was significantly increased on the GBA chip. After lipopolysaccharide (LPS) disrupted the IEB, and then BBB dysfunction was further observed, which confirmed the interaction between IEB and BBB modules. These results demonstrated that this GBA chip may offer a promising tool for gut-brain interaction study.

Keywords: decellularized matrix, gut-brain axis, organ-on-chip, three-dimensional printing.

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

Abstract:

A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Guowei Hou, Lixin Yu, Wei Zhuang, Hui Qin, Xue Yang

Abstract:

Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient. As cache plays a vital role in the design of System on Chip (SoC), and cache with Memory Management Unit (MMU) and cache memory unit makes the state space too large for simulation to verify, then a formal verification is presented for such system design. In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called “exhaustive search model” is proposed. Instead of using large size ram to denote the whole cache memory, exhaustive search model employs just two cache blocks. For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism. At last, the novel model is employed to the verification of a cache which is module of a custom-built SoC system that has been applied in practical, and the result shows that the cache system is verified correctly using the exhaustive search model, and it makes the verification much more manageable and flexible.

Keywords: cache system, formal verification, novel model, system on chip (SoC)

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Authors: Chun-Ming Huang, Yi-Jun Liu, Yi-Jie Hsieh, Jin-Ju Chue, Wei-Lin Lai, Chun-Yu Chen, Chih-Chyau Yang, Chien-Ming Wu

Abstract:

The market of wearable devices has been growing rapidly in two years. The integration of sensors and wearable devices has become the trend of the next technology products. Thus, the academics and industries are eager to cultivate talented persons in sensing technology. Currently, academic and industries have more and more demands on the integrations of versatile sensors and applications, especially for the teams who focus on the development of sensor circuit architectures. These teams tape-out many MEMs sensors chips through the chip fabrication service from National Chip Implementation Center (CIC). However, most of these teams are only able to focus on the circuit design of MEMs sensors; they lack the key support of further system demonstration. This paper follows the CIC’s main mission of promoting the chip/system advanced design technology and aims to establish the environments of the modularized sensing system platform and the system design flow with the measurement and calibration technology. These developed environments are used to support these research teams and help academically advanced sensor designs to perform the system demonstration. Thus, the research groups can promote and transfer their advanced sensor designs to industrial and further derive the industrial economic values. In this paper, the modularized sensing platform is proposed to enable the system demonstration for advanced sensor chip design. The environment of sensor measurement and calibration is established for academic to achieve an accurate sensor result. Two reference sensor designs cooperated with the modularized sensing platform are given to show the sensing system integration and demonstration. These developed environments and platforms are currently provided to academics in Taiwan, and so that the academics can obtain a better environment to perform the system demonstration and improve the research and teaching quality.

Keywords: modularized sensing platform, sensor design and calibration, sensor system, sensor system design flow

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Authors: Pedro Acevedo, Carlos Díaz, Mónica Vázquez, Joel Durán

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This paper describes the design of a pulse generator based on the Programmable System-on-Chip (PSoC) module. In this module, using programmable logic is possible to implement different pulses which are required for ultrasonic applications, either in a single channel or multiple channels. This module can operate with programmable frequencies from 3-74 MHz; its programming may be versatile covering a wide range of ultrasonic applications. It is ideal for low-power ultrasonic applications where PZT or PVDF transducers are used.

Keywords: PSoC, pulse generator, PVDF, ultrasonic transducer

Procedia PDF Downloads 293

Authors: Han-Bin Park, Taesam Kang, SunKi Hong, Jeong Hoi Gu

Abstract:

The piezoelectric material is being used widely for actuators due to its large power density with simple structure. It can generate a larger force than the conventional actuators with the same size. Furthermore, the response time of piezoelectric actuators is very short, and thus, it can be used for very fast system applications with compact size. To control the piezoelectric actuator, we need analog signal conditioning circuits as well as digital microcontrollers. Conventional microcontrollers are not equipped with analog parts and thus the control system becomes bulky compared with the small size of the piezoelectric devices. To overcome these weaknesses, we are developing one-chip micro controller that can handle analog and digital signals simultaneously using mixed signal FPGA technology. We used the SmartFusion™ FPGA device that integrates ARM®Cortex-M3, analog interface and FPGA fabric in a single chip and offering full customization. It gives more flexibility than traditional fixed-function microcontrollers with the excessive cost of soft processor cores on traditional FPGAs. In this paper we introduce the design of single chip controller using mixed signal FPGA, SmartFusion™[1] device. To demonstrate its performance, we implemented a PI controller for power driving circuit and a 5th order H-infinity controller for the system with piezoelectric actuator in the FPGA fabric. We also demonstrated the regulation of a power output and the operation speed of a 5th order H-infinity controller.

Keywords: mixed signal FPGA, PI control, piezoelectric actuator, SmartFusion™

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Authors: M. Benghersallah, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000, and 1200 m/min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: titanium alloy, dry hjgh speed turning, wear insert, MQL technique

Procedia PDF Downloads 555

Authors: Moaz H. Ali, Ahmed H. Al-Saadi

Abstract:

Most of the materials used in the industry of aero-engine components generally consist of titanium alloys. Advanced materials, because of their excellent combination of high specific strength, lightweight, and general corrosion resistance. In fact, chemical wear resistance of aero-engine alloy provide a serious challenge for cutting tool material during the machining process. The reduction in cutting temperature distributions leads to an increase in tool life and a decrease in wear rate. Hence, the chip morphology and segmentation play a predominant role in determining machinability and tool wear during the machining process. The result of low thermal conductivity and diffusivity of this alloy in the concentration of high temperatures at the tool-work-piece and tool-chip interface. Consequently, the chip morphology is very important in the study of machinability of metals as well as the study of cutting tool wear. Otherwise, the result will be accelerating tool wear, increasing manufacturing cost and time consuming.

Keywords: machinability, titanium alloy (ti-6al-4v), chip formation, milling process

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Authors: Sherif K. El Dyasti, Esam A. Hagras, Adel E. El-Hennawy

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This paper addresses the performance of antenna array beam-forming on Chip-Interleaved Code Division Multiple Access (CI_CDMA) system based on Minimum Mean Square Error (MMSE) detector in aeronautical mobile radio channel. Multipath fading, Doppler shifts caused by the speed of the aircraft, and Multiple Access Interference (MAI) are the most important reasons that affect and reduce the performance of aeronautical system. In this paper, we suggested the CI-CDMA with antenna array to combat this fading and improve the bit error rate (BER) performance. We further evaluate the performance of the proposed system in the four standard scenarios in aeronautical mobile radio channel.

Keywords: aeronautical channel, CI-CDMA, beamforming, communication, information

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Authors: Muhammad Rosli Abdullah, Noor Hasmiza Harun

Abstract:

A microorganism detection system has a potential to be used with the advancement in a biosensor development. The detection system requires an optical sensing system, microfluidic device and biological reagent. Although, the biosensors are available in the market, a label free and a lab-on-chip approach will promote a flexible solution. As a preliminary study of microorganism detection, three mechanisms such as Total Internal Reflection (TIR), Micro Fluidic Channel (MFC) and magnetic-electric field propagation were study and simulated. The objective are to identify the TIR angle, MFC parabolic flow and the wavelength for the microorganism detection. The simulation result indicates that evanescent wave is achieved when TIR angle > 42°, the corner and centre of a parabolic velocity are 0.02 m/s and 0.06 m/s respectively, and a higher energy distribution of a perfect electromagnetic scattering with dipole resonance radiation occurs at 500 nm. This simulation is beneficial to determine the components of the microorganism detection system that does not rely on classical microbiological, immunological and genetic methods which are laborious, time-consuming procedures and confined to specialized laboratories with expensive instrumentation equipment.

Keywords: microorganism, microfluidic, total internal reflection, lab on chip

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Authors: Vinayaga Jagadessh Raja, R. Ganesan, S. Ramesh Kumar

Abstract:

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system on- chip (SoC) is due to the interconnection scheme. In information, as equipment shrinks, the power contributes of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of clock gating in the data encoding techniques as a viable way to reduce both power dissipation and time consumption of NoC links. The projected scramble scheme exploits the wormhole switching techniques. That is, flits are scramble by the network interface (NI) before they are injected in the network and are decoded by the target NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers structural design is required. We review the projected scramble scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links.

Keywords: Xilinx 12.1, power consumption, Encoder, NOC

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Authors: D. O. Ramadan, R. S. Dwyer-Joyce

Abstract:

The measurement of the interface conditions in a cutting tool contact is essential information for performance monitoring and control. This interface provides the path for the heat flux to the cutting tool. This elevate in the cutting tool temperature leads to motivate the mechanism of tool wear, thus affect the life of the cutting tool and the productivity. This zone is representative by the tool-chip interface. Therefore, understanding and monitoring this interface is considered an important issue in machining. In this paper, an acoustic emission (AE) technique was used to find the correlation between AE parameters and the tool-chip interface. For this reason, a response surface design (RSD) has been used to analyse and optimize the machining parameters. The experiment design was based on the face centered, central composite design (CCD) in the Minitab environment. According to this design, a series of orthogonal cutting experiments for different cutting conditions were conducted on a Triumph 2500 lathe machine to study the sensitivity of the acoustic emission (AE) signal to change in tool-chip contact length. The cutting parameters investigated were the cutting speed, depth of cut, and feed and the experiments were performed for 6082-T6 aluminium tube. All the orthogonal cutting experiments were conducted unlubricated. The tool-chip contact area was investigated using a scanning electron microscope (SEM). The results obtained in this paper indicate that there is a strong dependence of the root mean square (RMS) on the cutting speed, where the RMS increases with increasing the cutting speed. A dependence on the tool-chip contact length has been also observed. However there was no effect observed of changing the cutting depth and feed on the RMS. These dependencies have been clarified in terms of the strain and temperature in the primary and secondary shear zones, also the tool-chip sticking and sliding phenomenon and the effect of these mechanical variables on dislocation activity at high strain rates. In conclusion, the acoustic emission technique has the potential to monitor in situ the tool-chip interface in turning and consequently could indicate the approaching end of life of a cutting tool.

Keywords: Acoustic emission, tool-chip interface, orthogonal cutting, monitoring

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Authors: Laura Boschis, Elena D. Ozzello, Enzo Mastromatteo

Abstract:

Point of care diagnostic finds growing interest in medicine and agri-food because of faster intervention and prevention. EliChip is a microfluidic platform to perform Point of Care immunoenzymatic assay based on ready-to-use kits and a portable instrument to manage fluidics and read reliable quantitative results. Thanks to miniaturization, analyses are faster and more sensible than conventional ELISA. EliChip is one of the crucial assets of the Europen-founded Flamingo project for in-line measuring inflammatory markers.

Keywords: lab on chip, point of care, immunoenzymatic analysis, synovial arthritis

Procedia PDF Downloads 187

Authors: Junior Nomani

Abstract:

This paper presents a novel approach to modelling the metal cutting of duplex stainless steels, a two-phase alloy regarded as a difficult-to-machine material. Calculation and control of shear strain and stresses during cutting are essential to achievement of ideal cutting conditions. Too low or too high leads to higher required cutting force or excessive heat generation causing premature tool wear failure. A 2D finite element cutting model was created based on electron backscatter diffraction (EBSD) data imagery of duplex microstructure. A mesh was generated using ‘object-oriented’ software OOF2 version V2.1.11, converting microstructural images to quadrilateral elements. A virtual workpiece was created on ABAQUS modelling software where a rigid body toolpiece advanced towards workpiece simulating chip formation, generating serrated edge chip formation cutting. Model results found calculated stress strain contour plots correlated well with similar finite element models tied with austenite stainless steel alloys. Virtual chip form profile is also similar compared experimental frozen machining chip samples. The output model data provides new insight description of strain behavior of two phase material on how it transitions from workpiece into the chip.

Keywords: Duplex stainless steel, ABAQUS, OOF2, Chip formation

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Authors: Zhao Bin, Yan Dan Lei

Abstract:

In this paper, a multi-pattern parallel PRBS generator and a dedicated parallel BER tester is proposed for the 8-Gbps On-chip interconnection testing. A unique full-parallel PRBS checker is also proposed. The proposed design, together with the custom-designed high-speed parallel-to-serial and the serial-to-parallel circuit, will be used to test different on-chip interconnection transceivers. The design is implemented in TSMC 28nm CMOS technology with working voltage at 1.0 V. The serial to parallel ratio is 8:1 so the parallel PRBS generation and BER Tester can be run at lower speed.

Keywords: PRBS, BER, high speed, generator

Procedia PDF Downloads 762