Search results for: flash memory

Authors: Yi-Pin Hsu, Shin-Yu Lin

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An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.

Keywords: Parallel-computing, FFT, low-memory reference, TIDSP.

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Authors: Suzana Basaruddin, Haryani Haron, Siti Arpah Noodin

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Managing knowledge of research is one way to ensure just in time information and knowledge to support research strategist and activities. Unfortunately researcher found the vital research knowledge in IHL (Institutions of Higher Learning) are scattered, unstructured and unorganized. Aiming on lay aside conceptual foundations for understanding and developing OMS (Organizational Memory System) to facilitate research in IHL, this research revealed ten factors contributed to the needs of research in the IHL and seven internal challenges of IHL in promoting research to their academic members. This study then suggested a comprehensive support of managing research knowledge using Organizational Memory System (OMS). Eight OMS characteristics to support research were identified. Finally the initial work in designing OMS was projected using knowledge taxonomy. All analysis is derived from pertinent research paper related to research in IHL and OMS. Further study can be conducted to validate and verify results presented.

Keywords: corporate memory, Institutions of Higher Learning, organizational memory system, research

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Authors: Md Abid Khan

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A recognized engineering challenge is related to personnel protection from fatal arc flash incident energy in the line side of the 480-volt switchgears incomer breakers during maintenance activities. The incident energy is typically high due to slow fault clearance and it can be higher than the available personnel protective equipment (PPE) ratings. A fault on the line side of the 480 Volt breaker is cleared by breakers or fuses in the upstream higher voltage system (4160 Volt or higher). The current reflection in the higher voltage upstream system for a fault in the 480-volt switchgear is low, the clearance time is slower and the inversely proportional incident energy is hence higher. The installation of overcurrent protection at 480-volt system upstream of the incomer breaker will operate fast enough and trips the upstream higher voltage breaker when a fault develops at the incomer breaker. Therefore, fault current reduction as reflected in the upstream higher voltage system is eliminated. Since the fast overcurrent protection is permanently installed, it is always functional, do not require human interventions and eliminates exposure to human errors. It is installed at the maintenance activity location and its operations can be locally monitored by craftsmen during maintenance activities.

Keywords: Arc flash, mitigation, maintenance switch, energy level.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

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With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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Authors: Mountassar Maamoun, Mehdi Neggazi, Abdelhamid Meraghni, Daoud Berkani

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This paper presents a VLSI design approach of a highspeed and real-time 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. Furthermore, an advanced twodimensional (2-D) discrete wavelet transform (DWT) implementation, with an efficient memory area, is designed to produce one output in every clock cycle. As a result, a very highspeed is attained. The system is verified, using JPEG2000 coefficients filters, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory. The resulting computing rate is up to 270 M samples/s and the (9,7) 2-D wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out memory) with 256×256 image size. In this way, the developed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.

Keywords: Discrete Wavelet Transform (DWT), Fast Convolution, FPGA, VLSI.

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Authors: M. Goodarzi, P. Lashgari

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A major part of the flow field involves no complicated turbulent behavior in many turbulent flows. In this research work, in order to reduce required memory and CPU time, the flow field was decomposed into several blocks, each block including its special turbulence. A two dimensional backward facing step was considered here. Four combinations of the Prandtl mixing length and standard k- E models were implemented as well. Computer memory and CPU time consumption in addition to numerical convergence and accuracy of the obtained results were mainly investigated. Observations showed that, a suitable combination of turbulence models in different blocks led to the results with the same accuracy as the high order turbulence model for all of the blocks, in addition to the reductions in memory and CPU time consumption.

Keywords: Computer memory, CPU time, Multi-block method, Turbulence modeling.

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Authors: Leila Maleki, Ezatollah Ahmadi

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The aim of this study was to investigate the effectiveness of memory training exercise on cognitive flexibility. The method of this study was experimental. The statistical population selected 40 students 14 years old, samples were chosen by available sampling method and then they were replaced in experimental (training program) group and control group randomly and answered to Wisconsin Card Sorting Test; covariance test results indicated that there were a significant in post-test scores of experimental group (p<0.005).

Keywords: Cognitive flexibility, working memory exercises, problem solving, reaction time.

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Authors: N. Khon, A. Kim, T. Mukhitdinova

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The aim of this research was to reveal the link between mental variables, such as spatial abilities, memory, intellect and professional experience of drivers. Participants were allocated to four groups: no experience, inexperienced, skilled and professionals (total 85 participants). The level of ability for spatial navigation and indicator of nonverbal memory grow along the process of accumulation of driving experience. At high levels of driving experience, this tendency is especially noticeable. The professionals having personal achievements in driving (racing) differ from skilled drivers in better feeling of direction, which is specific for them not just in a short-term situation of an experimental task, but also in life-size perspective. The level of ability of mental rotation does not grow with the growth of driving experience, which confirms the multiple intelligence theory according to which spatial abilities represent specific, other than logical intelligence type of intellect. The link between spatial abilities, memory, intellect and professional experience of drivers seems to be different relating spatial navigation or mental rotation as different kinds of spatial abilities.

Keywords: Memory, spatial abilities, intellect, drivers.

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Authors: Sofien Chtourou, Mohamed Chtourou, Omar Hammami

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Embedded systems need to respect stringent real time constraints. Various hardware components included in such systems such as cache memories exhibit variability and therefore affect execution time. Indeed, a cache memory access from an embedded microprocessor might result in a cache hit where the data is available or a cache miss and the data need to be fetched with an additional delay from an external memory. It is therefore highly desirable to predict future memory accesses during execution in order to appropriately prefetch data without incurring delays. In this paper, we evaluate the potential of several artificial neural networks for the prediction of instruction memory addresses. Neural network have the potential to tackle the nonlinear behavior observed in memory accesses during program execution and their demonstrated numerous hardware implementation emphasize this choice over traditional forecasting techniques for their inclusion in embedded systems. However, embedded applications execute millions of instructions and therefore millions of addresses to be predicted. This very challenging problem of neural network based prediction of large time series is approached in this paper by evaluating various neural network architectures based on the recurrent neural network paradigm with pre-processing based on the Self Organizing Map (SOM) classification technique.

Keywords: Address, data set, memory, prediction, recurrentneural network.

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Authors: Eleni Ioanna Levantinou

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Gestures play a major role in comprehension and memory recall due to the fact that aid the efficient channel of the meaning and support listeners’ comprehension and memory. In the present study, the assistance of two kinds of gestures (iconic and beat gestures) is tested in regards to memory and recall. The hypothesis investigated here is whether or not iconic and beat gestures provide assistance in memory and recall in Greek and in Greek speakers’ second language. Two groups of participants were formed, one comprising Greeks that reside in Athens and one with Greeks that reside in Copenhagen. Three kinds of stimuli were used: A video with words accompanied with iconic gestures, a video with words accompanied with beat gestures and a video with words alone. The languages used are Greek and English. The words in the English videos were spoken by a native English speaker and by a Greek speaker talking English. The reason for this is that when it comes to beat gestures that serve a meta-cognitive function and are generated according to the intonation of a language, prosody plays a major role. Thus, participants that have different influences in prosody may generate different results from rhythmic gestures. Memory recall was assessed by asking the participants to try to remember as many words as they could after viewing each video. Results show that iconic gestures provide significant assistance in memory and recall in Greek and in English whether they are produced by a native or a second language speaker. In the case of beat gestures though, the findings indicate that beat gestures may not play such a significant role in Greek language. As far as intonation is concerned, a significant difference was not found in the case of beat gestures produced by a native English speaker and by a Greek speaker talking English.

Keywords: First language, gestures, memory, second language acquisition.

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Authors: Dalvinder Singh Dhaliwal, Parvinder S. Sandhu, S. N. Panda

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This paper is on the general discussion of memory consistency model like Strict Consistency, Sequential Consistency, Processor Consistency, Weak Consistency etc. Then the techniques for implementing distributed shared memory Systems and Synchronization Primitives in Software Distributed Shared Memory Systems are discussed. The analysis involves the performance measurement of the protocol concerned that is Multiple Writer Protocol. Each protocol has pros and cons. So, the problems that are associated with each protocol is discussed and other related things are explored.

Keywords: Distributed System, Single owner protocol, Multiple owner protocol

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Authors: Samuel Kaspi, Sitalakshmi Venkatraman

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In-memory database systems are becoming popular due to the availability and affordability of sufficiently large RAM and processors in modern high-end servers with the capacity to manage large in-memory database transactions. While fast and reliable inmemory systems are still being developed to overcome cache misses, CPU/IO bottlenecks and distributed transaction costs, disk-based data stores still serve as the primary persistence. In addition, with the recent growth in multi-tenancy cloud applications and associated security concerns, many organisations consider the trade-offs and continue to require fast and reliable transaction processing of diskbased database systems as an available choice. For these organizations, the only way of increasing throughput is by improving the performance of disk-based concurrency control. This warrants a hybrid database system with the ability to selectively apply an enhanced disk-based data management within the context of inmemory systems that would help improve overall throughput. The general view is that in-memory systems substantially outperform disk-based systems. We question this assumption and examine how a modified variation of access invariance that we call enhanced memory access, (EMA) can be used to allow very high levels of concurrency in the pre-fetching of data in disk-based systems. We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems. This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number of processors and their speeds. The results of the experiments conducted clearly substantiate that when used in conjunction with all concurrency control mechanisms, EMA can increase the throughput of disk-based systems to levels quite close to those achieved by in-memory system. The promising results of this work show that enhanced disk-based systems facilitate in improving hybrid data management within the broader context of in-memory systems.

Keywords: Concurrency control, disk-based databases, inmemory systems, enhanced memory access (EMA).

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Authors: Bala Dhandayuthapani Veerasamy

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Parallel programming models exist as an abstraction of hardware and memory architectures. There are several parallel programming models in commonly use; they are shared memory model, thread model, message passing model, data parallel model, hybrid model, Flynn-s models, embarrassingly parallel computations model, pipelined computations model. These models are not specific to a particular type of machine or memory architecture. This paper expresses the model program for concurrent approach to data parallel model through java programming.

Keywords: Concurrent, Data Parallel, JDK, Parallel, Thread

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Authors: Diptoshi Roy, G. Sreevidya Varma, S. Asokan, Chandasree Das

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Germanium Telluride based quaternary thin film switching devices with composition Ge₁₅In₅Te₅₆Ag_24, have been deposited in sandwich geometry on glass substrate with aluminum as top and bottom electrodes. The bulk glassy form of the said composition is prepared by melt quenching technique. In this technique, appropriate quantity of elements with high purity are taken in a quartz ampoule and sealed under a vacuum of 10^-5 mbar. Then, it is allowed to rotate in a horizontal rotary furnace for 36 hours to ensure homogeneity of the melt. After that, the ampoule is quenched into a mixture of ice - water and NaOH to get the bulk ingot of the sample. The sample is then coated on a glass substrate using flash evaporation technique at a vacuum level of 10^-6 mbar. The XRD report reveals the amorphous nature of the thin film sample and Energy - Dispersive X-ray Analysis (EDAX) confirms that the film retains the same chemical composition as that of the base sample. Electrical switching behavior of the device is studied with the help of Keithley (2410^c) source-measure unit interfaced with Lab VIEW 7 (National Instruments). Switching studies, mainly SET (changing the state of the material from amorphous to crystalline) operation is conducted on the thin film form of the sample. This device is found to manifest memory switching as the device remains 'ON' even after the removal of the electric field. Also it is found that amorphous Ge₁₅In₅Te₅₆Ag₂₄ thin film unveils clean memory type of electrical switching behavior which can be justified by the absence of fluctuation in the I-V characteristics. The I-V characteristic also reveals that the switching is faster in this sample as no data points could be seen in the negative resistance region during the transition to on state and this leads to the conclusion of fast phase change during SET process. Scanning Electron Microscopy (SEM) studies are performed on the chosen sample to study the structural changes at the time of switching. SEM studies on the switched Ge₁₅In₅Te₅₆Ag₂₄ sample has shown some morphological changes at the place of switching wherein it can be explained that a conducting crystalline channel is formed in the device when the device switches from high resistance to low resistance state. From these studies it can be concluded that the material may find its application in fast switching Non-Volatile Phase Change Memory (PCM) Devices.

Keywords: Chalcogenides, vapor deposition, electrical switching, PCM.

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Authors: T. Ahmed, Z. Butt, M. Ali, S. Attiq, M. Ali

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A series of Ti based shape memory alloys with composition of Ti50Ni49Cr1, Ti50Ni47Cr3 and Ti50Ni45Cr5 were developed by vacuum arc-melting under a purified argon atmosphere. The histometric and corrosion evaluation of Ti-Ni-Cr shape memory alloys have been considered in this research work. The alloys were developed by vacuum arc melting and implanted subcutaneously in rabbits for 4, 8 and 12 weeks. Metallic implants were embedded in order to determine the outcome of implantation on histometric and corrosion evaluation of Ti-Ni-Cr metallic strips. Encapsulating membrane formation around the alloys was minimal in the case of all materials. After histomorphometric analyses it was possible to demonstrate that there were no statistically significant differences between the materials. Corrosion rate was also determined in this study which is within acceptable range. The results showed the Ti- Ni-Cr alloy was neither cytotoxic, nor have any systemic reaction on living system in any of the test performed. Implantation shows good compatibility and a potential of being used directly in vivo system.

Keywords: Shape memory alloy, Ti-Ni-Fe, histomorphometric, corrosion.

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Authors: R. Chalal, A. R. Ghomari

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Preparation and negotiation of innovative and future projects can be characterized as a strategic-type decision situation, involving many uncertainties and an unpredictable environment. We will focus in this paper on the bidding process. It includes cooperative and strategic decisions. Our approach for bidding process knowledge capitalization is aimed at information management in project-oriented organizations, based on the MUSIC (Management and Use of Co-operative Information Systems) model. We will show how to capitalize the company strategic knowledge and also how to organize the corporate memory. The result of the adopted approach is improvement of corporate memory quality.

Keywords: Bidding process, corporate memory, Knowledge capitalization, knowledge acquisition, strategic decisions.

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Authors: Choulseung Hyun, Hunki Kwon, Jaeho Kim, Eujoon Byun, Jongmoo Choi, Donghee Lee, Sam H. Noh

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Most file systems overwrite modified file data and metadata in their original locations, while the Log-structured File System (LFS) dynamically relocates them to other locations. We design and implement the Evergreen file system that can select between overwriting or relocation for each block of a file or metadata. Therefore, the Evergreen file system can achieve superior write performance by sequentializing write requests (similar to LFS-style relocation) when space utilization is low and overwriting when utilization is high. Another challenging issue is identifying performance benefits of LFS-style relocation over overwriting on a newly introduced SSD (Solid State Drive) which has only Flash-memory chips and control circuits without mechanical parts. Our experimental results measured on a SSD show that relocation outperforms overwriting when space utilization is below 80% and vice versa.

Keywords: Evergreen File System, Overwrite, Relocation, Solid State Drive.

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Authors: Nawang Chhunid, Gagnesh Kumar

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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

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Authors: Maha Idrissi Aouad, Rene Schott, Olivier Zendra

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Reducing energy consumption of embedded systems requires careful memory management. It has been shown that Scratch- Pad Memories (SPMs) are low size, low cost, efficient (i.e. energy saving) data structures directly managed at the software level. In this paper, the focus is on heuristic methods for SPMs management. A method is efficient if the number of accesses to SPM is as large as possible and if all available space (i.e. bits) is used. A Tabu Search (TS) approach for memory management is proposed which is, to the best of our knowledge, a new original alternative to the best known existing heuristic (BEH). In fact, experimentations performed on benchmarks show that the Tabu Search method is as efficient as BEH (in terms of energy consumption) but BEH requires a sorting which can be computationally expensive for a large amount of data. TS is easy to implement and since no sorting is necessary, unlike BEH, the corresponding sorting time is saved. In addition to that, in a dynamic perspective where the maximum capacity of the SPM is not known in advance, the TS heuristic will perform better than BEH.

Keywords: Energy consumption, memory allocation management, optimization, tabu search heuristic.

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Authors: Chih-Wei Hsieh, Chau-Yi Chou, Sheng-HsiuKuo, Tsung-Che Tsai, I-Chen Wu

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This paper presents the benchmarking results and performance evaluation of differentclustersbuilt atthe National Center for High-Performance Computingin Taiwan. Performance of processor, memory subsystem andinterconnect is a critical factor in the overall performance of high performance computing platforms. The evaluation compares different system architecture and software platforms. Most supercomputer used HPL to benchmark their system performance, in accordance with the requirement of the TOP500 List. In this paper we consider system memory access factors that affect benchmark performance, such as processor and memory performance.We hope these works will provide useful information for future development and construct cluster system.

Keywords: Performance Evaluation, Benchmarking and High-Performance Computing

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Authors: M. E. Marwan, A. R. Madar, N. Fuad

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Mobile learning (m-learning) is a new method in teaching and learning process which combines technology of mobile device with learning materials. It can enhance student's engagement in learning activities and facilitate them to access the learning materials at anytime and anywhere. In Kolej Poly-Tech Mara (KPTM), this method is seen as an important effort in teaching practice and to improve student learning performance. The aim of this paper is to discuss the development of m-learning application called Mobile EEF Learning System (MEEFLS) to be implemented for Electric and Electronic Fundamentals course using Flash, XML (Extensible Markup Language) and J2ME (Java 2 micro edition). System Development Life Cycle (SDLC) was used as an application development approach. It has three modules in this application such as notes or course material, exercises and video. MEELFS development is seen as a tool or a pilot test for m-learning in KPTM.

Keywords: Flash, mobile device, mobile learning, teaching and learning, SDLC, XML.

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Authors: Rana M. Zeina, Laila AL-Ayadhi, Shahid Bashir

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The association between sensory problems and cognitive abilities has been studied in individuals with Autism Spectrum Disorders (ASDs). In this study, we used a Neuropsychological Test to evaluate memory and attention in ASDs children with sensory problems compared to the ASDs children without sensory problems. Four visual memory tests of Cambridge Neuropsychological Test Automated Battery (CANTAB) including Big/little circle (BLC), Simple Reaction Time (SRT) Intra /Extra dimensional set shift (IED), Spatial recognition memory (SRM), were administered to 14 ASDs children with sensory problems compared to 13 ASDs without sensory problems aged 3 to 12 with IQ of above 70. ASDs individuals with sensory problems performed worse than the ASDs group without sensory problems on comprehension, learning, reversal and simple reaction time tasks, and no significant difference between the two groups was recorded in terms of the visual memory and visual comprehension tasks. The findings of this study suggest that ASDs children with sensory problems are facing deficits in learning, comprehension, reversal, and speed of response to a stimulus.

Keywords: Visual memory, Attention, Autism Spectrum Disorders (ASDs).

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Authors: Mackenzie Leake, Liyu Xia, Kamil Rocki, Wayne Imaino

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In the Hierarchical Temporal Memory (HTM) paradigm the effect of overlap between inputs on the activation of columns in the spatial pooler is studied. Numerical results suggest that similar inputs are represented by similar sets of columns and dissimilar inputs are represented by dissimilar sets of columns. It is shown that the spatial pooler produces these results under certain conditions for the connectivity and proximal thresholds. Following the discussion of the initialization of parameters for the thresholds, corresponding qualitative arguments about the learning dynamics of the spatial pooler are discussed.

Keywords: Hierarchical Temporal Memory, HTM, Learning Algorithms, Machine Learning, Spatial Pooler.

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Authors: B. B. Weng, Z. Fang, Z. X. Chen, X. P. Wang, G. Q. Lo, D. L. Kwong

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Resistive Random Access Memory (RRAM) had received great amount of attention from various research efforts in recent years, owing to its promising performance as a next generation memory device. In this paper, samples based on TiN/HfO_x/Pt stack were prepared and its electrical switching behaviors were characterized and discussed in brief.

Keywords: HfOx, resistive switching, RRAM.

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Authors: Amani Jaber-Awida

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This study examines two bilingual phenomena in the narratives of Arabic Hebrew and Hebrew-English bilingual adults in Israel: CO memories and code-switching (CS). The study examined these phenomena in the context of autobiographical memory, using a cue word technique. Student experimenters held two sessions in the homes of the participants. In separate language sessions, the participant was asked to look first at each of 16 cue words and then to state a concrete memory. After stating the memory, participants reported whether their memories were in the same language of the experiment session or different. Memories were classified as ‘Crossovers’ (CO) or ‘Same Language’ (SL) according to participants' self-reports. Participants were also required to elaborate about the setting, interlocutors and other languages involved in the specific memory. Beyond replicating the procedure of cuing technique, one memory from a specific lifespan period was chosen per participant, and the participant was required to provide further details about it. For the more detailed memories, CS count was conducted. Both bilingual groups confirmed the Reminiscence Bump phenomenon, retrieving more memories in the 10-30 age period. CO memories prevailed in second language sessions (L2). Same language memories were more abundant in first language sessions (L1). Higher CS frequency was found in L2 sessions. Finally, as predicted, 'individual' CS was prevalent in L2 sessions, but 'community-based' CS was not higher in L1 sessions. The two bilingual measures in this study, crossovers, and CS came from different research traditions, the former from an experimental paradigm in the psychology of autobiographical memory based on self-reported judgments, the latter a behavioral measure from linguistics. This merger of approaches offers new insight into the field of bilingual autobiographical memory. In addition, the study attempted to shed light on the investigation of motivations for CS, beginning with Walters’ SPPL Model and concluding with a distinction between ‘community-based’ and individual motivations.

Keywords: Autobiographical memory, code-switching, crossover memories, reminiscence bump.

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Authors: Danilo López, Nelson Vera, Luis Pedraza

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This paper analyzes fundamental ideas and concepts related to neural networks, which provide the reader a theoretical explanation of Long Short-Term Memory (LSTM) networks operation classified as Deep Learning Systems, and to explicitly present the mathematical development of Backward Pass equations of the LSTM network model. This mathematical modeling associated with software development will provide the necessary tools to develop an intelligent system capable of predicting the behavior of licensed users in wireless cognitive radio networks.

Keywords: Neural networks, multilayer perceptron, long short-term memory, recurrent neuronal network, mathematical analysis.

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Authors: Rachel Hurdley, Jane Hopkinson

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This article is based on observation of a cross-disciplinary, cross-institutional team that worked on an intervention called ‘Memory Mate’ for use in a UK Cancer Centre. This aimed to improve treatment outcomes for patients who had comorbid dementia or other memory impairment. Comorbid patients present ambiguous, spoiled identities, problematising the boundaries of health specialisms and frames of understanding. Memory Mate is theorised as a boundary object facilitating service transformation by changing relations between oncology and mental health care practice. It crosses the boundaries between oncology and mental health. Its introduction signifies an important step in reconfiguring relations between the specialisms. As a boundary object, it contains parallel, even contesting worlds, with potential to enable an eventual synthesis of the double stigma of cancer and dementia. Memory Mate comprises physical things, such as an animation, but its principal value is in the interaction it initiates across disciplines and services. It supports evolution of practices to address a newly emergent challenge for health service provision, namely the cancer patient with comorbid dementia/cognitive impairment. Getting clinicians from different disciplines working together on a practical solution generates a dialogue that can shift professional identity and change the culture of practice.

Keywords: Boundary object, cancer, dementia, interdisciplinary teams.

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Authors: Josu Arteche, Jesus Orbe

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The log periodogram regression is widely used in empirical applications because of its simplicity, since only a least squares regression is required to estimate the memory parameter, d, its good asymptotic properties and its robustness to misspecification of the short term behavior of the series. However, the asymptotic distribution is a poor approximation of the (unknown) finite sample distribution if the sample size is small. Here the finite sample performance of different nonparametric residual bootstrap procedures is analyzed when applied to construct confidence intervals. In particular, in addition to the basic residual bootstrap, the local and block bootstrap that might adequately replicate the structure that may arise in the errors of the regression are considered when the series shows weak dependence in addition to the long memory component. Bias correcting bootstrap to adjust the bias caused by that structure is also considered. Finally, the performance of the bootstrap in log periodogram regression based confidence intervals is assessed in different type of models and how its performance changes as sample size increases.

Keywords: bootstrap, confidence interval, log periodogram regression, long memory.

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Authors: Vishnu Pratap Singh Kirar

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Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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Authors: B. B. Weng, Z. Fang, Z. X. Chen, X. P. Wang, G. Q. Lo, D. L. Kwong

Abstract:

HfOx based Resistive Random Access Memory (RRAM) is one of the most widely studied material stack due to its promising performances as an emerging memory technology. In this work, we systematically investigated the effect of metal capping layer by preparing sample devices with varying thickness of Ti cap and comparing their operating parameters with the help of an Agilent-B1500A analyzer.

Keywords: HfOx, resistive switching, RRAM, metal capping.

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