Search results for: full-wave fully gate cross-coupled rectifiers CMOS rectifier

Authors: Devin Atkin, Orly Yadid-Pecht

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The continual demands for increasing resolution and dynamic range in CMOS image sensors have resulted in exponential increases in the amount of data that needs to be read out of an image sensor, and existing readouts cannot keep up with this demand. Interesting approaches such as sparse and burst readouts have been proposed and show promise, but at considerable trade-offs in other specifications. To this end, we have begun designing and evaluating various new readout topologies centered around an attempt to parallelize the sensor readout. In this paper, we have designed, simulated, and started testing a new light-controlled oscillator topology with dual column and row readouts. We expect the parallel readout structure to offer greater speed and alleviate the trade-off typical in this topology, where slow pixels present a major framerate bottleneck.

Keywords: CMOS image sensors, high-speed capture, wide dynamic range, light controlled oscillator

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Authors: Yiqiang Ni, Xuanlong Chen, Enliang Li, Linting Zheng, Shizheng Yang

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Bipolar ICs are playing an important role in military applications, mainly used in logic gates, such as inverter and NAND gate. The defect of metal break located on the step is one of the main failure mechanisms of bipolar ICs, resulting in open-circuit or functional failure. In this situation, general failure localization methods like optical beam-induced resistance change (OBIRCH) and photon emission microscopy (PEM) might not be fully effective. However, active voltage contrast (AVC) can be used as a voltage probe, which may pinpoint the incorrect potential and thus locate the failure position. Two case studies will be present in this paper on how to implement AVC for failure localization, and the detailed failure mechanism will be discussed.

Keywords: bipolar IC, failure localization, metal break, open failure, voltage contrast

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Authors: Mert Kıranç, Ekrem Duman, Murat Özbilen

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In order to achieve new product development (NPD) activities on time and within budgetary constraints, the NPD managers need a well-designed methodology. This study intends to create an integrated project management methodology for the ones who focus on new product development projects. In the scope of the study, four different management systems are combined. These systems are called as 'Schedule-oriented Stage-Gate Method, Risk Management, Change Management and Earned Value Management'. New product development term is quite common in many different industries such as defense industry, construction, health care/dental, higher education, fast moving consumer goods, white goods, electronic devices, marketing and advertising and software development. All product manufacturers run against each other’s for introducing a new product to the market. In order to achieve to produce a more competitive product in the market, an optimum project management methodology is chosen, and this methodology is adapted to company culture. The right methodology helps the company to present perfect product to the customers at the right time. The benefits of proposed methodology are discussed as an application by a company. As a result, how the integrated methodology improves the efficiency and how it achieves the success of the project are unfolded.

Keywords: project, project management, management methodology, new product development, risk management, change management, earned value, stage-gate

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Authors: Suruchi Saini, Hitender Kumar Tyagi

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With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: Farhan Beg

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A space vector based pulse width modulation control technique for the three-phase PWM converter is proposed in this paper. The proposed control scheme is based on a synchronous reference frame model. High performance and efficiency is obtained with regards to the DC bus voltage and the power factor considerations of the PWM rectifier thus leading to low losses. MATLAB/SIMULINK are used as a platform for the simulations and a SIMULINK model is presented in the paper. The results show that the proposed model demonstrates better performance and properties compared to the traditional SPWM method and the method improves the dynamic performance of the closed loop drastically. For the space vector based pulse width modulation, sine signal is the reference waveform and triangle waveform is the carrier waveform. When the value of sine signal is larger than triangle signal, the pulse will start producing to high; and then when the triangular signals higher than sine signal, the pulse will come to low. SPWM output will change by changing the value of the modulation index and frequency used in this system to produce more pulse width. When more pulse width is produced, the output voltage will have lower harmonics contents and the resolution will increase.

Keywords: power factor, SVPWM, PWM rectifier, SPWM

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Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

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This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

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Authors: Ursula D. C. Resende, Fabiano S. Bicalho, Sandro T. M. Gonçalves

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The growing demand for cheap and clean energy sources have been motivated by the study and development of distinct technologies and devices able to provide different amounts of energy. In order to supply energy for small loads, the energy from the electromagnetic spectrum can be harvested. This possibility is particularly interesting because this kind of energy is constantly available in the environment and the number of radiofrequency sources is permanently increasing, due to advances in telecommunications services. A rectenna, which is a combination of an antenna and a rectifier circuit, is an equipment that can efficiently perform the electromagnetic energy harvesting. However, since the amount of electromagnetic energy available in the environment is very small, limited values of power can be harvested by the rectenna. Therefore, several technical strategies have been investigated in order to increase this amount of power. In this work, a metamaterial electromagnetic lens is used to improve the electromagnetic energy harvesting. The rectenna investigated was designed and optimized to charge a Li-Ion battery using the electromagnetic energy from an internet Wi-Fi commercial router model TL-WR841HP operating in 2.45 GHz with maximal output power equal to 18 dBm. The rectenna consists of a high directive antenna, a double voltage rectifier circuit and a metamaterial lens. The printed antenna, constituted of two rectangular radiator elements, was projected and optimized by using the Computer Simulation Software (CST) in order to obtain high directivities and values of S11 parameter below -10 dB in 2.45 GHz. The antenna was printed over a double-sided copper fiberglass substrate, FR4, with characterized relative electric permittivity εr = 4.3 and tangent of losses δ = 0.01. The rectifier circuit, which incorporates a circuit for impedance matching and uses the Schottky diode HSMS-2852, was projected and optimized by using Advanced Design Software (ADS) and built over the same FR4 substrate. The metamaterial cell is composed of two Square Split Ring Resonator (S-SRR) and a thin wire in order to operate with negative values of εr and relative magnetic permeability in 2.45 GHz. In order to evaluate the performance of the purposed rectenna two experimental charging tests were performed, one without and other with the metamaterial lens. The result obtained demonstrate that the electromagnetic lens was able to significantly increase the levels of electric current delivered to the battery, approximately 44%.

Keywords: electromagnetic energy harvesting, electromagnetic lens, metamaterial, rectenna

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Authors: M. Kessi

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We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

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Authors: Gashin Shahsavari, Gilles Arnaud-Fassetta, Alberto Campisano, Roberto Bertilotti, Fabien Riou

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Sewer deposits have been identified as a major cause of dysfunctions in combined sewer systems regarding sewer management, which induces different negative consequents resulting in poor hydraulic conveyance, environmental damages as well as worker’s health. In order to overcome the problematics of sedimentation, flushing has been considered as the most operative and cost-effective way to minimize the sediments impacts and prevent such challenges. Flushing, by prompting turbulent wave effects, can modify the bed form depending on the hydraulic properties and geometrical characteristics of the conduit. So far, the dynamics of the bed-load during high-flow events in combined sewer systems as a complex environment is not well understood, mostly due to lack of measuring devices capable to work in the “hostile” in combined sewer system correctly. In this regards, a one-episode flushing issue from an opening gate valve with weir function was carried out in a trunk sewer in Paris to understanding its cleansing efficiency on the sediments (thickness: 0-30 cm). During more than 1h of flushing within 5 m distance in downstream of this flushing device, a maximum flowrate and a maximum level of water have been recorded at 5 m in downstream of the gate as 4.1 m3/s and 2.1 m respectively. This paper is aimed to evaluate the efficiency of this type of gate for around 1.1 km (from the point -50 m to +1050 m in downstream from the gate) by (i) determining bed grain-size distribution and sediments evolution through the sewer channel, as well as their organic matter content, and (ii) identifying sections that exhibit more changes in their texture after the flush. For the first one, two series of sampling were taken from the sewer length and then analyzed in laboratory, one before flushing and second after, at same points among the sewer channel. Hence, a non-intrusive sampling instrument has undertaken to extract the sediments smaller than the fine gravels. The comparison between sediments texture after the flush operation and the initial state, revealed the most modified zones by the flush effect, regarding the sewer invert slope and hydraulic parameters in the zone up to 400 m from the gate. At this distance, despite the increase of sediment grain-size rages, D50 (median grain-size) varies between 0.6 mm and 1.1 mm compared to 0.8 mm and 10 mm before and after flushing, respectively. Overall, regarding the sewer channel invert slope, results indicate that grains smaller than sands (< 2 mm) are more transported to downstream along about 400 m from the gate: in average 69% before against 38% after the flush with more dispersion of grain-sizes distributions. Furthermore, high effect of the channel bed irregularities on the bed material evolution has been observed after the flush.

Keywords: bed-load evolution, combined sewer systems, flushing efficiency, sediments transport

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Authors: A. boursali, A. Guen Bouazza, M. Khaouani, Z. Kourdi, B. Bouazza

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This paper presents the design, development and characterization of the devices simulation for X-Band Radar applications. The effect of an InAlN/GaN structure on the RF performance High Electron Mobility Transistor (HEMT) device. Systematic investigations on the small signal as well as power performance as functions of the drain biases are presented. Were improved for X-band applications. The Power Added Efficiency (PAE) was achieved over 23% for X-band. The developed devices combine two InAlN/GaN HEMTs of 30nm gate periphery and exhibited the output power of over 50W. An InAlN/GaN HEMT with 30nm gate periphery was developed and exhibited the output power of over 120W.

Keywords: InAlN/GaN, HEMT, RF analyses, PAE, X-Band, radar

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Authors: H. Bentarzi, A. Zitouni

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The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: amplifier class D, field-programmable gate array (FPGA), protective relay, tester

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Authors: A. Anitha, M. Aishwariya

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The realization of truly ubiquitous wireless sensor networks (WSN) demands Ultra-low power wireless communication capability. Because the radio transceiver in a wireless sensor node consumes more power when compared to the computation part it is necessary to reduce the power consumption. Hence, a low power transceiver is designed and implemented in a 120 nm CMOS technology for wireless sensor nodes. The power consumption of the transceiver is reduced still by maintaining the sensitivity. The transceiver designed combines the blocks including differential oscillator, mixer, envelope detector, power amplifiers, and LNA. RF signal modulation and demodulation is carried by On-Off keying method at 2.4 GHz which is said as ISM band. The transmitter demonstrates an output power of 2.075 mW while consuming a supply voltage of range 1.2 V-5.0 V. Here the comparison of LNA and power amplifier is done to obtain an amplifier which produces a high gain of 1.608 dB at receiver which is suitable to produce a desired sensitivity. The multistage RF amplifier is used to improve the gain at the receiver side. The power dissipation of the circuit is in the range of 0.183-0.323 mW. The receiver achieves a sensitivity of about -95 dBm with data rate of 1 Mbps.

Keywords: CMOS, envelope detector, ISM band, LNA, low power electronics, PA, wireless transceiver

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Authors: A. N. Moulai Khatir

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SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number.

Keywords: SOI, finFET, corner effect, dual-gate, tri-gate, BOX, multi-finFET

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Authors: Muhammad Ahsan

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The effective decommissioning of oil and gas fields and related assets is one of the most important challenges facing the oil and gas industry today and in the future. Decommissioning decisions can no longer be avoided by the operators and the industry as a whole. Decommissioning yields no return on investment and carries significant regulatory liabilities. The main objective of this paper is to provide an approach and mechanism for the estimation of emissions associated with decommissioning of Oil and Gas fields. The model uses gate to gate approach and considers field life from development phase up to asset end life. The model incorporates decommissioning processes which includes; well plugging, plant dismantling, wellhead, and pipeline dismantling, cutting and temporary fabrication, new manufacturing from raw material and recycling of metals. The results of the GHG emissions during decommissioning phase are 2.31x10-2 Kg CO2 Eq. per Mcf of the produced natural gas. Well plug and abandonment evolved to be the most GHG emitting activity with 84.7% of total field decommissioning operational emissions.

Keywords: LCA (life cycle analysis), gas field, decommissioning, emissions

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Authors: Alok Kumar Kamal, Vinod Kumar

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The trench gate MOSFET has shown itself as the most appropriate power device for low to medium voltage power applications due to its lowest possible ON resistance among all power semiconductor devices. In this research work a double-epilayer PSGT structure using a thin layer of N+ polysilicon as gate material. The total ON-state resistance (RON) of UMOSFET can be reduced by optimizing the epilayer thickness. The optimized structure of Double-Epilayer exhibits a 25.8% reduction in the ON-state resistance at Vgs=5V and improving the switching characteristics by reducing the Reverse transfer capacitance (Cgd) by 7.4%.

Keywords: Miller-capacitance, double-Epilayer;switching characteristics, power trench MOSFET (U-MOSFET), on-state resistance, blocking voltage

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Authors: Alaa Abdullah Altaee

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This paper presents an adaptive decision feedback equalizer (ADFE) for multi-Gbps serial links utilizing a fix-step error signal extracted from cross-points of received data symbols. The extracted signal is generated based on violation of received data symbols with minimum detection requirements at the clock and data recovery (CDR) stage. The iterations of the adaptation process search for the optimum feedback tap coefficients to maximize the data eye-opening and minimize the adaptation convergence time. The effectiveness of the proposed architecture is validated using the simulation results of a serial link designed in an IBM 130 nm 1.2V CMOS technology. The data link with variable channel lengths is analyzed using Spectre from Cadence Design Systems with BSIM4 device models.

Keywords: adaptive DFE, CMOS equalizer, error detection, serial links, timing jitter, wire-line communication

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Authors: Yueguang Gao, Qi Huang, Shunshan Feng

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In order to study the process and characteristic of the fragments in the warhead with one end cap under full constraint condition, we established a cylindrical casing with two end caps which one of which was fully constrained using the simulation analysis. The result showed that the fragmentation of cylindrical casing with one end full constrained has its own characteristic. The Mach stem was generated when the detonation wave propagated to the fully constrained end cap under the condition of one end detonation, working on unreactive explosives and causing the nearby fragment subjected to nearly 2.5 times the normal pressure to obtain a higher speed. The cylindrical casing first ruptured at the contact surface with the fully constrained end, and then at the end cover of the initiating end, and then the rupture extends to the whole cylindrical casing. The detonation products started to leak out from the rupture. Driving fragments to fly and forming two dense flying areas. The analysis of this paper can provide a reference for the optimal design of this kind of warhead.

Keywords: fragment, cylindrical casing, detonation waves, numerical simulation

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Authors: Kim Jin Sup

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This paper presents a vertical hall effect device using current-mode. Among different geometries that have been studied and simulated using COMSOL Multiphysics, optimized cross-shaped model displayed the best sensitivity. The cross-shaped model emerged as the optimum plate to fit the lowest noise and residual offset and the best sensitivity. The symmetrical cross-shaped hall plate is widely used because of its high sensitivity and immunity to alignment tolerances resulting from the fabrication process. The hall effect device has been designed using a 0.18-μm CMOS technology. The simulation uses the nominal bias current of 12μA. The applied magnetic field is from 0 mT to 20 mT. Simulation results achieved in COMSOL and validated with respect to the electrical behavior of equivalent circuit for Cadence. Simulation results of the one structure over the 13 available samples shows for the best geometry a current-mode sensitivity of 6.6 %/T at 20mT. Acknowledgment: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device).

Keywords: vertical hall device, current-mode, crossed-shaped model, CMOS technology

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Authors: Seyed Abdol Mohammad Rezavand, Mohammad Nikbakhsh

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Withdrawal resistance of screws driven into HDPE/Sugarcane Bagasse injection molded parts was investigated. After chemical treatment and drying, SCB was pre-mixed with HDPE using twin extruder. The resulting granules are used in producing samples in injection molding machine. SCB with the quantity of %10, %20, and %30 was used. By using a suitable fixture, screw heads can take with tensile test machine grips. Parts with screws in the center and edge were fasten together. Then, withdrawal resistance was measured with tensile test machine. Injection gate is at the one edge of the part. The results show that by increasing SCB content in composite, the withdrawal resistance is decreased. Furthermore, the withdrawal resistance at the edges (near injection gate and the end of the filling path of mold cavity) is more than that of the center.

Keywords: polyethylene, sugarcane bagasse, wood plastic, screw, withdrawal resistance

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, GaInP

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Authors: Victor Onomza Waziri, John K. Alhassan, Idris Ismaila, Noel Dogonyara

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This paper describes the problem of building secure computational services for encrypted information in the Cloud. Computing without decrypting the encrypted data; therefore, it meets the yearning of computational encryption algorithmic aspiration model that could enhance the security of big data for privacy or confidentiality, availability and integrity of the data and user’s security. The cryptographic model applied for the computational process of the encrypted data is the Fully Homomorphic Encryption Scheme. We contribute a theoretical presentations in a high-level computational processes that are based on number theory that is derivable from abstract algebra which can easily be integrated and leveraged in the Cloud computing interface with detail theoretic mathematical concepts to the fully homomorphic encryption models. This contribution enhances the full implementation of big data analytics based on cryptographic security algorithm.

Keywords: big data analytics, security, privacy, bootstrapping, Fully Homomorphic Encryption Scheme

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Authors: Christos Konstantopoulos, Thomas Ussmueller

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Digital low drop-out regulators, in contrast to analog counterparts, provide an architecture of sub-1 V regulation with low power consumption, high power efficiency, and system integration. Towards an optimized integration in the ultra-low-power system-on-chip Internet of Things architecture that is operated through a radio frequency energy harvesting scheme, the D-LDO regulator should constitute the main regulator that operates the master-clock and rest loads of the SoC. In this context, we present a D-LDO with linear search coarse regulation and asynchronous fine regulation, which incorporates an in-regulator clock generation unit that provides an autonomous, self-start-up, and power-efficient D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the frequency, this work presents a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of coarse regulation frequency. The design is implemented in a 55-nm Global Foundries CMOS process. With the purpose to validate the self-start-up capability of the presented D-LDO in the presence of ultra-low input power, an on-chip test-bench with an RF rectifier is implemented as well, which provides the RF to DC operation and feeds the D-LDO. Power efficiency and load regulation curves of the D-LDO are presented as extracted from the RF to regulated DC operation. The D-LDO regulator presents 83.6 % power efficiency during the RF to DC operation with a 3.65 uA load current and voltage regulator referred input power of -27 dBm. It succeeds 486 nA maximum quiescent current with CL 75 pF, the maximum current efficiency of 99.2%, and 1.16x power efficiency improvement compared to analog voltage regulator counterpart oriented to SoC IoT loads. Complementary, the transient performance of the D-LDO is evaluated under the transient droop test, and the achieved figure-of-merit is compared with state-of-art implementations.

Keywords: D-LDO, Internet of Things, RF energy harvesting, voltage regulators

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Authors: Lalit Ahuja, Nancy Das, Yashas Shetty

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LED lighting has been increasingly adopted for vehicles in both domestic and foreign automotive markets. Although this miniaturized technology gives the best light output, low energy consumption, and cost-efficient solutions for driving, the same is the need of the hour. In this paper, we present a methodology for driving the highest class two-wheeler headlamp with regulator and rectifier (RR) output. Unlike usual LED headlamps, which are driven by a battery, regulator, and rectifier (RR) driven, a low-cost and highly efficient LED Driver Module (LDM) is proposed. The positive half of magneto output is regulated and used to charge batteries used for various peripherals. While conventionally, the negative half was used for operating bulb-based exterior lamps. But with advancements in LED-based headlamps, which are driven by a battery, this negative half pulse remained unused in most of the vehicles. Our system uses negative half-wave rectified DC output from RR to provide constant light output at all RPMs of the vehicle. With the negative rectified DC output of RR, we have the advantage of pulsating DC input which periodically goes to zero, thus helping us to generate a constant DC output equivalent to the required LED load, and with a change in RPM, additional active thermal bypass circuit help us to maintain the efficiency and thermal rise. The methodology uses the negative half wave output of the RR along with a linear constant current driver with significantly higher efficiency. Although RR output has varied frequency and duty cycles at different engine RPMs, the driver is designed such that it provides constant current to LEDs with minimal ripple. In LED Headlamps, a DC-DC switching regulator is usually used, which is usually bulky. But with linear regulators, we’re eliminating bulky components and improving the form factor. Hence, this is both cost-efficient and compact. Presently, output ripple-free amplitude drivers with fewer components and less complexity are limited to lower-power LED Lamps. The focus of current high-efficiency research is often on high LED power applications. This paper presents a method of driving LED load at both High Beam and Low Beam using the negative half wave rectified pulsating DC from RR with minimum components, maintaining high efficiency within the thermal limitations. Linear regulators are significantly inefficient, with efficiencies typically about 40% and reaching as low as 14%. This leads to poor thermal performance. Although they don’t require complex and bulky circuitry, powering high-power devices is difficult to realise with the same. But with the input being negative half wave rectified pulsating DC, this efficiency can be improved as this helps us to generate constant DC output equivalent to LED load minimising the voltage drop on the linear regulator. Hence, losses are significantly reduced, and efficiency as high as 75% is achieved. With a change in RPM, DC voltage increases, which can be managed by active thermal bypass circuitry, thus resulting in better thermal performance. Hence, the use of bulky and expensive heat sinks can be avoided. Hence, the methodology to utilize the unused negative pulsating DC output of RR to optimize the utilization of RR output power and provide a cost-efficient solution as compared to costly DC-DC drivers.

Keywords: class D LED headlamp, regulator and rectifier, pulsating DC, low cost and highly efficient, LED driver module

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: S. Maddi Muhammed, Paul Davis, John Geraghty, Mabruk Derbesh

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This study discusses the probability of using electronic management in higher education institutions in Libya. This could be as sampled by creating an electronic gate at the faculties of Engineering and Computing "Information Technology" at Zaytuna University or any other university in Libya. As we all know, the competitive advantage amongst universities is based on their ability to use information technology efficiently and broadly. Universities today value information technology as part of the quality control and assurance and a ranking criterion for a range of services including e-learning and e-Registration. This could be done by developing email systems, electronic or virtual libraries, electronic cards, and other services provided to all students, faculty or staff. This paper discusses a range of important topics that explain how to apply the gate "E" with the faculties at Zaytuna University, Bani Walid colleges in Libya.

Keywords: e-management, educational institutions (EI), Libya, Zaytuna, information technology

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Authors: Sachin Kamble, Shradha Gawankar

Abstract:

This paper presents the findings of successful implementation of Business Process Reengineering (BPR) of cement dispatch activities in a cement manufacturing plant located in India. Simulation model was developed for the purpose of identifying and analyzing the areas for improvement. The company was facing a problem of low throughput rate and subsequent forced stoppages of the plant leading to a high production loss of 15000MT per month. It was found from the study that the present systems and procedures related to the in-plant logistics plant required significant changes. The major recommendations included process improvement at the entry gate, reducing the cycle time at the security gate and installation of an additional weigh bridge. This paper demonstrates how BPR can be implemented for improving the in-plant logistics process. Various recommendations helped the plant to increase its throughput by 14%.

Keywords: in-plant logistics, cement logistics, simulation modelling, business process re-engineering, supply chain management

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Authors: Se-Mi Lim, Won-Jae Jung, Jin-Sup Kim, Jun-Seok Park, Hyung-Il Chae

Abstract:

This paper presents a current-mode vertical hall device (VHD) structure using metal layers in a CMOS process. The proposed metal layer based vertical hall device (MLVHD) utilizes vertical connection among metal layers (from M1 to the top metal) to facilitate hall effect. The vertical metal structure unit flows a bias current Ibias from top to bottom, and an external magnetic field changes the current distribution by Lorentz force. The asymmetric current distribution can be detected by two differential-mode current outputs on each side at the bottom (M1), and each output sinks Ibias/2 ± Ihall. A single vertical metal structure generates only a small amount of hall effect of Ihall due to the short length from M1 to the top metal as well as the low conductivity of the metal, and a series connection between thousands of vertical structure units can solve the problem by providing NxIhall. The series connection between two units is another vertical metal structure flowing current in the opposite direction, and generates negative hall effect. To mitigate the negative hall effect from the series connection, the differential current outputs at the bottom (M1) from one unit merges on the top metal level of the other unit. The proposed MLVHD is simulated in a 3-dimensional model simulator in COMSOL Multiphysics, with 0.35 μm CMOS process parameters. The simulated MLVHD unit size is (W) 10 μm × (L) 6 μm × (D) 10 μm. In this paper, we use an MLVHD with 10 units; the overall hall device size is (W) 10 μm × (L)78 μm × (D) 10 μm. The COMSOL simulation result is as following: the maximum hall current is approximately 2 μA with a 12 μA bias current and 100mT magnetic field; This work was supported by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIP) (No.R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device).

Keywords: CMOS, vertical hall device, current mode, COMSOL

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Authors: Wei Zhang

Abstract:

With the rapid development of deep learning, neural network and deep learning algorithms play a significant role in various practical applications. Due to the high accuracy and good performance, Convolutional Neural Networks (CNNs) especially have become a research hot spot in the past few years. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses a significant challenge to construct a high-performance implementation of deep learning neural networks. Meanwhile, many of these application scenarios also have strict requirements on the performance and low-power consumption of hardware devices. Therefore, it is particularly critical to choose a moderate computing platform for hardware acceleration of CNNs. This article aimed to survey the recent advance in Field Programmable Gate Array (FPGA)-based acceleration of CNNs. Various designs and implementations of the accelerator based on FPGA under different devices and network models are overviewed, and the versions of Graphic Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs) are compared to present our own critical analysis and comments. Finally, we give a discussion on different perspectives of these acceleration and optimization methods on FPGA platforms to further explore the opportunities and challenges for future research. More helpfully, we give a prospect for future development of the FPGA-based accelerator.

Keywords: deep learning, field programmable gate array, FPGA, hardware accelerator, convolutional neural networks, CNN

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Authors: Parimalah Velo, Ahmad Zakaria

Abstract:

Introduction: Monte Carlo simulations of preclinical imaging systems allow opportunity to enable new research that could range from designing hardware up to discovery of new imaging application. The simulation system which could accurately model an imaging modality provides a platform for imaging developments that might be inconvenient in physical experiment systems due to the expense, unnecessary radiation exposures and technological difficulties. The aim of present study is to validate the Monte Carlo simulation of thyroid phantom imaging using Geant4-GATE for Siemen’s e-cam single head gamma camera. Upon the validation of the gamma camera simulation model by comparing physical characteristic such as energy resolution, spatial resolution, sensitivity, and dead time, the GATE simulation of thyroid phantom imaging is carried out. Methods: A thyroid phantom is defined geometrically which comprises of 2 lobes with 80mm in diameter, 1 hot spot, and 3 cold spots. This geometry accurately resembling the actual dimensions of thyroid phantom. A planar image of 500k counts with 128x128 matrix size was acquired using simulation model and in actual experimental setup. Upon image acquisition, quantitative image analysis was performed by investigating the total number of counts in image, the contrast of the image, radioactivity distributions on image and the dimension of hot spot. Algorithm for each quantification is described in detail. The difference in estimated and actual values for both simulation and experimental setup is analyzed for radioactivity distribution and dimension of hot spot. Results: The results show that the difference between contrast level of simulation image and experimental image is within 2%. The difference in the total count between simulation and actual study is 0.4%. The results of activity estimation show that the relative difference between estimated and actual activity for experimental and simulation is 4.62% and 3.03% respectively. The deviation in estimated diameter of hot spot for both simulation and experimental study are similar which is 0.5 pixel. In conclusion, the comparisons show good agreement between the simulation and experimental data.

Keywords: gamma camera, Geant4 application of tomographic emission (GATE), Monte Carlo, thyroid imaging

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Authors: P. Geetha, R. S. D. Wahida Banu

Abstract:

The crowning advances in Silicon based electronic technology have dominated the computation world for the past decades. The captivating performance of Si devices lies in sustainable scaling down of the physical dimensions, by that increasing device density and improved performance. But, the fundamental limitations due to physical, technological, economical, and manufacture features restrict further miniaturization of Si based devices. The pit falls are due to scaling down of the devices such as process variation, short channel effects, high leakage currents, and reliability concerns. To fix the above-said problems, it is needed either to follow a new concept that will manage the current hitches or to support the available concept with different materials. The new concept is to design spintronics, quantum computation or two terminal molecular devices. Otherwise, presently used well known three terminal devices can be modified with different materials that suits to address the scaling down difficulties. The first approach will occupy in the far future since it needs considerable effort; the second path is a bright light towards the travel. Modelling paves way to know not only the current-voltage characteristics but also the performance of new devices. So, it is desirable to model a new device of suitable gate control and project the its abilities towards capability of handling high current, high power, high frequency, short delay, and high velocity with excellent electronic and optical properties. Carbon nanotube became a thriving material to replace silicon in nano devices. A well-planned optimized utilization of the carbon material leads to many more advantages. The unique nature of this organic material allows the recent developments in almost all fields of applications from an automobile industry to medical science, especially in electronics field-on which the automation industry depends. More research works were being done in this area. This paper reviews the carbon nanotube field effect transistor with various gate configurations, number of channel element, CNT wall configurations and different modelling techniques.

Keywords: array of channels, carbon nanotube field effect transistor, double gate transistor, gate wrap around transistor, modelling, multi-walled CNT, single-walled CNT

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