Search results for: power trench MOSFET (U-MOSFET)

Authors: Alok Kumar Kamal, Vinod Kumar

Abstract:

The trench gate MOSFET has shown itself as the most appropriate power device for low to medium voltage power applications due to its lowest possible ON resistance among all power semiconductor devices. In this research work a double-epilayer PSGT structure using a thin layer of N+ polysilicon as gate material. The total ON-state resistance (RON) of UMOSFET can be reduced by optimizing the epilayer thickness. The optimized structure of Double-Epilayer exhibits a 25.8% reduction in the ON-state resistance at Vgs=5V and improving the switching characteristics by reducing the Reverse transfer capacitance (Cgd) by 7.4%.

Keywords: Miller-capacitance, double-Epilayer;switching characteristics, power trench MOSFET (U-MOSFET), on-state resistance, blocking voltage

Procedia PDF Downloads 24

Authors: Abdelghafour Galadi

Abstract:

In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: power MOSFET, drift layer, quasi-saturation effect, SPICE model

Procedia PDF Downloads 167

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

Procedia PDF Downloads 226

Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

Abstract:

In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

Procedia PDF Downloads 230

Authors: Petr Vaculik

Abstract:

The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber.

Keywords: SiC, Si, MOSFET, IGBT, SBD, RC snubber

Procedia PDF Downloads 442

Authors: Syakirin O. Yong, Nasrudin A. Rahim, Bilal M. Eid, Buray Tankut

Abstract:

The aim of this paper is to develop an ultra-fast gate driver for Silicon Carbide (SiC) based switching device applications such as AC/DC DC/AC converters. Wide bandgap semiconductors such as SiC switches are growing rapidly nowadays due to their numerous capabilities such as faster switching, higher power density and higher voltage level. Wide band-gap switches can work properly on high frequencies such 50-250 kHz which is very useful for many power electronic applications such as solar inverters. Increasing the frequency minimizes the output filter size and system complexity however, this causes huge spike between MOSFET’s drain and source leg which leads to the failure of MOSFET if the voltage rating is exceeded. This paper investigates and concludes the optimum design for a gate drive board for SiC MOSFET switches without causing spikes and noises.

Keywords: PV system, lithium-ion, charger, constant current, constant voltage, renewable energy

Procedia PDF Downloads 124

Authors: Fatma Soltani

Abstract:

In power electronics the DC-DC converters or choppers are now employed in large areas, particularly in the field of electricity generation by wind and solar energy conversion. Photovoltaic generators (GPV) can deliver maximum power for a point on the characteristic P = f (Vpv), called maximum power point (MPP), or climatic variations, entraiment fluctuation PPM. To remedy this problem is interposed between the generator and receiver a DC-DC converter. The converter is usually used a simple MOSFET chopper. However, the MOSFET can be applied in the field of low power when you need a high switching frequency but becomes highly dissipative when should block large voltages For PV generators medium and high power, the use of IGBT chopper is by far the most recommended. To reduce stress on semiconductor components using several choppers series connected in parallel is known as interleaved chopper. These choppers lead to rotas.

Keywords: converter DC-DC entrelaced

, photovoltaic generators, IGBT, optimisation

Procedia PDF Downloads 512

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Multi-gate SOI MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with a scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high -k dielectric materials as oxide layer at different places in MOSFET structures. One of the most important multi-gate structures is square GAA SOI MOSFET that is a strong candidate for the next generation nanoscale devices; show an even stronger control of short channel effects. In this paper, GAA SOI MOSFET structure with using high -k dielectrics materials Al2O3 (k~9), HfO2 (k~20), La2O3 (k~30) and metal gate TiN are simulated by using 3-D device simulator DevEdit and Atlas of SILVACO TCAD tools. Square GAA SOI MOSFET transistor with High-k HfO2 gate dielectrics and TiN metal gate exhibits significant improvements performances compared to Al2O3 and La2O3 dielectrics for the same structure. Simulation results of GAA SOI MOSFET transistor with HfO2 dielectric show the increase in saturation current and Ion/Ioff ratio while leakage current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, square GAA SOI MOSFET, high-k dielectric, Silvaco software

Procedia PDF Downloads 219

Authors: Dheeraj Sharma, Santosh Kumar Vishvakarma

Abstract:

We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product.

Keywords: Gate-All-Around MOSFET, GAA, output resistance, transconductance generation factor, intrinsic gain, cutoff frequency, fT

Procedia PDF Downloads 361

Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

Procedia PDF Downloads 477

Authors: Bentoutou Houari, Boutte Aissa, Belaidi El Yazid, Limam Lakhdar

Abstract:

The integration of a load switch with a DC/DC buck converter using LM2596 for power distribution in low-cost educational nanosatellites is a technique that aims to efficiently manage the power distribution system in these small spacecraft. The converter is based on the LM2596 regulator and designed to step down the input voltage of +16.8V to +12V, +5V, and +3.3V output, which are suitable for the nanosatellite's various subsystems. The load switch is based on MOSFET and is used to turn on or off the power supply to a particular load and protect the nanosatellite from power surges. A prototype of a +12V DC/DC buck converter with a high side load switch has been realized and tested, which meets our requirements and shows a good efficiency of 89%. In addition, the prototype features a capacitor between the source and gate of the MOSFET, which has effectively reduced the inrush current, demonstrating the effectiveness of this approach in reducing surges of current when the load is connected. The output current and voltage were measured at 0.7A and 11.89V, respectively, making this design suitable for use in low-cost educational nanosatellites.

Keywords: DC/DC buck converter, load switch, LM2596, electrical power subsystems, nanosatellite, inrush current

Procedia PDF Downloads 66

Authors: Azizi Cherifa, O. Benzaoui

Abstract:

The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

Procedia PDF Downloads 319

Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

Abstract:

According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling

Procedia PDF Downloads 496

Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

Abstract:

This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

Procedia PDF Downloads 458

Authors: Lakrim Abderrazak, Tahri Driss

Abstract:

This paper presents a new behavioural electrothermal model of power Silicon Carbide (SiC) MOSFET under SPICE. This model is based on the MOS model level 1 of SPICE, in which phenomena such as Drain Leakage Current IDSS, On-State Resistance RDSon, gate Threshold voltage VGSth, the transconductance (gfs), I-V Characteristics Body diode, temperature-dependent and self-heating are included and represented using behavioural blocks ABM (Analog Behavioural Models) of Spice library. This ultimately makes this model flexible and easily can be integrated into the various Spice -based simulation softwares. The internal junction temperature of the component is calculated on the basis of the thermal model through the electric power dissipated inside and its thermal impedance in the form of the localized Foster canonical network. The model parameters are extracted from manufacturers' data (curves data sheets) using polynomial interpolation with the method of simulated annealing (S A) and weighted least squares (WLS). This model takes into account the various important phenomena within transistor. The effectiveness of the presented model has been verified by Spice simulation results and as well as by data measurement for SiC MOS transistor C2M0025120D CREE (1200V, 90A).

Keywords: SiC power MOSFET, DC electro-thermal model, ABM Spice library, SPICE modelling, behavioural model, C2M0025120D CREE.

Procedia PDF Downloads 548

Authors: L. Boyaci

Abstract:

Two basic equipment of electrical power subsystem of space satellites are Power Conditioning Unit (PCU) and Power Distribution Unit (PDU). Today, the main switching element used in power equipment in satellites is silicon (Si) based radiation-hardened MOSFET. GaNFETs have superior performances over MOSFETs in terms of their conduction and switching characteristics. GaNFET has started to take MOSFET’s place in many applications in industry especially by virtue of its switching performances. If GaNFET can also be used in equipment for space applications, this would be great revolution for future space power subsystem designs. In this study, the effect of proton irradiation on Gallium Nitride based power transistors was investigated. Four commercial enhancement mode GaN power transistors from Efficient Power Conversion Corporation (EPC) are irradiated with 30MeV protons while devices are switching. Flux of 8.2x10⁹ protons/cm²/s is applied for 12.5 seconds to reach ultimate fluence of 10¹¹ protons/cm². Vgs-Ids characteristics are measured and recorded for each device before, during and after irradiation. It was observed that if there would be destructive events. Proton induced permanent damage on devices is not observed. All the devices remained healthy and continued to operate. For two of these devices, further irradiation is applied with same flux for 30 minutes up to a total fluence level of 1.476x10¹³ protons/cm². We observed that GaNFETs are fully functional under this high level of radiation and no destructive events and irreversible failures took place for transistors. Results reveal that irradiated GaNFET in this experiment has radiation tolerance under proton testing and very important candidate for being one of the future power switching element in space.

Keywords: enhancement mode GaN power transistors, proton irradiation effects, radiation tolerance

Procedia PDF Downloads 123

Authors: Won Taek Oh, Adin Richard

Abstract:

Workers are often required to enter unsupported trenches during the construction process, which may present serious risks. Trench failures can result in death or damage to adjacent properties, therefore trenches should be excavated with extreme precaution. Excavation work is often done in unsaturated soils, where the critical height (i.e. maximum depth that can be excavated without failure) of unsupported trenches can be more reliably estimated by considering the influence of matric suction. In this study, coupled stress/pore-water pressure analyses are conducted to investigate the critical height of sloped unsupported trenches considering the influence of pore-water pressure redistribution caused by excavating. Four different wall slopes (1.5V:1H, 2V:1H, 3V:1H, and 90°) and a vertical trench with the top 0.3 m sloped 1:1 were considered in the analyses with multiple depths of the ground water table in a sand. For comparison, the critical heights were also estimated using the limit equilibrium method for the same excavation scenarios used in the coupled analyses.

Keywords: critical height, matric suction, unsaturated soil, unsupported trench

Procedia PDF Downloads 96

Authors: A. A. Akande, B. P. Dhonge, B. W. Mwakikunga, A. G. J. Machatine

Abstract:

This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH₄VO₃ precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO₂ (B) with V₂O₅ and an amorphous phase. The BET surface area is found to be 67.67 m²/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO₂ sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO₂ sensors which normally show response and recovery times of the order of 5 minutes (300 s).

Keywords: VO2, VO2(B), MOSFET, gate voltage, humidity sensor

Procedia PDF Downloads 295

Authors: S.Pandeeswari, Raju Padma

Abstract:

In this paper a new solution to implement and control single-stage electronic ballast based on the integration of a buck-boost power factor correction stage and a half bridge resonant inverter is presented. The control signals are obtained using the inverter resonant current by means of a saturable transformer. Core saturation is used to control the required dead time between the control pulses on both switches. The turn-on time of one of the inverter switches is controlled to provide proper cathode preheating during the lamp ignition process. No special integrated circuits are required to control the ballast and the total number of components is minimized. Analysis and basic design of phase cut dimmer.

Keywords: MOSFET dimmer, PIC 16F877A, voltage regulator, bridge rectifier

Procedia PDF Downloads 343

Authors: Saurabh Chaudhury, Sanjeet Kumar Sinha

Abstract:

The MOSFET has been the main building block in high performance and low power VLSI chips for the last several decades. Device scaling is fundamental to technological advancements, which allows more devices to be integrated on a single die providing greater functionality per chip. Ultimately, the goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consumes less power. Scaling continued following Moore's law initially and now we see an exponential growth in today's nano scaled chip. However, device scaling to deep nano meter regime leads to exponential increase in leakage currents and excessive heat generation. Moreover, fabrication process variability causing a limitation to further scaling. Researchers believe that with a mix of chemistry, physics, and engineering, nano electronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nano tube (CNT) and nano wires (NW) based FETs have been analyzed and characterized in laboratory and also been demonstrated as prototypes. This work presents an extensive simulation based study and analysis of CNTFET and NW-FET devices and comparison of the results with conventional MOSFET. From this study, we can conclude that these devices have got some excellent properties and favorable characteristics which will definitely lead the future semiconductor devices in post silicon era.

Keywords: carbon nanotube, nanowire FET, low power, nanoscaled devices, VLSI

Procedia PDF Downloads 380

Authors: Yegetaneh T. Dejenu, Delesa Kejela, Abdulak Alemu

Abstract:

From the earliest time of humankind, the trenches were used for water to flow along and for soldiers to hide in during enemy attacks. Now a day due to civilization, the needs of the human being become endless, and the living condition becomes sophisticated. The unbalance between the needs and resource obligates them to find the way to manage this condition. The attempt to use the scares resource in very efficient and effective way makes the trench an endeavor practice in the world in all countries. A trencher is a construction equipment used to dig trenches, especially for laying pipes or cables, installing drainage, irrigation, installing fencing, and in preparation for trench warfare. It is a machine used to make a ditch by cutting the soil ground and effectively used in agricultural irrigation. The most common types of trencher are wheel trencher, chain trencher, micro trencher, portable trencher. In Ethiopia people have been trenching the ditch for many purposes and the tools they are using are Pickaxe, Shovel and some are using Micro Excavators. The adverse effect of using traditional equipment is, time and energy consuming, less productive, difficult and more man power is required. Hence it is necessary to design and produce low price, and simple machine to narrow this gap. Our objective is to design and model a light duty trencher that is used for trenching the ground or soil for making ditch and used for agricultural, ground cabling, ground piping, and drainage system. The designed machine trenches, maximum of 1-meter depth, 30 cm width, and the required length. The working mechanism is fully hydraulic, and the engine with 12.7 hp will provide suitable power for the pump that delivers 23 l/min at 1500 rpm to drive hydraulic motors and actuators.

Keywords: hydraulics, modelling, trenching, ditch

Procedia PDF Downloads 189

Authors: Sachin Kamble, Raghothama Anekal, Shivakumar Bhavi

Abstract:

Thermal management of electronic components packaged inside an IP65 rated enclosure is of prime importance in industrial applications. Electrical enclosure protects the multiple board configurations such as inverter, power, controller board components, busbars, and various power dissipating components from harsh environments. Industrial environments often experience relatively warm ambient conditions, and the electronic components housed in the enclosure dissipate heat, due to which the enclosures and the components require thermal management as well as reduction of internal ambient temperatures. Design of Experiments based thermal simulation approach with MOSFET arrangement, Heat sink design, Enclosure Volume, Copper and Aluminum Spreader, Power density, and Printed Circuit Board (PCB) type were considered to optimize air temperature inside the IP65 enclosure to ensure conducive operating temperature for controller board and electronic components through the different modes of heat transfer viz. conduction, natural convection and radiation using Ansys ICEPAK. MOSFET’s with the parallel arrangement, IP65 enclosure molded heat sink with rectangular fins on both enclosures, specific enclosure volume to satisfy the power density, Copper spreader to conduct heat to the enclosure, optimized power density value and selecting Aluminum clad PCB which improves the heat transfer were the contributors towards achieving a conducive operating temperature inside the IP-65 rated Motor Inverter enclosure. A reduction of 52 ℃ was achieved in internal ambient temperature inside the IP65 enclosure between baseline and final design parameters, which met the operative temperature requirements of the electronic components inside the IP-65 rated Motor Inverter.

Keywords: Ansys ICEPAK, aluminium clad PCB, IP 65 enclosure, motor inverter, thermal simulation

Procedia PDF Downloads 96

Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

Abstract:

An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

Procedia PDF Downloads 190

Authors: Rahil Samani, Saeed Soleimani, Ehsan Adib, Majid Pahlevani

Abstract:

This paper presents an inverting high step-up DC/DC converter. Basically, this high step-up DC/DC converter is an appealing interface for solar applications. The proposed topology takes advantage of using coupled inductors. Due to the leakage inductances of these coupled inductors, the power MOSFET has the zero current switching (ZCS) condition, which results in decreased switching losses. This will substantially improve the overall efficiency of the power converter. Furthermore, employing coupled inductors has led to a higher voltage gain. Theoretical analysis and experimental results of a 100W 20V/220V prototype are presented to verify the superior performance of the proposed DC/DC converter.

Keywords: coupled inductors, high step-up DC/DC converter, zero-current switching, Cuk converter, SEPIC converter

Procedia PDF Downloads 681

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter

Procedia PDF Downloads 425

Authors: S. Shahzadi, J. Rizk

Abstract:

This paper describes the pulse width modulated control of a three phase, 4 polar DC brushless motor. To implement this practically the Atmel’s AVR ATmega 328 microcontroller embedded on an Arduino Eleven board is utilized. The microcontroller programming is done in an open source Arduino IDE development environment. The programming logic effectively manipulated a six MOSFET bridge which was used to energize the stator windings as per control requirements. The results obtained showed accurate, precise and efficient pulse width modulated operation. Another advantage offered by this pulse width modulated control was the efficient speed control of the motor. By varying the time intervals between successive commutations, faster energizing of the stator windings was possible thereby leading to quicker rotor alignment with these energized phases and faster revolutions.

Keywords: brushless DC motors, commutation, MOSFET, PWM

Procedia PDF Downloads 480

Authors: Ravi Kiran Jaladi, Ezz I. El-Masry

Abstract:

Emerging technologies such as ultra-wide band wireless access technology that operate at ultra-low power present several challenges due to their inherent design that limits the use of voltage-mode filters. Therefore, Continuous-time current-mode (CTCM) filters have become very popular in recent times due to the fact they have a wider dynamic range, improved linearity, and extended bandwidth compared to their voltage-mode counterparts. The goal of this research is to develop analog filters which are suitable for the current scaling CMOS technologies. Bulk-driven MOSFET is one of the most popular low power design technique for the existing challenges, while other techniques have obvious shortcomings. In this work, a CTCM Gate-driven (GD) differentiator has been presented with a frequency range from dc to 100MHz which operates at very low supply voltage of 0.7 volts. A novel CTCM Bulk-driven (BD) differentiator has been designed for the first time which reduces the power consumption multiple times that of GD differentiator. These GD and BD differentiator has been simulated using CADENCE TSMC 65nm technology for all the bilinear and biquadratic band-pass frequency responses. These basic building blocks can be used to implement the higher order filters. A 6th order cascade CTCM Chebyshev band-pass filter has been designed using the GD and BD techniques. As a conclusion, a low power GD and BD 6th order chebyshev stagger-tuned band-pass filter was simulated and all the parameters obtained from all the resulting realizations are analyzed and compared. Monte Carlo analysis is performed for both the 6th order filters and the results of sensitivity analysis are presented.

Keywords: bulk-driven (BD), continuous-time current-mode filters (CTCM), gate-driven (GD)

Procedia PDF Downloads 229

Authors: Naima Guenifi, Shiromani Balmukund Rahi, Amina Bechka

Abstract:

Tunnel FET is one of the most suitable alternatives FET devices for conventional CMOS technology for low-power electronics and applications. Due to its lower subthreshold swing (SS) value, it is a strong follower of low power applications. It is a quantum FET device that follows the band to band (B2B) tunneling transport phenomena of charge carriers. Due to band to band tunneling, tunnel FET is suffering from a lower switching current than conventional metal-oxide-semiconductor field-effect transistor (MOSFET). For improvement of device features and limitations, the newly invented negative capacitance concept of ferroelectric material is implemented in conventional Tunnel FET structure popularly known as NC TFET. The present research work has implemented the idea of high-k gate dielectric added with ferroelectric material on double gate Tunnel FET for implementation of negative capacitance. It has been observed that the idea of negative capacitance further improves device features like SS value. It helps to reduce power dissipation and switching energy. An extensive investigation for circularity uses for digital, analog/RF and linearity features of double gate NCTFET have been adopted here for research work. Several essential designs paraments for analog/RF and linearity parameters like transconductance(gm), transconductance generation factor (gm/IDS), its high-order derivatives (gm2, gm3), cut-off frequency (fT), gain-bandwidth product (GBW), transconductance generation factor (gm/IDS) has been investigated for low power RF applications. The VIP₂, VIP₃, IMD₃, IIP₃, distortion characteristics (HD2, HD3), 1-dB, the compression point, delay and power delay product performance have also been thoroughly studied.

Keywords: analog/digital, ferroelectric, linearity, negative capacitance, Tunnel FET, transconductance

Procedia PDF Downloads 164

Authors: Zina Saheb, Ezz El-Masry

Abstract:

As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

Procedia PDF Downloads 502

Authors: Ryan Chalk, G. M. Shafiullah

Abstract:

Climate change is a pertinent issue facing governments and societies around the world. The industrial revolution has resulted in a steady increase in the average global temperature. The mining and energy production industries have been significant contributors to this change prompting government to intervene by promoting low emission technology within these sectors. This paper initially reviews the energy problem in Australia and the mining sector with a focus on the energy requirements and production methods utilised in Western Australia (WA). Renewable energy in the form of utility-scale solar photovoltaics (PV) provides a solution to these problems by providing emission-free energy which can be used to supplement the existing natural gas turbines in operation at the proposed site. This research presents a custom renewable solution for the mining site considering the specific township network, local weather conditions, and seasonal load profiles. A summary of the required PV output is presented to supply slightly over 50% of the towns power requirements during the peak (summer) period, resulting in close to full coverage in the trench (winter) period. Dig Silent Power Factory Software has been used to simulate the characteristics of the existing infrastructure and produces results of integrating PV. Large scale PV penetration in the network introduce technical challenges, that includes; voltage deviation, increased harmonic distortion, increased available fault current and power factor. Results also show that cloud cover has a dramatic and unpredictable effect on the output of a PV system. The preliminary analyses conclude that mitigation strategies are needed to overcome voltage deviations, unacceptable levels of harmonics, excessive fault current and low power factor. Mitigation strategies are proposed to control these issues predominantly through the use of high quality, made for purpose inverters. Results show that use of inverters with harmonic filtering reduces the level of harmonic injections to an acceptable level according to Australian standards. Furthermore, the configuration of inverters to supply active and reactive power assist in mitigating low power factor problems. Use of FACTS devices; SVC and STATCOM also reduces the harmonics and improve the power factor of the network, and finally, energy storage helps to smooth the power supply.

Keywords: climate change, mitigation strategies, photovoltaic (PV), power quality

Procedia PDF Downloads 143