Search results for: analog voltage inverter

Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

Procedia PDF Downloads 537

Authors: Atabak Faramarzpour, Mohsen Mohammadian

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In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

Procedia PDF Downloads 629

Authors: Sivaraman Karthikeyan

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Due to rapidly developing power electronics devices and technologies such as power line communication or self-commutating converters, voltage and current distortion, as well as interferences, have increased in the frequency range of 2 kHz to 150 kHz; there is an urgent need for regulation of electromagnetic compatibility (EMC) standards in this frequency range. Measuring or testing compliance with emission and immunity limitations necessitates the use of precise, repeatable measuring methods. Appropriate filters to minimize the fundamental component and its harmonics below 2 kHz in the measuring signal would improve the measurement accuracy in this frequency range leading to better analysis. This paper discusses filter suggestions in the current measurement standard and proposes an infinite impulse response (IIR) filter design that is optimized for a low number of poles, strong fundamental damping, and high accuracy above 2 kHz. The new filter’s transfer function is delivered as a result. An analog implementation is derived from the overall design.

Keywords: supraharmonics, 2 kHz, 150 kHz, filter, analog filter

Procedia PDF Downloads 112

Authors: V. S. Klimash, Ye Min Thu

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Thyristor rectifiers, inverters grid-tied, and AC voltage regulators are widely used in industry, and on electrified transport, they have a lot in common both in the power circuit and in the control system. They have a common mathematical structure and switching processes. At the same time, the rectifier, but the inverter units and thyristor regulators of alternating voltage are considered separately both theoretically and practically. They are written about in different books as completely different devices. The aim of this work is to combine them into one class based on the unity of the equations describing electromagnetic processes, and then, to show this unity on the mathematical model and experimental setup. Based on research from mathematics to the product, a conclusion is made about the methodology for the rapid conduct of research and experimental design work, preparation for production and serial production of converters with a unified bundle. In recent years, there has been a transition from thyristor circuits and transistor in modular design. Showing the example of thyristor rectifiers and AC voltage regulators, we can conclude that there is a unity of mathematical structures and grid-tied thyristor converters.

Keywords: direct current, alternating current, rectifier, AC voltage regulator, generalized mathematical model

Procedia PDF Downloads 228

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 495

Authors: Kang Hyun Yi

Abstract:

Wireless power transfer technologies are inductive coupling, magnetic resonance, and capacitive coupling methods, typically. Among them, the capacitive coupling wireless power transfer, also named Capacitive Coupling Wireless Power Transfer (CCWPT), has been researched to overcome the drawbacks of other approaches. The CCWPT has many advantages such as a simple structure, low standing power loss, reduced Electromagnetic Interference (EMI) and the ability to transfer power through metal barriers. In this paper, the CCWPT system with 6.78MHz class D inverter is proposed and analyzed. The proposed system is consisted of the 6.78MHz class D inverter with the LC low pass filter, the capacitor between a transmitter and a receiver and impedance transformers. The system is verified with a prototype for charging mobile devices.

Keywords: wireless power transfer, capacitive coupling power transfer, class D inverter, 6.78MHz

Procedia PDF Downloads 623

Authors: Alpana Agarwal, Akhil Sharma

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This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter

Procedia PDF Downloads 266

Authors: Markus Meyer, Bastian Maucher, Rolf Witzmann

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The ever increasing amount of distributed generation in low voltage distribution grids (mainly PV and micro-CHP) can lead to reverse load flows from low to medium/high voltage levels at times of high feed-in. Reverse load flow leads to rising voltages that may even exceed the limits specified in the grid codes. Furthermore, the share of electrical loads connected to low voltage distribution grids via switched power supplies continuously increases. In combination with inverter-based feed-in, this results in high harmonic levels reducing overall power quality. Especially high levels of third-order harmonic currents can lead to neutral conductor overload, which is even more critical if lines with reduced neutral conductor section areas are used. This paper illustrates a possible concept for smart grids in order to increase the feed-in capacity, improve power quality and to ensure safe operation of low voltage distribution grids at all times. The key feature of the concept is a hierarchically structured control strategy that is run on a superordinated controller, which is connected to several distributed grid analyzers and inverters via broad band powerline (BPL). The strategy is devised to ensure both quick response time as well as the technically and economically reasonable use of the available inverters in the grid (PV-inverters, batteries, stepless line voltage regulators). These inverters are provided with standard features for voltage control, e.g. voltage dependent reactive power control. In addition they can receive reactive power set points transmitted by the superordinated controller. To further improve power quality, the inverters are capable of active harmonic filtering, as well as voltage balancing, whereas the latter is primarily done by the stepless line voltage regulators. By additionally connecting the superordinated controller to the control center of the grid operator, supervisory control and data acquisition capabilities for the low voltage distribution grid are enabled, which allows easy monitoring and manual input. Such a low voltage distribution grid can also be used as a virtual power plant.

Keywords: distributed generation, distribution grid, power quality, smart grid, virtual power plant, voltage control

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Authors: N.Revathy, C.Gomathi

Abstract:

This work aims for a tunable capacitor as a sensor which can vary the control voltage of a voltage control oscillator in a ultra wide band (UWB) transmitter. In this paper power consumption is concentrated. The reason for choosing a capacitive sensing is it give slow temperature drift, high sensitivity and robustness. Previous works report a resistive sensing in a voltage control oscillator (VCO) not aiming at power consumption. But this work aims for power consumption of a capacitive sensing in ultra wide band transmitter. The ultra wide band transmitter to be used is a direct modulation of pulses. The VCO which is the heart of pulse generator of UWB transmitter works on the principle of voltage to frequency conversion. The VCO has and odd number of inverter stages which works on the control voltage input this input is now from a variable capacitor and the buffer stages is reduced from the previous work to maintain the oscillating frequency. The VCO is also aimed to consume low power. Then the concentration in choosing a variable capacitor is aimed. A compact model of a capacitor with the transient characteristics is to be designed with a movable dielectric and multi metal membranes. Previous modeling of the capacitor transient characteristics is with a movable membrane and a fixed membrane. This work aims at a membrane with a wide tuning suitable for ultra wide band transmitter.This is used in this work because a capacitive in a ultra wide transmitter need to be tuned in such a way that all satisfies FCC regulations.

Keywords: capacitive sensing, ultra wide band transmitter, voltage control oscillator, FCC regulation

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Authors: Wilfred Fritz

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Grid connected solar PV inverters need to be compliant to standard regulations regarding unwanted harmonic generation. This paper gives an introduction to harmonics, solar PV inverter voltage regulation and balancing through compensation and investigates the behaviour of harmonic generation at different power levels. Practical measurements of harmonics and power levels with a power quality data logger were made, on a test network at a university in Germany. The test setup and test results are discussed. The major finding was that between the morning and afternoon load peak windows when the PV inverters operate under low solar insolation and low power levels, more unwanted harmonics are generated. This has a huge impact on the power quality of the grid as well as capital and maintenance costs. The design of a single-tuned harmonic filter towards harmonic mitigation is presented.

Keywords: harmonics, power quality, pulse width modulation, total harmonic distortion

Procedia PDF Downloads 201

Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

Procedia PDF Downloads 528

Authors: Malinwo Estone Ayikpa

Abstract:

With the rapid increase of grid-connected PV systems over the last decades, genuine challenges have arisen for engineers and professionals of energy field in the planning and operation of existing distribution networks with the integration of new generation sources. However, the conventional distribution network, in its design was not expected to receive other generation outside the main power supply. The tools generally used to analyze the networks become inefficient and cannot take into account all the constraints related to the operation of grid-connected PV systems. Some of these constraints are voltage control difficulty, reverse power flow, and especially voltage unbalance which could be due to the poor distribution of single-phase PV systems in the network. In order to analyze the impact of the connection of small and large number of PV systems to the distribution networks, this paper presents an efficient optimization tool that minimizes voltage unbalance in three-phase distribution networks with active and reactive power injections from the allocation of single-phase and three-phase PV plants. Reactive power can be generated or absorbed using the available capacity and the adjustable power factor of the inverter. Good reduction of voltage unbalance can be achieved by reactive power control of the PV systems. The presented tool is based on the three-phase current injection method and the PV systems are modeled via an equivalent circuit. The primal-dual interior point method is used to obtain the optimal operating points for the systems.

Keywords: Photovoltaic system, Primal-dual interior point method, Three-phase optimal power flow, Voltage unbalance

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Authors: A. Elnady

Abstract:

This paper presents an improved Direct Power Control (DPC) scheme applied to the multilevel inverter that forms a Distributed Generation Unit (DGU). This paper demonstrates the performance of active and reactive power injected by the DGU to the smart grid. The DPC is traditionally operated by the hysteresis controller with the Space Vector Modulation (SVM) which is applied on the 2-level inverters or 3-level inverters. In this paper, the DPC is operated by the PI controller with the Phase-Disposition Pulse Width Modulation (PD-PWM) applied to the 5-level diode clamped inverter. The new combination of the DPC, PI controller, PD-PWM and multilevel inverter proves that its performance is much better than the conventional hysteresis-SVM based DPC. Simulations results have been presented to validate the performance of the suggested control scheme in the grid-connected mode.

Keywords: direct power control, PI controller, PD-PWM, and power control

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Authors: L. Lakhdari, B. Bouchiba, M. Bechar

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The multi-level inverters present an important novelty in the field of energy control with high voltage and power. The major advantage of all multi-level inverters is the improvement and spectral quality of its generated output signals. In recent years, various pulse width modulation techniques have been developed. From these technics we have: Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM). This work presents a detailed analysis of the comparative advantage of space vector pulse width modulation (SVPWM) and the standard SPWM technique for Three Level Diode Clamped Inverter fed Induction Motor. The comparison is based on the evaluation of harmonic distortion THD.

Keywords: induction motor, multilevel inverters, SVPWM, SPWM, THD

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Authors: Deepak M. Sajnekar, S. B. Deshpande, R. M. Mohril

Abstract:

At present many rotary excitation control system are using analog type of Automatic Voltage Regulator which now started to replace with the digital automatic voltage regulator which is provided with PID controller and tuning of PID controller is a challenging task. The cases where digital excitation control system is used tuning of PID controller are still carried out by pole placement method. Tuning of PID controller used for static excitation control system is not challenging because it does not involve exciter time constant. This paper discusses two methods of tuning PID controller i.e. Pole placement method and pole zero cancellation method. GUI prepared for both the methods on the platform of MATLAB. Using this GUI, performance results and time required for tuning for both the methods are compared. Sensitivity of the methods is also presented with parameter variation like loop gain ‘K’ and exciter time constant ‘te’.

Keywords: digital excitation system, automatic voltage regulator, pole placement method, pole zero cancellation method

Procedia PDF Downloads 637

Authors: MeiBo, ZhaoXing, LuoLei, YuQingkui, TangMin, HanZhengsheng

Abstract:

The Single Event Transients (SETs) were investigated on 0.18μm PDSOI transistors and 100 series CMOS inverter chain using pulse laser. The effect of different laser energy and device bias for waveform on SET was characterized experimentally, as well as the generation and propagation of SET in inverter chain. In this paper, the effects of struck transistors type and struck locations on SETs were investigated. The results showed that when irradiate NMOSFETs from 100th to 2nd stages, the SET pulse width measured at the output terminal increased from 287.4 ps to 472.9 ps; and when irradiate PMOSFETs from 99th to 1st stages, the SET pulse width increased from 287.4 ps to 472.9 ps. When struck locations were close to the output of the chain, the SET pulse was narrow; however, when struck nodes were close to the input, the SET pulse was broadening. SET pulses were progressively broadened up when propagating along inverter chains. The SET pulse broadening is independent of the type of struck transistors. Through analysis, history effect induced threshold voltage hysteresis in PDSOI is the reason of pulse broadening. The positive pulse observed by oscilloscope, contrary to the expected results, is because of charging and discharging of capacitor.

Keywords: single event transients, pulse laser, partially-depleted silicon-on-insulator, propagation-induced pulse broadening effect

Procedia PDF Downloads 384

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

Procedia PDF Downloads 348

Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 369

Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

Abstract:

At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

Procedia PDF Downloads 322

Authors: Kang Hyun Yi

Abstract:

This paper presents a new parallel output LLC DC/DC converter for electric vehicle. The electric vehicle has two batteries. One is a high voltage battery for the powertrain of the vehicle and the other is a low voltage battery for the vehicle electric system. The low voltage is charged from the high voltage battery and the high voltage input and the high current output DC/DC converter is needed. Therefore, the new LLC converter with the input voltage compensation is proposed for the high voltage input and the low voltage output DC/DC converter. The proposed circuit has two LLC converters with the series input voltage from the battery for the powertrain and the parallel output low battery voltage for the vehicle electric system because the battery voltage for the powertrain and the electric power for the vehicle become high. Also, the input series voltage compensation capacitor is used for balancing the input current in the two LLC converters. The proposed converter has an equal electric stress of the semiconductor parts and the reactive components, high efficiency and good heat dissipation.

Keywords: electric vehicle, LLC DC/DC converter, input voltage balancing, parallel output

Procedia PDF Downloads 1021

Authors: Dheeraj Sharma, Santosh Kumar Vishvakarma

Abstract:

We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product.

Keywords: Gate-All-Around MOSFET, GAA, output resistance, transconductance generation factor, intrinsic gain, cutoff frequency, fT

Procedia PDF Downloads 363

Authors: N. Ravikumar, S. Krishnan, B. Yokeshkumar

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In present days, the power quality issues are increases due to non-linear loads like fridge, AC, washing machines, induction motor, etc. This power quality issues will affects the output voltages, output current, and output power of the total performance of the generator. This paper explains how to test the generator using the Fluke 435 II series power quality analyser. This Fluke 435 II series power quality analyser is used to measure the voltage, current, power, energy, total harmonic distortion (THD), current harmonics, voltage harmonics, power factor, and frequency. The Fluke 435 II series power quality analyser have several advantages. They are i) it will records output in analog and digital format. ii) the fluke analyzer will records at every 0.25 sec. iii) it will also measure all the electrical parameter at a time.

Keywords: THD, harmonics, power quality, TNEB, Fluke 435

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Authors: Puneet Chawla, Balwinder Singh

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Recently, increased attention has been devoted to the voltage instability phenomenon in power systems. Many techniques have been proposed in the literature for evaluating and predicting voltage stability using steady state analysis methods. In this paper, P-V and Q-V curves have been generated for a 57 bus Patiala Rajpura circle of India. The power-flow program is developed in MATLAB using Newton-Raphson method. Using Q-V curves, the weakest bus of the power system and the maximum reactive power change permissible on that bus is calculated. STATCOMs are placed on the weakest bus to improve the voltage and hence voltage stability and also the power transmission capability of the line.

Keywords: voltage stability, reactive power, power flow, weakest bus, STATCOM

Procedia PDF Downloads 483

Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, voltage transition, node stabilization, biasing circuits

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Authors: Christos Konstantopoulos, Thomas Ussmueller

Abstract:

Digital low drop-out regulators, in contrast to analog counterparts, provide an architecture of sub-1 V regulation with low power consumption, high power efficiency, and system integration. Towards an optimized integration in the ultra-low-power system-on-chip Internet of Things architecture that is operated through a radio frequency energy harvesting scheme, the D-LDO regulator should constitute the main regulator that operates the master-clock and rest loads of the SoC. In this context, we present a D-LDO with linear search coarse regulation and asynchronous fine regulation, which incorporates an in-regulator clock generation unit that provides an autonomous, self-start-up, and power-efficient D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the frequency, this work presents a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of coarse regulation frequency. The design is implemented in a 55-nm Global Foundries CMOS process. With the purpose to validate the self-start-up capability of the presented D-LDO in the presence of ultra-low input power, an on-chip test-bench with an RF rectifier is implemented as well, which provides the RF to DC operation and feeds the D-LDO. Power efficiency and load regulation curves of the D-LDO are presented as extracted from the RF to regulated DC operation. The D-LDO regulator presents 83.6 % power efficiency during the RF to DC operation with a 3.65 uA load current and voltage regulator referred input power of -27 dBm. It succeeds 486 nA maximum quiescent current with CL 75 pF, the maximum current efficiency of 99.2%, and 1.16x power efficiency improvement compared to analog voltage regulator counterpart oriented to SoC IoT loads. Complementary, the transient performance of the D-LDO is evaluated under the transient droop test, and the achieved figure-of-merit is compared with state-of-art implementations.

Keywords: D-LDO, Internet of Things, RF energy harvesting, voltage regulators

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Authors: Kyoung-Il Do, Jun-Geol Park, Hee-Guk Chae, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

A SCR stacking structure is proposed to have improved Latch-up immunity. In comparison with conventional SCR (Silicon Controlled Rectifier), the proposed Electrostatic Discharge (ESD) protection circuit has a lower trigger characteristic by using the LVTSCR (Low Voltage Trigger) structure. Also the proposed ESD protection circuit has improved Holding Voltage Characteristic by using N-stack technique. These characteristics enable to have latch-up immunity in operating conditions. The simulations are accomplished by using the Synopsys TCAD. It has a trigger voltage of 8.9V and a holding voltage of 1.8V in a single structure. And when applying the stack technique, 2-stack has the holding voltage of 3.8V and 3-stack has the holding voltage of 5.1 V.

Keywords: electrostatic discharge (ESD), low voltage trigger silicon controlled rectifier (LVTSCR), MVTSCR, power clamp, silicon controlled rectifier (SCR), latch-up

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Authors: Megha Chavda, Parth Thummar, Rahul Ghetia

Abstract:

This paper presents the voltage and current control of microgrid accompanied by the synchronization of microgrid with the main utility grid in both islanded and grid-connected modes. Distributed Energy Resources (DERs) satisfy the wide-spread power demand of consumer by behaving as a micro source for a low voltage (LV) grid or microgrid. Synchronization of the microgrid with the main utility grid is done using PLL and PWM gate pulse generation technique is used for the Voltage Source Converter. Potential Function method achieves the voltage and current control of this microgrid in both islanded and grid-connected modes. A low voltage grid consisting of three distributed generators (DG) is considered for the study and is simulated in time-domain using PSCAD/EMTDC software. The simulation results depict the appropriateness of voltage and current control of microgrid and synchronization of microgrid with the medium voltage (MV) grid.

Keywords: microgrid, distributed energy resources, voltage and current control, voltage source converter, pulse width modulation, phase locked loop

Procedia PDF Downloads 386

Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, multi-inputs, voltage transition, node stabilization, biasing circuits

Procedia PDF Downloads 529

Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

Abstract:

In this paper, we proposed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuit for latch-up immunity. The proposed circuit has a lower trigger voltage and a higher holding voltage characteristic by using the zener diode structure. These characteristics prevent latch-up problem in normal operating conditions. The proposed circuit was analyzed to figure out the electrical characteristics by the variations of design parameters D1, D2 and stack technology to obtain the n-fold electrical characteristics. The simulations are accomplished by using the Synopsys TCAD simulator. When using the stack technology, 2-stack has the holding voltage of 6.9V and 3-stack has the holding voltage of 10.9V.

Keywords: ESD, SCR, trigger voltage, holding voltage

Procedia PDF Downloads 492

Authors: Shao-Ku Kao

Abstract:

This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: wireless power transfer, active diode, delay compensation, time to voltage converter, PCE

Procedia PDF Downloads 247