Search results for: push-pull circuits

Authors: K. Shaji Mon, P. R. John Sreenidhi

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In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Jerome G. Chandraseelan, Samuel M. D. Oliveira, Antti Häkkinen, Sofia Startceva, Andre S. Ribeiro

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We used live E. coli containing synthetic genetic oscillators to study how the degree of synchrony between the genetic circuits of sister cells changes with temperature. We found that both the mean and the variability of the degree of synchrony between the fluorescence signals from sister cells are affected by temperature. Also, while most pairs of sister cells were found to be highly synchronous in each condition, the number of asynchronous pairs increased with increasing temperature, which was found to be due to disruptions in the oscillations. Finally we provide evidence that these disruptions tend to affect multiple generations as opposed to individual cells. These findings provide insight in how to design more robust synthetic circuits and in how cell division can affect their dynamics.

Keywords: repressilator, robustness, synchrony, synthetic biology

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Authors: Abdeljalil Metioui

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The purpose of this article is to present the results of two-stage qualitative research. The first involved the identification of the alternative conceptions of 80 elementary pre-service teachers from Quebec in Canada about the operation of simple electrical circuits. To do this, they completed a two-choice questionnaire (true or false) with justification. Data analysis identifies many conceptual difficulties. For example, for their majority, whatever the electrical device that composes an electrical circuit, the current source (power supply), and the generated electrical power is constant. The second step was to develop a double multiple-choice questionnaire based on the identified designs. It allows teachers to quickly diagnose their students' conceptions and take them into account in their teaching.

Keywords: development, electrical circuits, two-tier diagnostic test, secondary and high school

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: M. A. Grigoryev, A. N. Shishkov, D. A. Sychev

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The article defines the necessity of choosing the optimal power circuits scheme of the electric drive with field regulated reluctance machine. The specific weighting factors are calculation, the linear regression dependence of specific losses in semiconductor frequency converters are presented depending on the values of the rated current. It is revealed that with increase of the carrier frequency PWM improves the output current waveform, but increases the loss, so you will need depending on the task in a certain way to choose from the carrier frequency. For task of optimization by criterion of the minimum electrical losses regression dependence of the electrical losses in the frequency converter circuit at a frequency of a PWM signal of 0 Hz. The surface optimization criterion is presented depending on the rated output torque of the motor and number of phases. In electric drives with field regulated reluctance machine with at low output power optimization criterion appears to be the worst for multiphase circuits. With increasing output power this trend hold true, but becomes insignificantly different optimal solutions for three-phase and multiphase circuits. This is explained to the linearity of the dependence of the electrical losses from the current.

Keywords: field regulated reluctance machine, the electrical losses, multiphase power circuit, the surface optimization criterion

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Authors: Kwan-Ho Kim, Jin-Hong Park

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The multi-valued logic (MVL) circuits, which can handle more than two logic states, are one of the promising solutions to overcome the bit density limitations of conventional binary logic systems. Recently, tunneling devices such as Esaki diode and resonant tunneling diode (RTD) have been extensively explored to construct the MVL circuits. These tunneling devices present a negative differential resistance (NDR) phenomenon in which a current decreases as a voltage increases in a specific applied voltage region. Due to this non-monotonic current behavior, the tunneling devices have more than two threshold voltages, consequently enabling construction of MVL circuits. Recently, the emergence of two dimensional (2D) van der Waals (vdW) crystals has opened up the possibility to fabricate such tunneling devices easily. Owing to the defect-free surface of the 2D crystals, a very abrupt junction interface could be formed through a simple stacking process, which subsequently allowed the implementation of a high-performance tunneling device. Here, we report a vdW heterostructure based tunneling device with multiple threshold voltages, which was fabricated with black phosphorus (BP) and hafnium diselenide (HfSe₂). First, we exfoliated BP on the SiO₂ substrate and then transferred HfSe₂ on BP using dry transfer method. The BP and HfSe₂ form type-Ⅲ heterojunction so that the highly doped n+/p+ interface can be easily implemented without additional electrical or chemical doping process. Owing to high natural doping at the junction, record high peak to valley ratio (PVCR) of 16 was observed to the best our knowledge in 2D materials based NDR device. Furthermore, based on this, we first demonstrate the feasibility of the ternary latch by connecting two multi-threshold voltage devices in series.

Keywords: two dimensional van der Waals crystal, multi-valued logic, negative differential resistnace, tunneling device

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Authors: Iman Farasat, Howard M. Salis

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Engineered genetic circuits reprogram cellular behavior to act as living computers with applications in detecting cancer, creating self-controlling artificial tissues, and dynamically regulating metabolic pathways. Phenemenological models are often used to simulate and design genetic circuit behavior towards a desired behavior. While such models assume that each circuit component’s function is modular and independent, even small changes in a circuit (e.g. a new promoter, a change in transcription factor expression level, or even a new media) can have significant effects on the circuit’s function. Here, we use statistical thermodynamics to account for the several factors that control transcriptional regulation in bacteria, and experimentally demonstrate the model’s accuracy across 825 measurements in several genetic contexts and hosts. We then employ our first principles model to design, experimentally construct, and characterize a family of signal amplifying genetic circuits (genetic OpAmps) that expand the dynamic range of cell sensors. To develop these models, we needed a new approach to measuring the in vivo binding free energies of transcription factors (TFs), a key ingredient of statistical thermodynamic models of gene regulation. We developed a new high-throughput assay to measure RNA polymerase and TF binding free energies, requiring the construction and characterization of only a few constructs and data analysis (Figure 1A). We experimentally verified the assay on 6 TetR-homolog repressors and a CRISPR/dCas9 guide RNA. We found that our binding free energy measurements quantitatively explains why changing TF expression levels alters circuit function. Altogether, by combining these measurements with our biophysical model of translation (the RBS Calculator) as well as other measurements (Figure 1B), our model can account for changes in TF binding sites, TF expression levels, circuit copy number, host genome size, and host growth rate (Figure 1C). Model predictions correctly accounted for how these 8 factors control a promoter’s transcription rate (Figure 1D). Using the model, we developed a design framework for engineering multi-promoter genetic circuits that greatly reduces the number of degrees of freedom (8 factors per promoter) to a single dimensionless unit. We propose the Ptashne (Pt) number to encapsulate the 8 co-dependent factors that control transcriptional regulation into a single number. Therefore, a single number controls a promoter’s output rather than these 8 co-dependent factors, and designing a genetic circuit with N promoters requires specification of only N Pt numbers. We demonstrate how to design genetic circuits in Pt number space by constructing and characterizing 15 2-repressor OpAmp circuits that act as signal amplifiers when within an optimal Pt region. We experimentally show that OpAmp circuits using different TFs and TF expression levels will only amplify the dynamic range of input signals when their corresponding Pt numbers are within the optimal region. Thus, the use of the Pt number greatly simplifies the genetic circuit design, particularly important as circuits employ more TFs to perform increasingly complex functions.

Keywords: transcription factor, synthetic biology, genetic circuit, biophysical model, binding energy measurement

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Authors: Jelena Slugan, Ivica Ružić

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We are witnessing the rapid development of technologies that change the world around us. However, curriculums and teaching processes are often slow to adapt to the change; it takes time, money and expertise to implement technology in the classroom. Therefore, the University of Split, Croatia, partnered with local school Marko Marulić High School and created the project "Modern competence in modern high schools" as part of which five different curriculums for STEM areas were developed. One of the curriculums involves combining information technology with physics. The main idea was to teach students how to use different circuits and microcomputers to explore nature and physical phenomena. As a result, using electrical circuits, students are able to recreate in the classroom the phenomena that they observe every day in their environment. So far, high school students had very little opportunity to perform experiments independently, and especially, those physics experiment did not involve ICT. Therefore, this project has a great importance, because the students will finally get a chance to develop themselves in accordance to modern technologies. This paper presents some new methods of teaching physics that will help students to develop experimental skills through the study of deterministic nature of physical laws. Students will learn how to formulate hypotheses, model physical problems using the electronic circuits and evaluate their results. While doing that, they will also acquire useful problem solving skills.

Keywords: ICT in physics, curriculum, laboratory activities, STEM (science, technology, engineering, mathematics)

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Authors: Vishal Pareek, Shubham Gupta, Sushil Chandra Jain

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With increasing high-speed computation demand the power consumption, heat dissipation and chip size issues are posing challenges for logic design with conventional technologies. Recovery of bit loss and bit errors is other issues that require reversibility and fault tolerance in the computation. The reversible computing is emerging as an alternative to conventional technologies to overcome the above problems and helpful in a diverse area such as low-power design, nanotechnology, quantum computing. Bit loss issue can be solved through unique input-output mapping which require reversibility and bit error issue require the capability of fault tolerance in design. In order to incorporate reversibility a number of combinational reversible logic based circuits have been developed. However, very few sequential reversible circuits have been reported in the literature. To make the circuit fault tolerant, a number of fault model and test approaches have been proposed for reversible logic. In this paper, we have attempted to incorporate fault tolerance in sequential reversible building blocks such as D flip-flop, T flip-flop, JK flip-flop, R-S flip-flop, Master-Slave D flip-flop, and double edge triggered D flip-flop by making them parity preserving. The importance of this proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault and single bit fault. In our opinion our design of reversible building blocks is superior to existing designs in term of quantum cost, hardware complexity, constant input, garbage output, number of gates and design of online testable D flip-flop have been proposed for the first time. We hope our work can be extended for building complex reversible sequential circuits.

Keywords: parity preserving gate, quantum computing, fault tolerance, flip-flop, sequential reversible logic

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Authors: Zahra Khalid, Gul Muhammad Khan, Arbab Masood Ahmad

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Cartesian Genetic Programming (CGP) is explored to design an optimal circuit capable of early stage breast cancer detection. CGP is used to evolve simple multiplexer circuits for detection of malignancy in the Fine Needle Aspiration (FNA) samples of breast. The data set used is extracted from Wisconsins Breast Cancer Database (WBCD). A range of experiments were performed, each with different set of network parameters. The best evolved network detected malignancy with an accuracy of 99.14%, which is higher than that produced with most of the contemporary non-linear techniques that are computational expensive than the proposed system. The evolved network comprises of simple multiplexers and can be implemented easily in hardware without any further complications or inaccuracy, being the digital circuit.

Keywords: breast cancer detection, cartesian genetic programming, evolvable hardware, fine needle aspiration

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Mohamed Sanad, Noha Hassan

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A broadband resonant terminal antenna has been developed. It can be used in different MIMO arrangements such as 2x2, 4x4, 8x8, or even 12x12 MIMO configurations. The antenna covers the whole LTE and WiFi bands besides the existing 2G/3G bands (700-5800 MHz), without using any matching/tuning circuits. Matching circuits significantly reduce the efficiency of any antenna and reduce the battery life. They also reduce the bandwidth because they are frequency dependent. The antenna can be implemented in smartphone handsets, tablets, laptops, notebooks or any other terminal. It is also suitable for different IoT and vehicle applications. The antenna is manufactured from a flexible material and can be bent or folded and shaped in any form to fit any available space in any terminal. It is self-contained and does not need to use the ground plane, the chassis or any other component of the terminal. Hence, it can be mounted on any terminal at different positions and configurations. Its performance does not get affected by the terminal, regardless of its type, shape or size. Moreover, its performance does not get affected by the human body of the terminal’s users. Because of all these unique features of the antenna, multiples of them can be simultaneously used for MIMO diversity coverage in any terminal device with a high isolation and a low correlation factor between them.

Keywords: IOT, LTE, MIMO, terminal antenna, WiFi

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Authors: K. Yahia, M. Sahraoui, A. Guettaf

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This paper deals with the problem of stator faults diagnosis in induction motors. Using the discrete wavelet transform (DWT) for the current Park’s vector modulus (CPVM) analysis, the inter-turn short-circuit faults diagnosis can be achieved. This method is based on the decomposition of the CPVM signal, where wavelet approximation and detail coefficients of this signal have been extracted. The energy evaluation of a known bandwidth detail permits to define a fault severity factor (FSF). This method has been tested through the simulation of an induction motor using a mathematical model based on the winding-function approach. Simulation, as well as experimental results, show the effectiveness of the used method.

Keywords: induction motors (IMs), inter-turn short-circuits diagnosis, discrete wavelet transform (DWT), Current Park’s Vector Modulus (CPVM)

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Authors: P. Pistelok

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The article presents the concept of an electromagnetic circuit generator with permanent magnets mounted on the surface rotor core designed for single phase work. Computation field-circuit model was shown. The spectrum of time course of voltages in the idle work was presented. The cross section with graphically presentation of magnetic induction in particular parts of electromagnetic circuits was presented. Distribution of magnetic induction at the rated load point for each phase were shown. The time course of voltages and currents for each phases for rated power were displayed. An analysis of laboratory results and measurement of load characteristics of the generator was discussed. The work deals with three electromagnetic circuits of generators with permanent magnet where output voltage characteristics versus rated power were expressed.

Keywords: permanent magnet generator, permanent magnets, vibration, course of torque, single phase work, asymmetrical three phase work

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

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As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: scan chain, single event transient, soft error, 8051 processor

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Authors: K. Yahia, A. Ghoggal, A. Titaouine, S. E. Zouzou, F. Benchabane

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This paper deals with the problem of stator faults diagnosis in induction motors. Using the discrete wavelet transform (DWT) for the current Park’s vector modulus (CPVM) analysis, the inter-turn short-circuit faults diagnosis can be achieved. This method is based on the decomposition of the CPVM signal, where wavelet approximation and detail coefficients of this signal have been extracted. The energy evaluation of a known bandwidth detail permits to define a fault severity factor (FSF). This method has been tested through the simulation of an induction motor using a mathematical model based on the winding-function approach. Simulation, as well as experimental, results show the effectiveness of the used method.

Keywords: Induction Motors (IMs), Inter-turn Short-Circuits Diagnosis, Discrete Wavelet Transform (DWT), Current Park’s Vector Modulus (CPVM)

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Authors: Mark Anthony Casimiro, Ivan Culaba, Cornelia Soto

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Misconceptions are the wrong concepts understood by the students which may come up based on what they experience and observe around their environment. This seemed to hinder students’ learning. In this study, six different misconceptions were determined by the researcher from the previous researches. Teachers play a vital role in the classroom. The use of appropriate strategies can contribute a lot in the success of teaching and learning Physics. The current study aimed to compare two strategies- Interactive Lecture Demonstration (ILD) and Inquiry-Based Instruction (IBI) in addressing students’ misconceptions in electric circuits. These two strategies are both interactive learning activities and student-centered. In ILD, the teacher demonstrates the activity and the students have their predictions while in IBI, students perform the experiments. The study used the mixed method in which quantitative and qualitative researches were combined. The main data of this study were the test scores of the students from the pretest and posttest. Likewise, an interview with the teacher, observer and students was done before, during and after the execution of the activities. Determining and Interpreting Resistive Electric Circuits Test version 2 (DIRECT v.2) was the instrument used in the study. Two sections of Grade 9 students from Kalumpang National High School were the respondents of the study. The two strategies were executed to each section; one class was assigned as the ILD group and the other class was the IBI group. The Physics teacher of the said school was the one who taught and executed the activities. The researcher taught the teacher the steps in doing the two strategies. The Department of Education level of proficiency in the Philippines was adopted in scoring and interpretation. The students’ level of proficiency was used in assessing students’ knowledge on electric circuits. The pretest result of the two groups had a p-value of 0.493 which was greater than the level of significance 0.05 (p >0.05) and it implied that the students’ level of understanding in the topic was the same before the execution of the strategies. The posttest results showed that the p-value (0.228) obtained was greater than the level of significance which is 0.05 (p> 0.05). This implied that the students from the ILD and IBI groups had the same level of understanding after the execution of the two strategies. This could be inferred that either of the two strategies- Interactive Lecture Demonstration and Inquiry-Based Instruction could be used in addressing students’ misconception in electric circuit as both had similar effect on the students’ level of understanding in the topic. The result of this study may greatly help teachers, administration, school heads think of appropriate strategies that can address misconceptions depending on the availability of their materials of their school.

Keywords: inquiry- based instruction, interactive lecture demonstration, misconceptions, mixed method

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Authors: Saleem Rao, Mohammed Al-Ghadeer, Archan Banerjee, Hossein Fariborzi

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Materials imperfection, particularly two-level-system (TLS) defects in planer superconducting quantum circuits, contributes significantly to decoherence, ultimately limiting the performance of quantum computation and sensing. Oxides at air interfaces are among the host of TLS, and different material has been used to reduce TLS losses. Passivation with an inorganic layer is not an option to reduce these interface oxides; however, they can be etched away, but their regrowth remains a problem. Here, we report the chemisorption of molecular self-assembled monolayers (SAMs) at air interfaces of superconducting co-planer waveguide (CPW) resonators that suppress the regrowth of oxides and also modify the dielectric constant of the interface. With SAMs, we observed sustained order of magnitude improvement in quality factor -better than oxide etched interfaces. Quality factor measurements at millikelvin temperature and at single photon, XPS data, and TEM images of SAM passivated air interface sustenance our claim. Compatibility of SAM with micro-/nano-fabrication processes opens new ways to improve the coherence time in cQED.

Keywords: superconducting circuits, quality-factor, self-assembled monolayer, coherence

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Authors: Fawzi Srairi, Abderrahmane Dib

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Recently, the desire for a self-powered micro and nanodevices has attracted a great interest of using sustainable energy sources. Further, the ultimate goal of nanogenerator is to harvest energy from the ambient environment in which a self-powered device based on these generators is needed. With the development of nanogenerator-based circuits design and optimization, the building of new device simulator is necessary for the study and the synthesis of electromechanical parameters of this type of models. In the present article, both numerical modeling and optimization of piezoelectric nanogenerator based on zinc oxide have been carried out. They aim to improve the electromechanical performances, robustness, and synthesis process for nanogenerator. The proposed model has been developed for a systematic study of the nanowire morphology parameters in stretching mode. In addition, heuristic optimization technique, namely, particle swarm optimization has been implemented for an analytic modeling and an optimization of nanogenerator-based process in stretching mode. Moreover, the obtained results have been tested and compared with conventional model where a good agreement has been obtained for excitation mode. The developed nanogenerator model can be generalized, extended and integrated into simulators devices to study nanogenerator-based circuits.

Keywords: electrical potential, heuristic algorithms, numerical modeling, nanogenerator

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Authors: Atif Mahmood, Mohammad Inayatullah Khan Babar

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Communication infrastructure has been installed, operated, and maintained all over the world according to defined electrical safety standards for separate or joint structures. These safety standards have been set for the safeguard of public, utility workers (employees and contractors), utility facilities, electrical communication equipment’s connected to the utility facilities and other facilities or premise adjacent to utility facilities. Different communication utilities in Pakistan use standards of different countries due to the absence of Common National Electrical Safety Standards of Pakistan. It is really important to devise a framework for implementation of a uniform standard for strict compliance. In this context, it is important to explore the compliance of safety standards for communication conductors and equipment for separate or joint structures for which NESC standards are taken as reference. Specific reference to grounding techniques including grounding AC/DC systems and its frames, leaving Fences, Messenger wires and special circuits used for the protection for lightning etc, ungrounded so recommendations are also given after in-depth analysis of current technical practices for the installation and maintenance of communication infrastructure.

Keywords: utility facilities, grounding electrodes, special circuits, grounding conductor

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Authors: Mehdi Radmehr, Amir Hamed Mashhadzadeh, Mehdi Jafari

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Traditional HVDC systems are tough to DC short circuits as they are current regulated with a large reactance connected in series with cables. Multi-terminal DC wind farm topologies are attracting increasing research attempt. With AC/DC converters on the generator side, this topology can be developed into a multi-terminal DC network for wind power collection, which is especially suitable for large-scale offshore wind farms. For wind farms, the topology uses high-voltage direct-current transmission based on voltage-source converters (VSC-HVDC). Therefore, they do not suffer from over currents due to DC cable faults and there is no over current to react to. In this study, the multi-terminal DC wind farm topology is introduced. Then, possible internal DC faults are analyzed according to type and characteristic. Fault over current expressions are given in detail. Under this characteristic analysis, fault detection and detailed protection methods are proposed. Theoretical analysis and PSCAD/EMTDC simulations are provided.

Keywords: DC short circuits, multi-terminal DC wind farm topologies, HVDC transmission based on VSC, fault analysis

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Authors: Patel Himeshkumar Ashokbhai, Suchit Sharma, Arvind Kumar Garg

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The purpose of this paper is to study the effect of change in feed rate on grinding circuit and cyclone efficiency in case of lead-zinc ore. The following experiments and analysis were conducted on beneficiation circuit of Sindesar Khurd (SK) mines under Hindustan Zinc Ltd. subsidiary of Vedanta Group of Companies, a leading producer of lead-Zinc, silver and cadmium (as by products) in India. Feed rate is an important variable in beneficiation circuit operation. Optimizing feed rate is indispensable for any grinding circuit and directly effects cyclone efficiency. The size analysis of ore in grinding circuit along with cyclone efficiency on varying feed rates establishes their interdependence. Feed rate determines retention time ore gets within grinding circuit. Retention time in turn determines degree of liberation of mineral. Inadequate liberation causes decreased circuit efficiency. In this paper we have studied the effect of varying feed rate on (1) D80 particle size of different sections of different streams of grinding circuit (2) Re-circulating load (3) Cyclone efficiency. As a conclusion, this study gives some clues to operate grinding circuits and hydro-cyclones in more efficient way regarding beneficiation of Lead-zinc ore.

Keywords: cyclone efficiency, feed rate, grinding circuit, re-circulating load

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Authors: Felipe M. de Freitas, Icaro V. Soares, Lucas L. L. Fortes, Sandro T. M. Gonçalves, Úrsula D. C. Resende

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The SPICE-based simulators are quite robust and widely used for simulation of electronic circuits, their algorithms support linear and non-linear lumped components and they can manipulate an expressive amount of encapsulated elements. Despite the great potential of these simulators based on SPICE in the analysis of quasi-static electromagnetic field interaction, that is, at low frequency, these simulators are limited when applied to microwave hybrid circuits in which there are both lumped and distributed elements. Usually the spatial discretization of the FDTD (Finite-Difference Time-Domain) method is done according to the actual size of the element under analysis. After spatial discretization, the Courant Stability Criterion calculates the maximum temporal discretization accepted for such spatial discretization and for the propagation velocity of the wave. This criterion guarantees the stability conditions for the leapfrogging of the Yee algorithm; however, it is known that for the field update, the stability of the complete FDTD procedure depends on factors other than just the stability of the Yee algorithm, because the FDTD program needs other algorithms in order to be useful in engineering problems. Examples of these algorithms are Absorbent Boundary Conditions (ABCs), excitation sources, subcellular techniques, grouped elements, and non-uniform or non-orthogonal meshes. In this work, the influence of the stability of the FDTD method in the modeling of concentrated elements such as resistive sources, resistors, capacitors, inductors and diode will be evaluated. In this paper is proposed, therefore, the electromagnetic modeling of electronic components in order to create models that satisfy the needs for simulations of circuits in ultra-wide frequencies. The models of the resistive source, the resistor, the capacitor, the inductor, and the diode will be evaluated, among the mathematical models for lumped components in the LE-FDTD method (Lumped-Element Finite-Difference Time-Domain), through the parametric analysis of Yee cells size which discretizes the lumped components. In this way, it is sought to find an ideal cell size so that the analysis in FDTD environment is in greater agreement with the expected circuit behavior, maintaining the stability conditions of this method. Based on the mathematical models and the theoretical basis of the required extensions of the FDTD method, the computational implementation of the models in Matlab® environment is carried out. The boundary condition Mur is used as the absorbing boundary of the FDTD method. The validation of the model is done through the comparison between the obtained results by the FDTD method through the electric field values and the currents in the components, and the analytical results using circuit parameters.

Keywords: hybrid circuits, LE-FDTD, lumped element, parametric analysis

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Authors: Ahmad Zahran, Ahmed Herzallah, Ahmad Ahmad, Mahran Quraan

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Generation of high DC voltages is necessary for testing the insulation material of high voltage AC transmission lines with long lengths. The harmonic and ripple contents of the output DC voltage supplied by high voltage DC circuits require the use of costly capacitors to smooth the output voltage after rectification. This paper proposes a new modular multiplier high voltage DC generator with embedded Cockcroft-Walton circuits that achieve a negligible harmonic and ripple contents of the output DC voltage without the need for costly filters to produce a nearly constant output voltage. In this new topology, Cockcroft-Walton modules are connected in series to produce a high DC output voltage. The modules are supplied by low input AC voltage sources that have the same magnitude and frequency and shifted from each other by a certain angle to eliminate the harmonics from the output voltage. The small ripple factor is provided by the smoothing column capacitors and the phase shifted input voltages of the cascaded modules. The constituent harmonics within each module are determined using Fourier analysis. The viability of the proposed DC generator for testing purposes and the effectiveness of the cascaded connection are confirmed by numerical simulations using MATLAB/Simulink.

Keywords: Cockcroft-Walton circuit, harmonics, ripple factor, HVDC generator

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Authors: Mudavath Raju, Bhaskar Gugulothu, B. Rajendra Naik

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The rapid advances in Very Large Scale Integration (VLSI) technology has resulted in the reduction of minimum feature size to sub-quarter microns and switching time in tens of picoseconds or even less. As a result, the degradation of high-speed digital circuits due to signal integrity issues such as coupling effects, clock feedthrough, crosstalk noise and delay uncertainty noise. Crosstalk noise in VLSI interconnects is a major concern and reduction in VLSI interconnect has become more important for high-speed digital circuits. It is the most effectively considered in Deep Sub Micron (DSM) and Ultra Deep Sub Micron (UDSM) technology. Increasing spacing in-between aggressor and victim line is one of the technique to reduce the crosstalk. Guard trace or shield insertion in-between aggressor and victim is also one of the prominent options for the minimization of crosstalk. In this paper, far end crosstalk noise is estimated with mutual inductance and capacitance RLC interconnect model. Also investigated the extent of crosstalk in capacitive and inductively coupled interconnects to minimizes the same through shield insertion technique.

Keywords: VLSI, interconnects, signal integrity, crosstalk, shield insertion, guard trace, deep sub micron

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Authors: Nada Verdel, Tomaz Rijavec, Albin Pintar, Ales Lapanje

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Objectives: White water circuits of woodfree paper mills contain suspended, dissolved, and colloidal particles, such as cellulose, starch, paper sizings, and dyes. By closing the white water circuits, these particles start to accumulate and affect the production. Due to high amount of organic matter that scavenge radicals and adsorbs onto catalyst surfaces, treatment of white water with photocatalysis is inappropriate. The most suitable approach should be bioaugmentation-assisted bioremediation. Accordingly, objectives were: - to isolate bacteria capable of degrading organic compounds used for the papermaking process - to select the most active bacteria for bioaugmentation. Status: The state-of-the-art of bioaugmentation of pulp and paper mill effluents is mostly based on biodegradation of lignin. Whereas in white water circuits of woodfree paper mills only papermaking compounds are present. As far as one can tell from the literature, the study on degradation activities of bacteria for all possible compounds of the papermaking process is a novelty. Methodology: The main parameters of the selected white water were systematically analyzed during a period of two months. Bacteria were isolated on selective media with particular carbon source. Organic substances used as carbon source either enter white water circuits as base paper or as recycled broke. The screening of bacterial activities for starch, cellulose, latex, polyvinyl alcohol, alkyl ketene dimers, and resin acids was followed by addition of lugol. Degraders of polycyclic aromatic dyes were selected by cometabolism tests; cometabolism is simultaneous biodegradation of two compounds, in which the degradation of the second compound depends on the presence of the first. The obtained strains were identified by 16S rRNA sequencing. Findings: 335 autochthonous strains were isolated on plates with selected carbon source. The isolated strains were selected according to degradation of the particular carbon source. The ultimate degraders of cationic starch, cellulose, and sizings are Pseudomonas sp. NV-CE12-CF and Aeromonas sp. NV-RES19-BTP. The most active strains capable of degrading azo dyes are Aeromonas sp. NV-RES19-BTP and Sphingomonas sp. NV-B14-CF. Klebsiella sp. NV-Y14A-BTP degrade polycyclic aromatic direct blue 15 and also yellow dye, Agromyces sp. NV-RED15A-BF and Cellulosimicrobium sp. NV-A4-BF are specialists for whitener and Aeromonas sp. NV-RES19-BTP is general degrader of all compounds. To the white water adapted bacteria were isolated and selected according to their degradation activities for particular organic substances. Mostly isolated bacteria are specialized to lower the competition in the microbial community. Degraders of readily-biodegradable compounds do not degrade recalcitrant polycyclic aromatic dyes and vice versa. General degraders are rare.

Keywords: bioaugmentation, biodegradation of azo dyes, cometabolism, smart wastewater treatment technologies

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Authors: Felipe M. de Freitas, Ícaro V. Soares, Lucas L. L. Fortes, Sandro T. M. Gonçalves, Úrsula D. C. Resende

Abstract:

There is a dispersed energy in Radio Frequencies (RF) that can be reused to power electronics circuits such as: sensors, actuators, identification devices, among other systems, without wire connections or a battery supply requirement. In this context, there are different types of energy harvesting systems, including rectennas, coil systems, graphene and new materials. A secondary step of an energy harvesting system is the rectification of the collected signal which may be carried out, for example, by the combination of one or more Schottky diodes connected in series or shunt. In the case of a rectenna-based system, for instance, the diode used must be able to receive low power signals at ultra-high frequencies. Therefore, it is required low values of series resistance, junction capacitance and potential barrier voltage. Due to this low-power condition, voltage multiplier configurations are used such as voltage doublers or modified bridge converters. Lowpass filter (LPF) at the input, DC output filter, and a resistive load are also commonly used in the rectifier design. The electronic circuits projects are commonly analyzed through simulation in SPICE (Simulation Program with Integrated Circuit Emphasis) environment. Despite the remarkable potential of SPICE-based simulators for complex circuit modeling and analysis of quasi-static electromagnetic fields interaction, i.e., at low frequency, these simulators are limited and they cannot model properly applications of microwave hybrid circuits in which there are both, lumped elements as well as distributed elements. This work proposes, therefore, the electromagnetic modelling of electronic components in order to create models that satisfy the needs for simulations of circuits in ultra-high frequencies, with application in rectifiers coupled to antennas, as in energy harvesting systems, that is, in rectennas. For this purpose, the numerical method FDTD (Finite-Difference Time-Domain) is applied and SPICE computational tools are used for comparison. In the present work, initially the Ampere-Maxwell equation is applied to the equations of current density and electric field within the FDTD method and its circuital relation with the voltage drop in the modeled component for the case of lumped parameter using the FDTD (Lumped-Element Finite-Difference Time-Domain) proposed in for the passive components and the one proposed in for the diode. Next, a rectifier is built with the essential requirements for operating rectenna energy harvesting systems and the FDTD results are compared with experimental measurements.

Keywords: energy harvesting system, LE-FDTD, rectenna, rectifier, wireless power systems

Procedia PDF Downloads 101

Authors: Tugba Tosun, Mert Tosun

Abstract:

Cooling system performance and energy consumption in the bypass two-circuit cycle have been studied experimentally to find optimum evaporator type and geometry, capillary tube diameter and capillary length. Two types of evaporators, such as wire on the tube and finned tube evaporators were used for the experiments in the fresh food compartment. As capillary tube inner diameter and total length; 0.66 mm and 0.8mm, and 3000 mm and 3500 mm were selected as parameters, respectively. Experiments were performed at the 25⁰C ambient temperature while the average temperature of the fresh food compartment is kept at 5⁰C and the highest package temperature of the freezer compartment is kept at -18⁰C, which are defined in IEC 62552 European standard. The Design of Experiments (DOE) technique which is six sigma method has been used to indicate of effective parameters in the bypass two-circuit cycle. The experimental results revealed that the most effective parameter of the system is the evaporator type. Finned tube evaporator with 12 tube passes was found as the best option for the bypass two-circuit refrigeration cycle among the 8 different opportunities. The optimum cooling performance and the lowest energy consumption were provided with 0.66 mm capillary tube inner diameter and 3500 mm capillary tube length.

Keywords: capillary tube, energy consumption, heat exchanger, refrigerator, separate cooling circuits

Procedia PDF Downloads 133

Authors: A. Oukaira, A. Lakhssassi, O. Ettahri

Abstract:

To make a good thermal management in an ABDM (Adapter Board Detector Module) card, we must first control temperature and its gradient from the first step in the design of integrated circuits ASIC of our complex system. In this paper, our main goal is to develop and validate the thermal stability in order to get an idea of the flow of heat around the ASIC in transient and thus address the thermal issues for integrated circuits at the ABDM card. However, we need heat sources simulations for ABDM card to establish its thermal mapping. This led us to perform simulations at each ASIC that will allow us to understand the thermal ABDM map and find real solutions for each one of our complex system that contains 36 ABDM map, taking into account the different layers around ASIC. To do a transient simulation under NISA, we had to build a function of power modulation in time TIMEAMP. The maximum power generated in the ASIC is 0.6 W. We divided the power uniformly in the volume of the ASIC. This power was applied for 5 seconds to visualize the evolution and distribution of heat around the ASIC. The DBC (Dirichlet Boundary conditions) method was applied around the ABDM at 25°C and just after these simulations in NISA tool we will validate them by COMSOL tool, wich is a numerical calculation software for a modular finite element for modeling a wide variety of physical phenomena characterizing a real problem. It will also be a design tool with its ability to handle 3D geometries for complex systems.

Keywords: ABDM, APD, thermal mapping, complex system

Procedia PDF Downloads 242

Authors: Jianshu Yang, Delphine Sordes, Marek Kolmer, Christian Joachim

Abstract:

Nanoelectronics, for example the calculating circuits integrating at molecule scale logic gates, atomic scale circuits, has been constructed and investigated recently. A major challenge is their functional properties characterization because of the connecting problem from atomic scale to micrometer scale. New experimental instruments and new processes have been proposed therefore. To satisfy a precisely measurement at atomic scale and then connecting micrometer scale electrical integration controller, the technique improvement is kept on going. Our new machine, a low temperature high vacuum four scanning tunneling microscope, as a customer required instrument constructed by Omicron GmbH, is expected to be scaling down to atomic scale characterization. Here, we will present our first testified results about the performance of this new instrument. The sample we selected is Au(111) surface. The measurements have been taken at 4.2 K. The atomic resolution surface structure was observed with each of four scanners with noise level better than 3 pm. With a tip-sample distance calibration by I-z spectra, the sample conductance has been derived from its atomic locally I-V spectra. Furthermore, the surface conductance measurement has been performed using two methods, (1) by landing two STM tips on the surface with sample floating; and (2) by sample floating and one of the landed tips turned to be grounding. In addition, single atom manipulation has been achieved with a modified tip design, which is comparable to a conventional LT-STM.

Keywords: low temperature ultra-high vacuum four scanning tunneling microscope, nanoelectronics, point contact, single atom manipulation, tunneling resistance

Procedia PDF Downloads 257