Search results for: GATE Developer

Authors: Aleksey Fedorov

Abstract:

Building a scalable platform for quantum computing remains one of the most challenging tasks in quantum science and technologies. However, the implementation of most important quantum operations with qubits (quantum analogues of classical bits), such as multiqubit Toffoli gate, requires either a polynomial number of operation or a linear number of operations with the use of ancilla qubits. Therefore, the reduction of the number of operations in the presence of scalability is a crucial goal in quantum information processing. One of the most elegant ideas in this direction is to use qudits (multilevel systems) instead of qubits and rely on additional levels of qudits instead of ancillas. Although some of the already obtained results demonstrate a reduction of the number of operation, they suffer from high complexity and/or of the absence of scalability. We show a strong reduction of the number of operations for the realization of the Toffoli gate by using qudits for a scalable multi-qudit processor. This is done on the basis of a general relation between the dimensionality of qudits and their topology of connections, that we derived.

Keywords: quantum computing, qudits, Toffoli gates, gate decomposition

Procedia PDF Downloads 146

Authors: Khadijah Hasim, Achmad Fauzan Firdaus, Choirunnisa

Abstract:

Waqf land which previously was idle assets can be built on top of a building that is a means for people to conduct business. Nadzir (waqf managers) lease of waqf lands it manages, the agreed rental fee, which is payable in the form of the building, not in cash. After standing building, the developer will lease to interested companies. Given the magnitude of the beginning funds needed, The company later issuing sukuk al-intifa on the trading floor. With this sukuk issuance, the company has sufficient capital to begin operations and pay obligations of the rental fee to the developer each year. Building that had stood trade area will be established (Micro, Small, Middle Entreprises) MSMEs. It is expected that through the sukuk al-intifa, can help to make waqf land previously unproductive due to lack of capital to be very beneficial and help awaken the people of Indonesian MSMEs

Keywords: Sukuk Al-Intifa, MSMEs, waqf land, underlying asset

Procedia PDF Downloads 470

Authors: A. Ardianto, M. A. Putera Agung, S. Pramusandi

Abstract:

Power waterway is one of dam structures and as an intake vertical tunnel or well function for hydroelectric power plants in Jatigede area, Sumedang, West Java. Gate shaft is also one of parts the power waterway system. The paper concerns some consideration in determining a critical state parameter on the back stability analysis of gate shaft or excavation wall stability during excavation. Study analysis was carried out using without and with reinforcement system. Results study showed that reinforcement shaft could reduce the total displacement and safety factor could increases significantly. Based on the back calculation results, it was recommended to install some reinforcement materials and drainage system to reduce pore water pressure.

Keywords: power waterway, reinforcement, displacement, safety

Procedia PDF Downloads 410

Authors: Poonam A. Trambadia, Ashish V. Trambadia

Abstract:

The architecture of sultanate period of Ahmedabad had evolved just before the establishment of Mughal rule in North India. After shifting the capital of the kingdom from Patan to Ahmedabad, when the buildings and structures were being built, an interesting cultural blend happened in architecture. Many sultanate buildings in Ahmedabad historic city have resemblance with Patan including the names. Outer fortification walls and Gates were built during the rule of the third ruler in the late 15th century. All the gates had sandstone slabs supported by three arched entrance in sandstone with wooden shutter. A restoration project of Khanpur Gate was initiated in 2016. The paper identifies some evidences and some hidden layers of structures as important elements of cultural interchange while some were just forgotten in the process. The recycling of pre-existing elements of structures are examined and compared. There were layers uncovered that were hidden behind later repairs using traditional brick arch, which was taken out in the process. As the gate had partially collapsed, the restoration included piece by piece dismantling and restoring in the same sequence wherever required. The recycled materials found in the process were recorded and provided the basis for this study. The gate after this discovery sets a new example of fortification Gate built in Sultanate era. The comparison excludes Maratha and British Period Gates to avoid further confusion and focuses on 15th – 16th century sultanate architecture of Ahmedabad.

Keywords: Ahmedabad World Heritage, fortification, Indo-Islamic style, Sultanate architecture, cultural interchange

Procedia PDF Downloads 116

Authors: Kianoosh Ahadi, Mustafa Ergil

Abstract:

In this study, the event of vibrations caused by vortexes and the distribution of induced hydrodynamic forces due to vortexes on the sliding gate valves has been investigated. For this reason, a sliding valve with the help of computational fluid dynamics (CFD) software was simulated in two-dimensional )2D(, where the flow and turbulence equations were solved for three different valve openings (full, half, and 16.7 %) models. The variety of vortexes formed within the vicinity of the valve structure was investigated based on time where the trend of fluctuations and their occurrence regions have been detected. From the gathered solution dataset of the numerical simulations, the pressure coefficient (CP), the lift force coefficient (CL), the drag force coefficient (CD), and the momentum coefficient due to hydrodynamic forces (CM) were examined, and relevant figures were generated were from these results, the vortex-induced vibrations were analyzed.

Keywords: induced vibrations, computational fluid dynamics, sliding gate valves, vortexes

Procedia PDF Downloads 120

Authors: Nikhil Jain, Yang Xu, Bin Yu

Abstract:

Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

Procedia PDF Downloads 364

Authors: Syakirin O. Yong, Nasrudin A. Rahim, Bilal M. Eid, Buray Tankut

Abstract:

The aim of this paper is to develop an ultra-fast gate driver for Silicon Carbide (SiC) based switching device applications such as AC/DC DC/AC converters. Wide bandgap semiconductors such as SiC switches are growing rapidly nowadays due to their numerous capabilities such as faster switching, higher power density and higher voltage level. Wide band-gap switches can work properly on high frequencies such 50-250 kHz which is very useful for many power electronic applications such as solar inverters. Increasing the frequency minimizes the output filter size and system complexity however, this causes huge spike between MOSFET’s drain and source leg which leads to the failure of MOSFET if the voltage rating is exceeded. This paper investigates and concludes the optimum design for a gate drive board for SiC MOSFET switches without causing spikes and noises.

Keywords: PV system, lithium-ion, charger, constant current, constant voltage, renewable energy

Procedia PDF Downloads 156

Authors: Indre Brazauskaite, Vilte Auruskeviciene

Abstract:

The paper explores the Stage-Gate framework application for innovation maturity among small and medium-sized enterprises (SMEs). Innovation management becomes an essential business survival process for all sizes of organizations that can be evaluated and audited systemically. This research systemically defines and assesses the innovation process from the perspective of the company’s top management. Empirical research explores attitudes and existing practices of innovation management in SMEs in Baltic countries. It structurally investigates the current innovation management practices, level of standardization, and potential challenges in the area. Findings allow to structure of existing practices based on an institutionalized model and contribute to a more advanced understanding of the innovation process among SMEs. Practically, findings contribute to advanced decision-making and business planning in the process.

Keywords: innovation measure, innovation process, SMEs, stage-gate framework

Procedia PDF Downloads 98

Authors: Syamsul Syafiq, Maslina Daud, Hafizah Hasan, Ahmad Zairi, Shazil Imri, Ezaini Akmar, Norbazilah Rahim

Abstract:

Over recent years, web development has changed significantly. Driven largely by the rise of trends like mobiles, the world of development is rapidly evolving. The rise of the Internet makes web applications crucial nowadays. The web application has been an interface for a company and one of the ways they present their portfolio to the client. On the other hand, the web has become part of the file management system which takes over the role of paper. Due to high demand in web applications, developers are required to develop a web application that are cost-effective, secure and well coded. A framework has been proposed to develop an application rather than using library style development. The framework is helping the developer in creating the structure of a web automatically. This paper will compare the advantages and disadvantages of web development using framework against library-style development. This comparison is based on a previous research paper focusing on two main indicators, which are the impact to management and impact to the developer.

Keywords: framework, library style development, web application development, traditional web, static web, dynamic web

Procedia PDF Downloads 224

Authors: G. S. Dangayach, Gaurav Gaurav, Alok Bihari Singh

Abstract:

The popularity of vehicles in both industrialized and developing economies led to a rise in the production of tyres. People have become increasingly concerned about the tyre industry's possible environmental impact in the last two decades. The life cycle assessment (LCA) methodology was used to assess the environmental impacts of industrial tyres throughout their life cycle, which included four stages: manufacture, transportation, consumption, and end-of-life. The majority of prior studies focused on tyre recycling and disposal. Only a few studies have been conducted on the environmental impact of tyre production process. LCA methodology was employed to determine the environmental impact of tyre manufacture process (gate to gate) at an Indian firm. Comparative analysis was also conducted to identify the environmental hotspots in various stages of tire manufacturing. This study is limited to gate-to-gate analysis of manufacturing processes with the functional unit of a single tyre weighing 50 kg. GaBi software was used to do both qualitative and quantitative analysis. Different environmental impact indicators are measured in terms of CO2, SO2, NOx, GWP (global warming potential), AP (acidification potential), EP (eutrophication potential), POCP (photochemical oxidant formation potential), and HTP (toxic human potential). The results demonstrate that the major contributor to environmental pollution is electricity. The Banbury process has a very high negative environmental impact, which causes respiratory problems to workers and operators.

Keywords: life cycle assessment (LCA), environmental impact indicators, tyre manufacturing process, environmental impact assessment

Procedia PDF Downloads 151

Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

Procedia PDF Downloads 511

Authors: Emmanuel Mkambankhani, Tiwonge Manda

Abstract:

Software platform architecture includes system components, their relationships, and design, as well as evolution principles. Software architecture and documentation affect a platform's customizability and openness to external innovators, thus affecting developer productivity. Malawi Point of Care (POC) Electronic Medical Records System (EMRS) follows some architectural design standards, but it lacks third-party innovators and is difficult to customize as compared to CommCare and District Health Information System 2 (DHIS2). Improving software architecture and documentation for the Malawi POC will increase productivity and third-party contributions. A conceptual framework based on Generativity and Boundary Resource Model (BRM) was used to compare the three platforms. Interviews, observations, and document analysis were used to collect primary and secondary data. Themes were found by analyzing qualitative and quantitative data, which led to the following results. Configurable, flexible, and cross-platform software platforms and the availability of interfaces (Boundary Resources) that let internal and external developers interact with the platform's core functionality, hence boosting developer productivity. Furthermore, documentation increases developer productivity, while its absence inhibits the use of resources. The study suggests that the architecture and openness of the Malawi POC EMR software platform will be improved by standardizing web application program interfaces (APIs) and making interfaces that can be changed by the user. In addition, increasing the availability of documentation and training will improve the use of boundary resources, thus improving internal and third-party development productivity.

Keywords: health systems, configurable platforms, software architecture, software documentation, software development productivity

Procedia PDF Downloads 88

Authors: Mehdi Moayyedian, Kazem Abhary, Romeo Marian

Abstract:

This paper presents an evaluation of a plastic defect in injection molding before it occurs in the process; it is known as the short shot defect. The evaluation of different parameters which affect the possibility of short shot defect is the aim of this paper. The analysis of short shot possibility is conducted via SolidWorks Plastics and Taguchi method to determine the most significant parameters. Finite Element Method (FEM) is employed to analyze two circular flat polypropylene plates of 1 mm thickness. Filling time, part cooling time, pressure holding time, melt temperature and gate type are chosen as process and geometric parameters, respectively. A methodology is presented herein to predict the possibility of the short-shot occurrence. The analysis determined melt temperature is the most influential parameter affecting the possibility of short shot defect with a contribution of 74.25%, and filling time with a contribution of 22%, followed by gate type with a contribution of 3.69%. It was also determined the optimum level of each parameter leading to a reduction in the possibility of short shot are gate type at level 1, filling time at level 3 and melt temperature at level 3. Finally, the most significant parameters affecting the possibility of short shot were determined to be melt temperature, filling time, and gate type.

Keywords: injection molding, plastic defects, short shot, Taguchi method

Procedia PDF Downloads 218

Authors: Kiurski S. Jelena, Oros B. Ivana, Kecić S. Vesna, Kovačević M. Ilija, Aksentijević M. Snežana

Abstract:

The adsorption efficiency of various adsorbents for the removal of Zn(II) ions from the waste printing developer was studied in laboratory batch mode. The maximum adsorption efficiency of 94.1% was achieved with unfired clay pellets size (d≈15 mm). The obtained values of adsorption efficiency was subjected to the independent samples t-test in order to investigate the statistically significant differences of the investigated adsorbents for the effective removal of Zn(II) ions from the waste printing developer. The most statistically significant differences of adsorption efficiencies for Zn(II) ions removal were obtained between unfired clay pellets size (d≈15 mm) and activated carbon (|t|= 6.909), natural zeolite (|t|= 10.380), mixture of activated carbon and natural zeolite (|t|= 9.865), bentonite (|t|= 6.159), fired clay (|t|= 6.641), fired clay pellets size (d≈5 mm) (|t|= 6.678), fired clay pellets size (d≈8 mm) (|t|= 3.422), respectively.

Keywords: Adsorption efficiency, adsorbent, statistical analysis, zinc ion.

Procedia PDF Downloads 389

Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

Abstract:

A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: high voltage, IGBT, solid state switch, bipolar transistor

Procedia PDF Downloads 552

Authors: Samson Mil'shtein, Dhawal Asthana, Benjamin Sullivan

Abstract:

The wide energy gap of GaN is the major parameter justifying the design and fabrication of high-power electronic components made of this material. However, the existence of a piezo-electrics in nature sheet charge at the AlGaN/GaN interface complicates the control of carrier injection into the intrinsic channel of GaN HEMTs (High Electron Mobility Transistors). As a result, most of the transistors created as R&D prototypes and all of the designs used for mass production are D-mode devices which introduce challenges in the design of integrated circuits. This research presents the design and modeling of an E-mode GaN HEMT with a very low turn-on voltage. The proposed device includes two critical elements allowing the transistor to achieve zero conductance across the channel when Vg = 0V. This is accomplished through the inclusion of an extremely thin, 2.5nm intrinsic Ga₀.₇₄Al₀.₂₆N spacer layer. The added spacer layer does not create piezoelectric strain but rather elastically follows the variations of the crystal structure of the adjacent GaN channel. The second important factor is the design of a gate metal with a high work function. The use of a metal gate with a work function (Ni in this research) greater than 5.3eV positioned on top of n-type doped (Nd=10¹⁷cm⁻³) Ga₀.₇₄Al₀.₂₆N creates the necessary built-in potential, which controls the injection of electrons into the intrinsic channel as the gate voltage is increased. The 5µm long transistor with a 0.18µm long gate and a channel width of 30µm operate at Vd=10V. At Vg =1V, the device reaches the maximum drain current of 0.6mA, which indicates a high current density. The presented device is operational at frequencies greater than 10GHz and exhibits a stable transconductance over the full range of operational gate voltages.

Keywords: compound semiconductors, device modeling, enhancement mode HEMT, gallium nitride

Procedia PDF Downloads 260

Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: local interconnect network, controller, transceiver, processor

Procedia PDF Downloads 288

Authors: Karan R. Chavan, Paula Saavalainen, Kumudini V. Marathe, Riitta L. Keiski, Ganapati D. Yadav

Abstract:

Co-contamination of groundwaters by arsenic in different forms is often observed around the globe. Arsenic is introduced into the waters by several mechanisms and different technologies are proposed and practiced for effective removal. The assessment of three prominent technologies, namely, adsorption, ion exchange and nanofiltration was carried out in this study based on lifecycle methodology. The life of the technologies was divided into two stages: cradle to gate (C-G) and gate to gate (G-G), in order to find out the impacts in different categories of environmental burdens, human health and resource consumption. Life cycle inventory was estimated by use of models and design equations concerning with the different technologies. Regeneration was considered for each technology and over the course of its full lifetime. The impact values of adsorption technology for the C-G stage are greater by thousand times (103) and million times (106) compared to ion exchange and nanofiltration technologies, respectively. The impact of G-G stage of the lifecycle is the major contributor of the impact for all the 3 technologies due to electricity consumption during the operation. Overall, the ion Exchange technology fares well in this study of removal of As (V) only.

Keywords: arsenic, nanofiltration, lifecycle assessment, membrane technology

Procedia PDF Downloads 245

Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

Abstract:

Gate Assignment Problem (GAP) is one of the most substantial issues in airport operation. In principle, GAP intends to maintain the maximum capacity of the airport through the best possible allocation of the resources (gates) in order to reach the optimum outcome. The problem involves a wide range of dependent and independent resources and their limitations, which add to the complexity of GAP from both theoretical and practical perspective. In this study, GAP was mathematically formulated as a three-objective problem. The preliminary goal of multi-objective formulation was to address a higher number of objectives that can be simultaneously optimized and therefore increase the practical efficiency of the final solution. The problem is solved by applying the second version of Non-dominated Sorting Genetic Algorithm (NSGA-II). Results showed that the proposed mathematical model could address most of major criteria in the decision-making process in airport management in terms of minimizing both airport/airline cost and passenger walking distance time. Moreover, the proposed approach could properly find acceptable possible answers.

Keywords: airport management, gate assignment problem, mathematical modeling, genetic algorithm, NSGA-II

Procedia PDF Downloads 299

Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

Abstract:

Assigning aircrafts’ activities to appropriate gates is one the most challenging issues in airport authorities’ multiple criteria decision making. The potential financial loss due to imbalances of demand and supply in congested airports, higher occupation rates of gates, and the existing restrictions to expand facilities provide further evidence for the need for an optimal supply allocation. Passengers walking distance, towing movements, extra fuel consumption (as a result of awaiting longer to taxi when taxi conflicts happen at the apron area), etc. are the major traditional components involved in GAP models. In particular, the total cost associated with gate assignment problem highly depends on the airport terminal layout. The study herein presents a well-elaborated literature review on the topic focusing on major concerns, applicable variables and objectives, as well as proposing a three-objective mathematical model for the gate assignment problem. The model has been tested under different concourse layouts in order to check its performance in different scenarios. Results revealed that terminal layout pattern is a significant parameter in airport and that the proposed model is capable of dealing with key constraints and objectives, which supports its practical usability for future decision making tools. Potential solution techniques were also suggested in this study for future works.

Keywords: airport management, terminal layout, gate assignment problem, mathematical modeling

Procedia PDF Downloads 229

Authors: A.N. Moulay Khatir, A. Guen-Bouazza, B. Bouazza

Abstract:

SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator to investigate the influence of fins number on corner effect by analyzing its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current for SOI-single-fin FET, three-fin and five-fin, and we provide a comparison with a Trigate SOI Multi-FinFET structure.

Keywords: SOI, FinFET, corner effect, dual-gate, tri-gate, Multi-Fin FET

Procedia PDF Downloads 475

Authors: Xuerui Niu, Bolin Wang, Xinchuang Zhang, Xiaohua Ma, Bin Hou, Ling Yang

Abstract:

The application of discrete GaN-based power switches requires the collaboration of silicon-based peripheral circuit structures. However, the packages and interconnection between the Si and GaN devices can introduce parasitic effects to the circuit, which has great impacts on GaN power transistors. GaN-based monolithic power integration technology is an emerging solution which can improve the stability of circuits and allow the GaN-based devices to achieve more functions. Complementary logic circuits consisting of GaN-based E-mode p-channel heterostructure field-effect transistors (p-HFETs) and E-mode n-channel HEMTs can be served as the gate drivers. E-mode p-HFETs with recessed gate have attracted increasing interest because of the low leakage current and large gate swing. However, they suffer from a poor interface between the gate dielectric and polarized nitride layers. The reliability of p-HFETs is analyzed and discussed in this work. In circuit applications, the inverter is always operated with dynamic gate voltage (VGS) rather than a constant VGS. Therefore, dynamic electrical stress has been simulated to resemble the operation conditions for E-mode p-HFETs. The dynamic electrical stress condition is as follows. VGS is a square waveform switching from -5 V to 0 V, VDS is fixed, and the source grounded. The frequency of the square waveform is 100kHz with the rising/falling time of 100 ns and duty ratio of 50%. The effective stress time is 1000s. A number of stress tests are carried out. The stress was briefly interrupted to measure the linear IDS-VGS, saturation IDS-VGS, As VGS switches from -5 V to 0 V and VDS = 0 V, devices are under negative-bias-instability (NBI) condition. Holes are trapped at the interface of oxide layer and GaN channel layer, which results in the reduction of VTH. The negative shift of VTH is serious at the first 10s and then changes slightly with the following stress time. However, different phenomenon is observed when VDS reduces to -5V. VTH shifts negatively during stress condition, and the variation in VTH increases with time, which is different from that when VDS is 0V. Two mechanisms exists in this condition. On the one hand, the electric field in the gate region is influenced by the drain voltage, so that the trapping behavior of holes in the gate region changes. The impact of the gate voltage is weakened. On the other hand, large drain voltage can induce the hot holes generation and lead to serious hot carrier stress (HCS) degradation with time. The poor-quality interface between the oxide layer and GaN channel layer at the gate region makes a major contribution to the high-density interface traps, which will greatly influence the reliability of devices. These results emphasize that the improved etching and pretreatment processes needs to be developed so that high-performance GaN complementary logics with enhanced stability can be achieved.

Keywords: GaN-based E-mode p-HFETs, dynamic electric stress, threshold voltage, monolithic power integration technology

Procedia PDF Downloads 90

Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center

Procedia PDF Downloads 155

Authors: Ghania Zerari, Abderrezak Guessoum, Rachid Beguenane

Abstract:

This paper introduces high-performance architecture for fully parallel stochastic Low-Density Parity-Check (LDPC) field programmable gate array (FPGA) based LDPC decoder. The new approach is designed to decrease the decoding latency and to reduce the FPGA logic utilisation. To accomplish the target logic utilisation reduction, the routing of the proposed sub-variable node (VN) internal memory is designed to utilize one slice distributed RAM. Furthermore, a VN initialization, using the channel input probability, is achieved to enhance the decoder convergence, without extra resources and without integrating the output saturated-counters. The Xilinx FPGA implementation, of IEEE 802.3an standard LDPC code, shows that the proposed decoding approach attain high performance along with reduction of FPGA logic utilisation.

Keywords: low-density parity-check (LDPC) decoder, stochastic decoding, field programmable gate array (FPGA), IEEE 802.3an standard

Procedia PDF Downloads 297

Authors: Deepika Sharma, Bal Krishan

Abstract:

In this paper, the structure of N-channel VDMOS was designed and analyzed using Silvaco TCAD tools by varying N+ source doping concentration, P-Body doping concentration, gate oxide thickness and the diffuse time. VDMOS is considered to be ideal power switches due to its high input impedance and fast switching speed. The performance of the device was analyzed from the Ids vs Vgs curve. The electrical characteristics such as threshold voltage, gate oxide thickness and breakdown voltage for the proposed device structures were extarcted. Effect of epitaxial layer on various parameters is also observed.

Keywords: on-resistance, threshold voltage, epitaxial layer, breakdown voltage

Procedia PDF Downloads 327

Authors: Chingwen Yeh, Yu Ru Chen

Abstract:

This paper aims to explore the growth and development of children in the creative dance class of Cloud Gate Dance School in Taichung Taiwan. Professor Chingwen Yeh’s qualitative research method was applied in this study. First of all, application of Dalcroze Eurhythmic teaching materials such as music, teaching aids, speaking language through classroom situation was collected and exam. Second, the in-class observation on the participation of the young children's learning situation was recorded both by words and on video screen as the research data. Finally, data analysis was categorized into the following aspects: children's body movement coordination, children’s mind concentration and imagination and children’s verbal expression. Through the in-depth interviews with the in-class teachers, parents of participating children and other in class observers were conducted from time to time; this research found the children's body rhythm, language skills, and social learning growth were improved in certain degree through the creative dance training. These authors hope the study can contribute as the further research reference on the related topic.

Keywords: Cloud Gate Dance School, creative dance, Dalcroze, Eurhythmic

Procedia PDF Downloads 297

Authors: Mert Kıranç, Ekrem Duman, Murat Özbilen

Abstract:

In order to achieve new product development (NPD) activities on time and within budgetary constraints, the NPD managers need a well-designed methodology. This study intends to create an integrated project management methodology for the ones who focus on new product development projects. In the scope of the study, four different management systems are combined. These systems are called as 'Schedule-oriented Stage-Gate Method, Risk Management, Change Management and Earned Value Management'. New product development term is quite common in many different industries such as defense industry, construction, health care/dental, higher education, fast moving consumer goods, white goods, electronic devices, marketing and advertising and software development. All product manufacturers run against each other’s for introducing a new product to the market. In order to achieve to produce a more competitive product in the market, an optimum project management methodology is chosen, and this methodology is adapted to company culture. The right methodology helps the company to present perfect product to the customers at the right time. The benefits of proposed methodology are discussed as an application by a company. As a result, how the integrated methodology improves the efficiency and how it achieves the success of the project are unfolded.

Keywords: project, project management, management methodology, new product development, risk management, change management, earned value, stage-gate

Procedia PDF Downloads 312

Authors: Suruchi Saini, Hitender Kumar Tyagi

Abstract:

With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

Procedia PDF Downloads 61

Authors: M. Kessi

Abstract:

We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

Procedia PDF Downloads 181

Authors: Gashin Shahsavari, Gilles Arnaud-Fassetta, Alberto Campisano, Roberto Bertilotti, Fabien Riou

Abstract:

Sewer deposits have been identified as a major cause of dysfunctions in combined sewer systems regarding sewer management, which induces different negative consequents resulting in poor hydraulic conveyance, environmental damages as well as worker’s health. In order to overcome the problematics of sedimentation, flushing has been considered as the most operative and cost-effective way to minimize the sediments impacts and prevent such challenges. Flushing, by prompting turbulent wave effects, can modify the bed form depending on the hydraulic properties and geometrical characteristics of the conduit. So far, the dynamics of the bed-load during high-flow events in combined sewer systems as a complex environment is not well understood, mostly due to lack of measuring devices capable to work in the “hostile” in combined sewer system correctly. In this regards, a one-episode flushing issue from an opening gate valve with weir function was carried out in a trunk sewer in Paris to understanding its cleansing efficiency on the sediments (thickness: 0-30 cm). During more than 1h of flushing within 5 m distance in downstream of this flushing device, a maximum flowrate and a maximum level of water have been recorded at 5 m in downstream of the gate as 4.1 m3/s and 2.1 m respectively. This paper is aimed to evaluate the efficiency of this type of gate for around 1.1 km (from the point -50 m to +1050 m in downstream from the gate) by (i) determining bed grain-size distribution and sediments evolution through the sewer channel, as well as their organic matter content, and (ii) identifying sections that exhibit more changes in their texture after the flush. For the first one, two series of sampling were taken from the sewer length and then analyzed in laboratory, one before flushing and second after, at same points among the sewer channel. Hence, a non-intrusive sampling instrument has undertaken to extract the sediments smaller than the fine gravels. The comparison between sediments texture after the flush operation and the initial state, revealed the most modified zones by the flush effect, regarding the sewer invert slope and hydraulic parameters in the zone up to 400 m from the gate. At this distance, despite the increase of sediment grain-size rages, D50 (median grain-size) varies between 0.6 mm and 1.1 mm compared to 0.8 mm and 10 mm before and after flushing, respectively. Overall, regarding the sewer channel invert slope, results indicate that grains smaller than sands (< 2 mm) are more transported to downstream along about 400 m from the gate: in average 69% before against 38% after the flush with more dispersion of grain-sizes distributions. Furthermore, high effect of the channel bed irregularities on the bed material evolution has been observed after the flush.

Keywords: bed-load evolution, combined sewer systems, flushing efficiency, sediments transport

Procedia PDF Downloads 403