Search results for: low power CMOS design

Authors: Christos Konstantopoulos, Thomas Ussmueller

Abstract:

Digital low drop-out regulators, in contrast to analog counterparts, provide an architecture of sub-1 V regulation with low power consumption, high power efficiency, and system integration. Towards an optimized integration in the ultra-low-power system-on-chip Internet of Things architecture that is operated through a radio frequency energy harvesting scheme, the D-LDO regulator should constitute the main regulator that operates the master-clock and rest loads of the SoC. In this context, we present a D-LDO with linear search coarse regulation and asynchronous fine regulation, which incorporates an in-regulator clock generation unit that provides an autonomous, self-start-up, and power-efficient D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the frequency, this work presents a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of coarse regulation frequency. The design is implemented in a 55-nm Global Foundries CMOS process. With the purpose to validate the self-start-up capability of the presented D-LDO in the presence of ultra-low input power, an on-chip test-bench with an RF rectifier is implemented as well, which provides the RF to DC operation and feeds the D-LDO. Power efficiency and load regulation curves of the D-LDO are presented as extracted from the RF to regulated DC operation. The D-LDO regulator presents 83.6 % power efficiency during the RF to DC operation with a 3.65 uA load current and voltage regulator referred input power of -27 dBm. It succeeds 486 nA maximum quiescent current with CL 75 pF, the maximum current efficiency of 99.2%, and 1.16x power efficiency improvement compared to analog voltage regulator counterpart oriented to SoC IoT loads. Complementary, the transient performance of the D-LDO is evaluated under the transient droop test, and the achieved figure-of-merit is compared with state-of-art implementations.

Keywords: D-LDO, Internet of Things, RF energy harvesting, voltage regulators

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Authors: A. M. El-Akhdar, A. M. El-Tager, H. M. El-Hennawy

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This paper presents a broadband power divider with equal power division ratio. Two sections of transmission line transformers based on coupled microstrip lines are applied to obtain broadband performance. In addition, design methodology is proposed for the novel structure. A prototype is designed, simulated to operate in the band from 2.1 to 3.8 GHz to fulfill the requirements of 3G and 4G applications. The proposed structure features reduced size and less resistors than other conventional techniques. Simulation verifies the proposed idea and design methodology.

Keywords: power dividers, coupled lines, microstrip, 4G applications

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Authors: Debabrata Das

Abstract:

This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

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Authors: Hyungil Chae

Abstract:

This work presents a method to reduce spinning current of a Hall-effect sensor for low-power magnetic sensor applications. Spinning current of a Hall-effect sensor changes the direction of bias current periodically and can separate signals from DC-offset. The bias current is proportional to the sensor sensitivity but also increases the power consumption. To achieve both high sensitivity and low power consumption, the bias current can be pulse-width modulated. When the bias current duration Tb is reduced by a factor of N compared to the spinning current period of Tₛ/2, the total power consumption can be saved by N times. N can be large as long as the Hall-effect sensor settles down within Tb. The proposed scheme is implemented and simulated in a 0.18um CMOS process, and the power saving factor is 9.6 when N is 10. Acknowledgements: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (20160001360022003, Development of Hall Semi-conductor for Smart Car and Device).

Keywords: chopper stabilization, Hall-effect sensor, pulse width modulation, spinning current

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Ravi Kiran Jaladi, Ezz I. El-Masry

Abstract:

Emerging technologies such as ultra-wide band wireless access technology that operate at ultra-low power present several challenges due to their inherent design that limits the use of voltage-mode filters. Therefore, Continuous-time current-mode (CTCM) filters have become very popular in recent times due to the fact they have a wider dynamic range, improved linearity, and extended bandwidth compared to their voltage-mode counterparts. The goal of this research is to develop analog filters which are suitable for the current scaling CMOS technologies. Bulk-driven MOSFET is one of the most popular low power design technique for the existing challenges, while other techniques have obvious shortcomings. In this work, a CTCM Gate-driven (GD) differentiator has been presented with a frequency range from dc to 100MHz which operates at very low supply voltage of 0.7 volts. A novel CTCM Bulk-driven (BD) differentiator has been designed for the first time which reduces the power consumption multiple times that of GD differentiator. These GD and BD differentiator has been simulated using CADENCE TSMC 65nm technology for all the bilinear and biquadratic band-pass frequency responses. These basic building blocks can be used to implement the higher order filters. A 6th order cascade CTCM Chebyshev band-pass filter has been designed using the GD and BD techniques. As a conclusion, a low power GD and BD 6th order chebyshev stagger-tuned band-pass filter was simulated and all the parameters obtained from all the resulting realizations are analyzed and compared. Monte Carlo analysis is performed for both the 6th order filters and the results of sensitivity analysis are presented.

Keywords: bulk-driven (BD), continuous-time current-mode filters (CTCM), gate-driven (GD)

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Authors: Spyridon Nikolaidis

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A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: Idris Elfeituri

Abstract:

In the current study, energy and exergy analysis of a 65 MW steam power plant was carried out. This study investigated the effect of variations of overall conductance of the super heater on the performance of an existing steam power plant located in Derna, Libya. The performance of the power plant was estimated by a mathematical modelling which considers the off-design operating conditions of each component. A fully interactive computer program based on the mass, energy and exergy balance equations has been developed. The maximum exergy destruction has been found in the steam generation unit. A 50% reduction in the design value of overall conductance of the super heater has been achieved, which accordingly decreases the amount of the net electrical power that would be generated by at least 13 MW, as well as the overall plant exergy efficiency by at least 6.4%, and at the same time that would cause an increase of the total exergy destruction by at least 14 MW. The achieved results showed that the super heater design and operating conditions play an important role on the thermodynamics performance and the fuel utilization of the power plant. Moreover, these considerations are very useful in the process of the decision that should be taken at the occasions of deciding whether to replace or renovate the super heater of the power plant.

Keywords: Exergy, Super-heater, Fouling; Steam power plant; Off-design., Fouling;, Super-heater, Steam power plant

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Authors: Mogens Saberi

Abstract:

This paper presents different design approaches for the design of turbine foundations. In the design process, several unknown factors must be considered such as the soil stiffness at the site. The main static and dynamic loads are presented and the results of a dynamic simulation are presented for a turbine foundation that is currently being built. A turbine foundation is an important part of a power plant since a non-optimal behavior of the foundation can damage the turbine itself and thereby stop the power production with large consequences.

Keywords: dynamic turbine design, harmonic response analysis, practical turbine design experience, concrete foundation

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Authors: Kashmir Johal

Abstract:

Within a wider context of improving whole-life effectiveness of gas and oil fields, we have been researching how to generate power local to the wellhead. (Provision of external power to a subsea wellhead can be prohibitively expensive and results in uneconomic fields. This has been an oil/gas industry challenge for many years.) We have been developing a possible approach to “local” power generation and have been conducting technical, environmental, (and economic) research to develop a viable approach. We sought to create a workable design for a new type of power generation system that makes use of differential pressure that can exist between the sea surface and a gas (or oil reservoir). The challenge has not just been to design a system capable of generating power from potential energy but also to design it in such a way that it anticipates and deals with the wide range of technological, environmental, and chemical constraints faced in such environments. We believe this project shows the enormous opportunity in deriving clean, economic, and zero emissions renewable energy from offshore sources. Since this technology is not currently available, a patent has been filed to protect the advancement of this technology.

Keywords: renewable, energy, power, offshore

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Authors: Shao-Ku Kao

Abstract:

This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: wireless power transfer, active diode, delay compensation, time to voltage converter, PCE

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Authors: T. Angeline Priyanka, R. Ganesan

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Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Olusegun Solomon

Abstract:

This paper describes the concept for the design and maximum power point tracking control for an interior permanent magnet synchronous generator wind turbine system. Two design concepts are compared to outline the effect of magnet design on the performance of the interior permanent magnet synchronous generator. An approximate model that includes the effect of core losses has been developed for the machine to simulate the dynamic performance of the wind energy system. An algorithm for Maximum Power Point Tracking control is included to describe the process for maximum power extraction.

Keywords: permanent magnet synchronous generator, wind power system, wind turbine

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Authors: Nissar Mohammad Karim, Norhayati Soin

Abstract:

To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, Sol-Gel, precursor aging, aging

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Authors: J. S. Kim

Abstract:

This paper presents a 0.13-µm Complementary Metal-Oxide Semiconductor (CMOS) vector modulator for beamforming system. The vector modulator features a 360° phase and gain range of -10 dB to 10 dB with a root mean square phase and amplitude error of only 2.2° and 0.45 dB, respectively. These features make it a suitable for wireless backhaul system in the 5 GHz industrial, scientific, and medical (ISM) bands. It draws a current of 20.4 mA from a 1.2 V supply. The total chip size is 1.87x1.34 mm².

Keywords: CMOS, vector modulator, beamforming, 802.11ac

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Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

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At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

Abstract:

This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Nissar Mohammad Karim, Norhayati Soin

Abstract:

To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, sol-gel, precursor ageing, metallurgical and materials engineering

Procedia PDF Downloads 349

Authors: Madhav Pant, Khem N. Poudel

Abstract:

Wireless power transfer is continuously becoming more powerful and compact in medical implantable devices and the wide range of applications. A rectenna is designed for wireless power transfer technique that can be applied to medical implant devices. The experiment is performed using ANSYS HFSS, a full wave electromagnetic simulation. The dipole antenna combinations operating at 2.4 GHz are used for wireless power transfer and the maximum DC voltage reception by the implant considering International Commission on Non-Ionizing Radiation Protection (ICNIRP) regulation. The power receiving dipole antenna is placed inside the cylindrical geometry having the similar properties of the human body at the frequency of 2.4 GHz. Our design can provide the power at the depth of 5 mm skin and 5mm of bone for the implant. The voltage doubler/quadrupler rectifier in ANSYS Simplorer is used to calculate the exact DC current utilized by implant inside the human body. The qualitative design and analysis of this wireless power transfer method could also be used for other biomedical implants systems such as cardiac pacemaker, insulin pump, and retinal implants.

Keywords: dipole antenna, medical implants, wireless power transfer, rectifier

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Authors: Nagaraju Pendam, C. P. Vardhani

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A simple technology–compatible design of silicon-on-insulator based 1×2 optical power splitter is proposed. For developing large area Opto-electronic Silicon-on-Insulator (SOI) devices, the power splitter is a key passive device. The SOI rib- waveguide dimensions (height, width, and etching depth, refractive indices, length of waveguide) leading simultaneously to single mode propagation. In this paper a low loss optical power splitter is designed by using R Soft cad tool and simulated by Beam propagation method, here s-bend waveguides proposed. We concentrate changing the refractive index difference, branching angle, width of the waveguide, free space wavelength of the waveguide and observing transmitted power, effective refractive index in the designed waveguide, and choosing the best simulated results to be fabricated on silicon-on insulator platform. In this design 1550 nm free spacing are used.

Keywords: beam propagation method, insertion loss, optical power splitter, rib waveguide, transmitted power

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Authors: Alaa Abdullah Altaee

Abstract:

This paper presents an adaptive decision feedback equalizer (ADFE) for multi-Gbps serial links utilizing a fix-step error signal extracted from cross-points of received data symbols. The extracted signal is generated based on violation of received data symbols with minimum detection requirements at the clock and data recovery (CDR) stage. The iterations of the adaptation process search for the optimum feedback tap coefficients to maximize the data eye-opening and minimize the adaptation convergence time. The effectiveness of the proposed architecture is validated using the simulation results of a serial link designed in an IBM 130 nm 1.2V CMOS technology. The data link with variable channel lengths is analyzed using Spectre from Cadence Design Systems with BSIM4 device models.

Keywords: adaptive DFE, CMOS equalizer, error detection, serial links, timing jitter, wire-line communication

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Authors: Yasaman Esfandiari

Abstract:

Mechanical engineering has always dealt with amplification of the input power in power trains. One of the ways to achieve this goal is to use gears to change the amplitude and direction of the torque and the speed. However, the gears should be optimally designed to best achieve these objectives. In this study, helical gear systems are optimized to achieve maximum power. Material selection, space restriction, available facilities for manufacturing, the probability of tooth breakage, and tooth wear are taken into account and governing equations are derived. Finally, a Matlab code was generated to solve the optimization problem and the results are verified.

Keywords: design, gears, Matlab, optimization

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Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: power integrity, power-aware signal integrity analysis, electromagnetic simulation, channel simulation

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Authors: Michael Naderer, Manuel Hartong, Raad Al-Kinani

Abstract:

The use of hollow conductors is known in electric generators of large MW scale. The application of motors of small scale between 50 and 200kW is new. The latest results in the practical application and set up of machines show that the power density can be raised significantly and the common problem of derating of the motors is prevented. Furthermore, new design dimensions can be realised as continuous current densities up to 75A/mm² are achievable. This paper shows the results of the application of hollow conductors for a motor design used for automotive traction machines comparing common coolings with hollow conductor cooling.

Keywords: degree of efficiency, electric motor design, hollow conductors, power density

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Authors: Júlio Cesar Lopes de Oliveira, Carlos Henrique Gonçalves Treviso

Abstract:

The shortage of the automotive market in relation to options for sources of high power car audio systems, led to development of this work. Thus, we developed a source with stabilized voltage with 4320 W effective power. Designed to the voltage of 14.4 V and a choice of two currents: 30 A load option in battery banks and 300 A at full load. This source can also be considered as a source of general use dedicated commercial with a simple control circuit in analog form based on discrete components. The assembly of power circuit uses a methodology for higher power than the initially stipulated.

Keywords: DC-DC power converters, converters, power conversion, pulse width modulation converters

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Authors: Wahab Ali Shah, Junjia He

Abstract:

Transferring electrical power without any wiring has been a dream since late 19^th century. There were some advances in this area as to know more about microwave systems. However, this subject has recently become very attractive due to their practiScal systems. There are low power applications such as charging the batteries of contactless tooth brushes or implanted devices, and higher power applications such as charging the batteries of electrical automobiles or buses. In the first group of applications operating frequencies are in microwave range while the frequency is lower in high power applications. In the latter, the concept is also called inductive power transfer. The aim of the paper is to have an overview of the inductive power transfer for electrical vehicles with a special concentration on coil design and power converter simulation for static charging. Coil design is very important for an efficient and safe power transfer. Coil design is one of the most critical tasks. Power converters are used in both side of the system. The converter on the primary side is used to generate a high frequency voltage to excite the primary coil. The purpose of the converter in the secondary is to rectify the voltage transferred from the primary to charge the battery. In this paper, an inductive power transfer system is studied. Inductive power transfer is a promising technology with several possible applications. Operation principles of these systems are explained, and components of the system are described. Finally, a single phase 2 kW system was simulated and results were presented. The work presented in this paper is just an introduction to the concept. A reformed compensation network based on traditional inductor-capacitor-inductor (LCL) topology is proposed to realize robust reaction to large coupling variation that is common in dynamic wireless charging application. In the future, this type compensation should be studied. Also, comparison of different compensation topologies should be done for the same power level.

Keywords: coil design, contactless charging, electrical automobiles, inductive power transfer, operating frequency

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: R. Sharma, J. K. Bhatnagar, Poonam, R. C. Sharma

Abstract:

Metal–air batteries have been designed and developed as an essential source of electric power to propel automobiles, make electronic equipment functional, and use them as the source of power in remote areas and space. High energy and power density, lightweight, easy recharge capabilities, and low cost are essential features of these batteries. Both primary and rechargeable magnesium air batteries are highly promising. Our focus will be on the basics of electrode reaction kinetics of Mg–air cell in this paper. Design and development of Mg or Mg alloys as anode materials, design and composition of air cathode, and promising electrolytes for Mg–air batteries have been reviewed. A brief note on the possible and proposed improvements in design and functionality is also incorporated. This article may serve as the primary and premier document in the critical research area of Mg-air battery systems.

Keywords: air cathode, battery design, magnesium air battery, magnesium anode, rechargeable magnesium air battery

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Authors: Gagnesh Kumar, Nitin Gupta

Abstract:

Ternary Content Addressable Memory cells are mainly popular in network routers for packet forwarding and packet classification, but they are also useful in a variety of other applications that require high-speed table look-up. The main TCAM-design challenge is to decrease the power consumption associated with the large amount of parallel active circuitry, without compromising with speed or memory density. Furthermore, when the channel length decreases, leakage power becomes more significant, and it can even dominate dynamic power at lower technologies. In this paper, we propose a TCAM-design technique, called Virtual Power Supply technique that reduces the leakage by a substantial amount.

Keywords: match line (ML), search line (SL), ternary content addressable memory (TCAM), Leakage power (LP)

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