Search results for: power hardware in the loop

Authors: Debabrata Das

Abstract:

This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

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Authors: Alaa A. Zaky

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In this work, we present for the first time the grid-integration of 3rd generation perovskite solar cells (PSCs) based on nanotechnology in fabrication. The effect of this penetration is analyzed in normal, fault, and islanding cases of operation under different irradiation conditions using the power hardware in the loop (PHIL) methodology. The PHL method allows the PSCs to connect to the electric grid, which is simulated in the real-time digital simulator (RTDS), for laboratory validation of the PSCs behavior under conditions very close to real.

Keywords: perovskite solar cells, power hardware in the loop, real-time digital simulator, smart grid

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Authors: Ha Thi Nguyen, Guangya Yang, Arne Hejde Nielsen, Peter Højgaard Jensen

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Automatic voltage regulator (AVR) plays an important role in volt/var control of synchronous condenser (SC) in power systems. Test AVR performance in steady-state and dynamic conditions in real grid is expensive, low efficiency, and hard to achieve. To address this issue, we implement hardware-in-the-loop (HiL) test for the AVR of SC to test the steady-state and dynamic performances of AVR in different operating conditions. Startup procedure of the system and voltage set point changes are studied to evaluate the AVR hardware response. Overexcitation, underexcitation, and AVR set point loss are tested to compare the performance of SC with the AVR hardware and that of simulation. The comparative results demonstrate how AVR will work in a real system. The results show HiL test is an effective approach for testing devices before deployment and is able to parameterize the controller with lower cost, higher efficiency, and more flexibility.

Keywords: automatic voltage regulator, hardware-in-the-loop, synchronous condenser, real time digital simulator

Procedia PDF Downloads 245

Authors: Kyung-Jung Lee, Hyun-Sik Ahn

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This paper suggests a design methodology for the hardware and software of the Electronic Control Unit (ECU) of safety-critical vehicle applications such as braking and steering. The architecture of the hardware is a high integrity system such that it incorporates a high performance 32-bit CPU and a separate Peripheral Control-Processor (PCP) together with an external watchdog CPU. Communication between the main CPU and the PCP is executed via a common area of RAM and events on either processor which are invoked by interrupts. Safety-related software is also implemented to provide a reliable, self-testing computing environment for safety critical and high integrity applications. The validity of the design approach is shown by using the Hardware-in-the-Loop Simulation (HILS) for Electric Power Steering (EPS) systems which consists of the EPS mechanism, the designed ECU, and monitoring tools.

Keywords: electronic control unit, electric power steering, functional safety, hardware-in-the-loop simulation

Procedia PDF Downloads 288

Authors: Gondu Vykunta Rao, Madhuri Bayya, Aruna Bharathi M., Paramesw Chidamparam, B. Murali

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The increase in software content in today’s electric vehicles is increasing attention to having vast, unique topographies from low emission to high efficiency, whereas the chemical batteries have huge short comes, such as limited cycle life, power density, and cost. As for understanding and visualization, the companies are turning toward the virtual vehicle to test their design in software which is known as a simulation in the loop (SIL). In this project, in addition to the electric vehicle (EV) technology, we are adding a dynamo with the vehicle for regenerative braking. Traditionally the principle of dynamos is used in lighting the purpose of the bicycle. Here by using the same mechanism, we are running the vehicle as well as charging the vehicle from system-level simulation to the model in the loop and then to the Hardware in Loop (HIL) by using model-based development.

Keywords: electric vehicle, simulation in the loop (SIL), model in loop (MIL), hardware in loop (HIL), dynamos, model-based development (MBD), permanent magnet synchronous motor (PMSM), current control (CC), field-oriented control (FOC), regenerative braking

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Authors: Reza Karami, Ali Akbar Ebrahimi

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This paper discusses concurrent engineering of robot manipulators, based on the Holistic Concurrent Design (HCD) methodology and by using a hardware-in-the-loop simulation platform. The methodology allows for considering numerous design variables with different natures concurrently. It redefines the ultimate goal of design based on the notion of satisfaction, resulting in the simplification of the multi-objective constrained optimization process. It also formalizes the effect of designer’s subjective attitude in the process. To enhance modeling efficiency for both computation and accuracy, a hardware-in-the-loop simulation platform is used, which involves physical joint modules and the control unit in addition to the software modules. This platform is implemented in the HCD design architecture to reliably evaluate the design attributes and performance super criterion during the design process. The resulting overall architecture is applied to redesigning kinematic, dynamic and control parameters of an industrial robot manipulator.

Keywords: concurrent engineering, hardware-in-the-loop simulation, robot manipulator, multidisciplinary systems, mechatronics

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Authors: Heung Sun Yoon, Jong Tae Kim

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In this paper, we present an activity diagram model for double-loop control self-adaptive braking system. Since activity diagram helps to improve visibility of self-adaption, we can easily find where improvement is needed on double-loop control. Double-loop control is adopted since the design conditions and actual conditions can be different. The system is reconfigured in runtime by using double-loop control. We simulated to verify and validate our model by using MATLAB. We compared single-loop control model with double-loop control model. Simulation results show that double-loop control provides more consistent brake power control than single-loop control.

Keywords: activity diagram, automotive, braking system, double-loop, self-adaptive, UML, vehicle

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Balasundaram Prasaant, Ploix Stephane, Delinchant Benoit, Muresan Cristian

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Hardware in Loop (HIL) testing is done to test and validate a particular product especially in building technology. When it comes to building technology, it is more important to test the products for their efficiency. The test rig in the HIL simulator may contribute to some uncertainties on measured efficiency. The uncertainties include physical uncertainties and scenario-based uncertainties. In this paper, a simple uncertainty analysis framework for an HIL setup is shown considering only the physical uncertainties. The entire modeling of the HIL setup is done in Dymola. The uncertain sources are considered based on available knowledge of the components and also on expert knowledge. For the propagation of uncertainty, Monte Carlo Simulation is used since it is the most reliable and easy to use. In this article it is shown how an HIL setup can be modeled and how uncertainty propagation can be performed on it. Such an approach is not common in building energy analysis.

Keywords: energy in buildings, hardware in loop testing, modelica modelling, Monte Carlo simulation, uncertainty propagation

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Authors: Longfei Wang, Selçuk Köse

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Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Jorge Rodriguez-Guerra, Carlos Calleja, Aron Pujana, Ana Maria Macarulla

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Hydraulic-press commissioning consumes a great amount of man-hours, due to the fact that it takes place several miles away from where it has been designed. This factor became exacerbated due to control designers’ lack of knowledge about which will be the final controller gains before they start working with it. Virtual commissioning has been postulated as an optimal solution to deal with this lack of knowledge. Here, a case study is presented in which a controller is set up against a real-time model based on a hydraulic-press. The press model is designed following manufacturer specifications and it is embedded in a real-time simulator. This methodology ensures that the model achieves similar responses as the real machine that would be placed on the industry. A deterministic communication protocol is in charge of the bidirectional information transmission between the real-time model and the controller. This platform allows the engineer to test and verify the final control responses with exactly the same hardware that is going to be installed in the hydraulic-press, in other words, realize a virtual commissioning of the electro-hydraulic actuator. The Hardware in the Loop (HiL) platform validates in laboratory conditions and harmless for the machine the control algorithms designed, which allows embedding them afterwards in the industrial environment without further modifications.

Keywords: deterministic communication protocol, electro-hydraulic actuator, hardware in the loop, real-time, virtual commissioning

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Authors: Hanan Mikhael Dawood, Afaneen Anwer Abood Al-Khazraji

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The paper presents an investigation of field oriented control strategy of Permanent Magnet Synchronous Motor (PMSM) based on hardware in the loop simulation (HIL) over a wide speed range. A sensorless rotor position estimation using sliding mode observer for permanent magnet synchronous motor is illustrated considering the effects of magnetic saturation between the d and q axes. The cross saturation between d and q axes has been calculated by finite-element analysis. Therefore, the inductance measurement regards the saturation and cross saturation which are used to obtain the suitable id-characteristics in base and flux weakening regions. Real time matrix multiplication in Field Programmable Gate Array (FPGA) using floating point number system is used utilizing Quartus-II environment to develop FPGA designs and then download these designs files into development kit. dSPACE DS1103 is utilized for Pulse Width Modulation (PWM) switching and the controller. The hardware in the loop results conducted to that from the Matlab simulation. Various dynamic conditions have been investigated.

Keywords: magnetic saturation, rotor position estimation, sliding mode observer, hardware in the loop (HIL)

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Authors: Shail N. Shah, K. K. Baraya, A. Madhusudan Achari

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Loop Heat Pipe is a passive two-phase heat transfer device which can be used without any external power source to transfer heat from source to sink. The main aim of this paper is to have modelling of water-based LHP at varying heat loads. Through figures, how the fluid flow occurs within the loop has been explained. Energy Balance has been done in each section. IC (Iterative Convergence) scheme to find out the SSOT (Steady State Operating Temperature) has been developed. It is developed using Dev C++. To best of the author’s knowledge, hardly any detail is available in the open literature about how temperature distribution along the loop is to be evaluated. Results for water-based loop heat pipe is obtained and compared with open literature and error is found within 4%. Parametric study has been done to see the effect of different parameters on pressure drop and SSOT at varying heat loads.

Keywords: loop heat pipe, modelling of loop heat pipe, parametric study of loop heat pipe, functioning of loop heat pipe

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Authors: Kashif Habib, Zeeshan Ayyub

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ZnO voltage dependent resistor was widely used as components of the electrical system for over-voltage protection. It has a wide application prospect in superconducting energy-removal, generator de-excitation, overvoltage protection of electrical & electronics equipment. At present, the research for the application of ZnO voltage dependent resistor stop, it uses just in the field of its nonlinear voltage current characteristic and overvoltage protection areas. There is no further study over the over-voltage breakdown characteristics, such as the combustion phenomena and the measure of the voltage/current when it breakdown, and the affect to its surrounding equipment. It is also a blind spot in its application. So, when we do the feature test of ZnO voltage dependent resistor, we need to design a reasonable test power supply, making the terminal voltage keep for sine wave, simulating the real use of PF voltage in power supply conditions. We put forward the solutions of using inverter to generate a controllable power. The paper mainly focuses on the breakdown characteristic test power supply of nonlinear ZnO voltage dependent resistor. According to the current mature switching power supply technology, we proposed power control system using the inverter as the core. The power mainly realize the sin-voltage output on the condition of three-phase PF-AC input, and 3 control modes (RMS, Peak, Average) of the current output. We choose TMS320F2812M as the control part of the hardware platform. It is used to convert the power from three-phase to a controlled single-phase sin-voltage through a rectifier, filter, and inverter. Design controller produce SPWM, to get the controlled voltage source via appropriate multi-loop control strategy, while execute data acquisition and display, system protection, start logic control, etc. The TMS320F2812M is able to complete the multi-loop control quickly and can be a good completion of the inverter output control.

Keywords: ZnO, multi-loop control, SPWM, non-linear load

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Authors: Abdelhalim Kessal

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This paper treats a design of combined control of a single phase power factor correction (PFC). The strategy of the proposed control is based on two parts, the first, for the outer loop (DC output regulated voltage), and the second govern the input current of the converter in order to achieve a sinusoidal form in phase with the grid voltage. Two kinds of regulators are used, Fuzzy controller for the outer loop and predictive controller for the inner loop. The controllers are verified and discussed through simulation under MATLAB/Simulink platform. Also an experimental confirmation is applied. Results present a high dynamic performance under various parameters changes.

Keywords: boost converter, harmonic distortion, Fuzzy, predictive, unity power factor

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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Authors: Ali Kadivar, Kaveh Niayesh

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The integration of green energy resources is a major focus, and the role of Medium Voltage Direct Current (MVDC) systems is exponentially expanding. However, the protection of MVDC systems against DC faults is a challenge that can have consequences on reliable and safe grid operation. This challenge reveals the need for MVDC circuit breakers (MVDC CB), which are in infancies of their improvement. Therefore will be a lack of MVDC CBs standards, including thresholds for acceptable power losses and operation speed. To establish a baseline for comparison purposes, a benchmark system for testing future MVDC CBs is vital. The literatures just give the timing sequence of each switch and the emphasis is on the topology, without in-depth study on the control algorithm of DCCB, as the circuit breaker control system is not yet systematic. A digital testing benchmark is designed for the Proof-of-concept of simulation studies using software models. It can validate studies based on real-time digital simulators and Transient Network Analyzer (TNA) models. The proposed experimental setup utilizes data accusation from the accurate sensors installed on the tested MVDC CB and through general purpose input/outputs (GPIO) from the microcontroller and PC Prototype studies in the laboratory-based models utilizing Hardware-in-the-Loop (HIL) equipment connected to real-time digital simulators is achieved. The improved control algorithm of the circuit breaker can reduce the peak fault current and avoid arc resignation, helping the coordination of DCCB in relay protection. Moreover, several research gaps are identified regarding case studies and evaluation approaches.

Keywords: DC circuit breaker, hardware-in-the-loop, real time digital simulation, testing benchmark

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Authors: Naheem Olakunle Adesina

Abstract:

The memristor is considered as one of the promising candidates for mamoelectronic engineering and applications. Owing to its high compatibility with CMOS, nanoscale size, and low power consumption, memristor has been employed in the design of commonly used circuits such as phase-locked loop (PLL). In this paper, we designed a memristor-based loop filter (LF) together with other components of PLL. Following this, we evaluated the noise-rejection feature of loop filter by comparing the noise levels of input and output signals of the filter. Our SPICE simulation results showed that memristor behaves like a linear resistor at high frequencies. The result also showed that loop filter blocks the high-frequency components from phase frequency detector so as to provide a stable control voltage to the voltage controlled oscillator (VCO). In addition, we examined the effects of temperature on the performance of the designed phase locked loop circuit. A critical temperature, where there is frequency drift of VCO as a result of variations in control voltage, is identified. In conclusion, the memristor is a suitable choice for nanoelectronic systems owing to a small area, low power consumption, dense nature, high switching speed, and endurance. The proposed memristor-based loop filter, together with other components of the phase locked loop, can be designed using memristive emulator and EDA tools in current CMOS technology and simulated.

Keywords: Fast Fourier Transform, hysteresis curve, loop filter, memristor, noise, phase locked loop, voltage controlled oscillator

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Authors: Chinmay Shah

Abstract:

The project is all about development of a close loop traffic light control system using PLC (Programmable Logic Controller). This project is divided into two parts which are hardware and software. The hardware part for this project is a model of four way junction of a traffic light. Three indicator lamps (Red, Yellow and Green) are installed at each lane for represents as traffic light signal. This traffic control model is a replica of actuated traffic control. Actuated traffic control system is a close loop traffic control system which controls the timing of the indicator lamps depending on the fluidity of traffic for a particular lane. To make it autonomous, in each lane three IR sensors are placed which helps to sense the percentage of traffic present on any particular lane. The IR Sensors and Indicator lamps are connected to LG PLC XGB series. The PLC controls every signal which is coming from the inputs (IR Sensors) to software and display to the outputs (Indicator lamps). Default timing for the indicator lamps is 30 seconds for each lane. But depending on the percentage of traffic present, if the traffic is nearly 30-35%, green lamp will be on for 10 seconds, for 65-70% traffic it will be 20 seconds, for full 100% traffic it will be on for full 30 seconds. The software part that operates with LG PLC is “XG 5000” Programmer. Using this software, the ladder logic diagram is programmed to control the traffic light base on the flow chart. At the end of this project, the traffic light system is actuated successfully by PLC.

Keywords: close loop, IR sensor, PLC, light control system

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Authors: S. Sadhu, M. Ramgopal, S. Bhattacharyya

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Natural circulation loops (NCLs) are buoyancy driven flow systems without any moving components. NCLs have vast applications in geothermal, solar and nuclear power industry where reliability and safety are of foremost concern. Due to certain favorable thermophysical properties, especially near supercritical regions, carbon dioxide can be considered as an ideal loop fluid in many applications. In the present work, a high temperature NCL that uses supercritical carbon dioxide as loop fluid is analysed. The effects of relevant design and operating variables on loop performance are studied. The system operating under steady state is modelled taking into account the axial conduction through loop fluid and loop wall, and heat transfer with surroundings. The heat source is considered to be a heater with controlled heat flux and heat sink is modelled as an end heat exchanger with water as the external cold fluid. The governing equations for mass, momentum and energy conservation are normalized and are solved numerically using finite volume method. Results are obtained for a loop pressure of 90 bar with the power input varying from 0.5 kW to 6.0 kW. The numerical results are validated against the experimental results reported in the literature in terms of the modified Grashof number (Gr_m) and Reynolds number (Re). Based on the results, buoyancy and friction dominated regions are identified for a given loop. Parametric analysis has been done to show the effect of loop diameter, loop height, ambient temperature and insulation. The results show that for the high temperature loop, heat loss to surroundings affects the loop performance significantly. Hence this conjugate heat transfer between the loop and surroundings has to be considered in the analysis of high temperature NCLs.

Keywords: conjugate heat transfer, heat loss, natural circulation loop, supercritical carbon dioxide

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Authors: Osama Abdallah Mohammed Enan, Amin Babiker A/Nabi Mustafa

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The aim of this study is to evaluate and analyze different parameters of WCDMA (wideband code division multiplication). Moreover, this study also incorporates brief yet throughout analysis of WCDMA’s components as well as its internal architecture. This study also examines different power controls. These power controls may include open loop power control, closed or inner group loop power control and outer loop power control. Different handover techniques or methods of WCDMA are also illustrated in this study. These handovers may include hard handover, inter system handover and soft and softer handover. Different duplexing techniques are also described in the paper. This study has also presented an idea about different parameters of WCDMA that leads the system towards QoS issues. This may help the operator in designing and developing adequate network configuration. In addition to this, the study has also investigated various parameters including Bit Energy per Noise Spectral Density (Eb/No), Noise rise, and Bit Error Rate (BER). After simulating these parameters, using MATLAB environment, it was investigated that, for a given Eb/No value the system capacity increase by increasing the reuse factor. Besides that, it was also analyzed that, noise rise is decreasing for lower data rates and for lower interference levels. Finally, it was examined that, BER increase by using one type of modulation technique than using other type of modulation technique.

Keywords: duplexing, handover, loop power control, WCDMA

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Authors: C. T. Cheung, R. K. P. Ng, T. Y. Lo, Zhou Jinyun

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This paper aims at manipulating loop alignment in knitting a three-dimensional (3D) shape by its geometry. Two loop alignment methods are introduced to handle a surface with positive Gaussian curvature. As weft knitting is a two-dimensional (2D) knitting mechanism that the knitting cam carrying the feeders moves in two directions only, left and right, the knitted fabric generated grows in width and length but not in depth. Therefore, a 3D shape is required to be flattened to a 2D plane with surface area preserved for knitting. On this flattened plane, dimensional measurements are taken for loop alignment. The way these measurements being taken derived two different loop alignment methods. In this paper, only plain knitted structure was considered. Each knitted loop was taken as a basic unit for loop alignment in order to achieve the required geometric dimensions, without the inclusion of other stitches which give textural dimensions to the fabric. Two loop alignment methods were experimented and compared. Only one of these two can successfully preserve the dimensions of the shape.

Keywords: 3D knitting, 3D shape, loop alignment, positive Gaussian curvature

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Authors: Hyun Chul Koag, Hyun-Sik Ahn

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In this paper, we propose a design approach for the safety mechanism of an actuator used in a commercial vehicle’s EPS system. As the number of electric/electronic system in a vehicle increases, the importance of the functional safety has been receiving much attention. EPS(Electric Power Steering) systems for commercial vehicles require large power than passenger vehicles, and hence, dual motor can be applied to get more torque. We show how to formulate the development process for the design of hardware and software of an EPS system using dual motors. A lot of safety mechanisms for the processor, sensors, and memory have been suggested, however, those for actuators have not been fully researched. It is shown by metric analyses that the target ASIL(Automotive Safety Integrated Level) is satisfied in the point of view of hardware of EPS controller.

Keywords: safety mechanism, functional safety, commercial vehicles, electric power steering

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Authors: Ziyuan Wu, Yulong Jia, Xiang Zhang, Wanting Zhou, Lei Li

Abstract:

The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method.

Keywords: IoT, security, SoC, bus architecture, lightweight hardware firewall, FPGA

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Authors: Peter A. L’vov, Roman S. Konovalov, Alexey A. L’vov

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The paper presents the advanced digital modification of the conventional current loop circuit for pressure piezoelectric transducers. The optimal DSP algorithms of current loop responses by the maximum likelihood method are applied for diminishing of measurement errors. The loop circuit has some additional advantages such as the possibility to operate with any type of resistance or reactance sensors, and a considerable increase in accuracy and quality of measurements to be compared with AC bridges. The results obtained are dedicated to replace high-accuracy and expensive measuring bridges with current loop circuits.

Keywords: current loop, maximum likelihood method, optimal digital signal processing, precise pressure measurement

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Authors: R. S. Sheu, H. Usman, M. S. Lawal

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Takagi-Sugeno (T-S) fuzzy model based control of a load frequency deviation in a single machine with limit nonlinearity on power coefficient is presented in the paper. Two T-S fuzzy rules with only rotor angle variable as input in the premise part, and linear state space models in the consequent part involving characteristic matrices determined from limits set on the power coefficient constant are formulated, state feedback control gains for closed loop control was determined from the formulated Linear Matrix Inequality (LMI) with eigenvalue optimization scheme for asymptotic and exponential stability (speed of esponse). Numerical evaluation of the closed loop object was carried out in Matlab. Simulation results generated of both the open and closed loop system showed the effectiveness of the control scheme in maintaining load frequency stability.

Keywords: T-S fuzzy model, state feedback control, linear matrix inequality (LMI), frequency deviation control

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Authors: Pavuluri Gopikrishna, B. Neelima

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Power line carrier communication means audio power transmission via power line and reception of the amplified audio power at the receiver as in the form of speaker output signal using power line as the channel medium. The main objective of this suggested work is to transmit our message signal after frequency modulation by the help of FM modulator IC LM565 which gives output proportional to the input voltage of the input message signal. And this audio power is received from the power line by the help of isolation circuit and demodulated from IC LM565 which uses the concept of the PLL and produces FM demodulated signal to the listener. Message signal will be transmitted over the carrier signal that will be generated from the FM modulator IC LM565. Using this message signal will not damage because of no direct contact of message signal from the power line, but noise can disturb our information.

Keywords: amplification, fm demodulator ic 565, fm modulator ic 565, phase locked loop, power isolation

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Authors: Seda Yavuz, Anıl Çelebi, Aysun Taşyapı Çelebi, Oğuzhan Urhan

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Nowadays, demand for using real-time video transmission capable devices is ever-increasing. So, high resolution videos have made efficient video compression techniques an essential component for capturing and transmitting video data. Motion estimation has a critical role in encoding raw video. Hence, various motion estimation methods are introduced to efficiently compress the video. Low bit‑depth representation based motion estimation methods facilitate computation of matching criteria and thus, provide small hardware footprint. In this paper, a hardware implementation of a two-bit transformation based low-complexity motion estimation method using local binary pattern approach is proposed. Image frames are represented in two-bit depth instead of full-depth by making use of the local binary pattern as a binarization approach and the binarization part of the hardware architecture is explained in detail. Experimental results demonstrate the difference between the proposed hardware architecture and the architectures of well-known low-complexity motion estimation methods in terms of important aspects such as resource utilization, energy and power consumption.

Keywords: binarization, hardware architecture, local binary pattern, motion estimation, two-bit transform

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Authors: Ravi Ande, Mousumi Hazari

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One of the common geophysical techniques for mapping subsurface geo-electrical structures, extensive hydro-geological research, and engineering and environmental geophysics applications is the use of time domain electromagnetic (TDEM)/transient electromagnetic (TEM) soundings. A large transmitter loop for energising the ground and a small receiver loop or magnetometer for recording the transient voltage or magnetic field in the air or on the surface of the earth, with the receiver at the center of the loop or at any random point inside or outside the source loop, make up a large loop TEM system. In general, one can acquire data using one of the configurations with a large loop source, namely, with the receiver at the center point of the loop (central loop method), at an arbitrary in-loop point (in-loop method), coincident with the transmitter loop (coincidence-loop method), and at an arbitrary offset loop point (offset-loop method), respectively. Because of the mathematical simplicity associated with the expressions of EM fields, as compared to the in-loop and offset-loop systems, the central loop system (for ground surveys) and coincident loop system (for ground as well as airborne surveys) have been developed and used extensively for the exploration of mineral and geothermal resources, for mapping contaminated groundwater caused by hazardous waste and thickness of permafrost layer. Because a proper analytical expression for the TEM response over the layered earth model for the large loop TEM system does not exist, the forward problem used in this inversion scheme is first formulated in the frequency domain and then it is transformed in the time domain using Fourier cosine or sine transforms. Using the EMLCLLER algorithm, the forward computation is initially carried out in the frequency domain. As a result, the EMLCLLER modified the forward calculation scheme in NLSTCI to compute frequency domain answers before converting them to the time domain using Fourier Cosine and/or Sine transforms.

Keywords: time domain electromagnetic (TDEM), TEM system, geoelectrical sounding structure, Fourier cosine

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Authors: Mohd Sabri Minhat, Nurul Adilla Mohd Subha

Abstract:

The 1MWth PUSPATI TRIGA Reactor (RTP) in Malaysia Nuclear Agency has been operating more than 35 years. The existing core power control is using conventional controller known as Feedback Control Algorithm (FCA). It is technically challenging to keep the core power output always stable and operating within acceptable error bands for the safety demand of the RTP. Currently, the system could be considered unsatisfactory with power tracking performance, yet there is still significant room for improvement. Hence, a new design core power control is very important to improve the current performance in tracking and regulating reactor power by controlling the movement of control rods that suit the demand of highly sensitive of nuclear reactor power control. In this paper, the proposed Model Predictive Control (MPC) law was applied to control the core power. The model for core power control was based on mathematical models of the reactor core, MPC, and control rods selection algorithm. The mathematical models of the reactor core were based on point kinetics model, thermal hydraulic models, and reactivity models. The proposed MPC was presented in a transfer function model of the reactor core according to perturbations theory. The transfer function model-based predictive control (TFMPC) was developed to design the core power control with predictions based on a T-filter towards the real-time implementation of MPC on hardware. This paper introduces the sensitivity functions for TFMPC feedback loop to reduce the impact on the input actuation signal and demonstrates the behaviour of TFMPC in term of disturbance and noise rejections. The comparisons of both tracking and regulating performance between the conventional controller and TFMPC were made using MATLAB and analysed. In conclusion, the proposed TFMPC has satisfactory performance in tracking and regulating core power for controlling nuclear reactor with high reliability and safety.

Keywords: core power control, model predictive control, PUSPATI TRIGA reactor, TFMPC

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