Search results for: hardware in loop (HIL)

Authors: Debabrata Das

Abstract:

This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

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Authors: Reza Karami, Ali Akbar Ebrahimi

Abstract:

This paper discusses concurrent engineering of robot manipulators, based on the Holistic Concurrent Design (HCD) methodology and by using a hardware-in-the-loop simulation platform. The methodology allows for considering numerous design variables with different natures concurrently. It redefines the ultimate goal of design based on the notion of satisfaction, resulting in the simplification of the multi-objective constrained optimization process. It also formalizes the effect of designer’s subjective attitude in the process. To enhance modeling efficiency for both computation and accuracy, a hardware-in-the-loop simulation platform is used, which involves physical joint modules and the control unit in addition to the software modules. This platform is implemented in the HCD design architecture to reliably evaluate the design attributes and performance super criterion during the design process. The resulting overall architecture is applied to redesigning kinematic, dynamic and control parameters of an industrial robot manipulator.

Keywords: concurrent engineering, hardware-in-the-loop simulation, robot manipulator, multidisciplinary systems, mechatronics

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Authors: Ha Thi Nguyen, Guangya Yang, Arne Hejde Nielsen, Peter Højgaard Jensen

Abstract:

Automatic voltage regulator (AVR) plays an important role in volt/var control of synchronous condenser (SC) in power systems. Test AVR performance in steady-state and dynamic conditions in real grid is expensive, low efficiency, and hard to achieve. To address this issue, we implement hardware-in-the-loop (HiL) test for the AVR of SC to test the steady-state and dynamic performances of AVR in different operating conditions. Startup procedure of the system and voltage set point changes are studied to evaluate the AVR hardware response. Overexcitation, underexcitation, and AVR set point loss are tested to compare the performance of SC with the AVR hardware and that of simulation. The comparative results demonstrate how AVR will work in a real system. The results show HiL test is an effective approach for testing devices before deployment and is able to parameterize the controller with lower cost, higher efficiency, and more flexibility.

Keywords: automatic voltage regulator, hardware-in-the-loop, synchronous condenser, real time digital simulator

Procedia PDF Downloads 224

Authors: Gondu Vykunta Rao, Madhuri Bayya, Aruna Bharathi M., Paramesw Chidamparam, B. Murali

Abstract:

The increase in software content in today’s electric vehicles is increasing attention to having vast, unique topographies from low emission to high efficiency, whereas the chemical batteries have huge short comes, such as limited cycle life, power density, and cost. As for understanding and visualization, the companies are turning toward the virtual vehicle to test their design in software which is known as a simulation in the loop (SIL). In this project, in addition to the electric vehicle (EV) technology, we are adding a dynamo with the vehicle for regenerative braking. Traditionally the principle of dynamos is used in lighting the purpose of the bicycle. Here by using the same mechanism, we are running the vehicle as well as charging the vehicle from system-level simulation to the model in the loop and then to the Hardware in Loop (HIL) by using model-based development.

Keywords: electric vehicle, simulation in the loop (SIL), model in loop (MIL), hardware in loop (HIL), dynamos, model-based development (MBD), permanent magnet synchronous motor (PMSM), current control (CC), field-oriented control (FOC), regenerative braking

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Authors: Kyung-Jung Lee, Hyun-Sik Ahn

Abstract:

This paper suggests a design methodology for the hardware and software of the Electronic Control Unit (ECU) of safety-critical vehicle applications such as braking and steering. The architecture of the hardware is a high integrity system such that it incorporates a high performance 32-bit CPU and a separate Peripheral Control-Processor (PCP) together with an external watchdog CPU. Communication between the main CPU and the PCP is executed via a common area of RAM and events on either processor which are invoked by interrupts. Safety-related software is also implemented to provide a reliable, self-testing computing environment for safety critical and high integrity applications. The validity of the design approach is shown by using the Hardware-in-the-Loop Simulation (HILS) for Electric Power Steering (EPS) systems which consists of the EPS mechanism, the designed ECU, and monitoring tools.

Keywords: electronic control unit, electric power steering, functional safety, hardware-in-the-loop simulation

Procedia PDF Downloads 269

Authors: Balasundaram Prasaant, Ploix Stephane, Delinchant Benoit, Muresan Cristian

Abstract:

Hardware in Loop (HIL) testing is done to test and validate a particular product especially in building technology. When it comes to building technology, it is more important to test the products for their efficiency. The test rig in the HIL simulator may contribute to some uncertainties on measured efficiency. The uncertainties include physical uncertainties and scenario-based uncertainties. In this paper, a simple uncertainty analysis framework for an HIL setup is shown considering only the physical uncertainties. The entire modeling of the HIL setup is done in Dymola. The uncertain sources are considered based on available knowledge of the components and also on expert knowledge. For the propagation of uncertainty, Monte Carlo Simulation is used since it is the most reliable and easy to use. In this article it is shown how an HIL setup can be modeled and how uncertainty propagation can be performed on it. Such an approach is not common in building energy analysis.

Keywords: energy in buildings, hardware in loop testing, modelica modelling, Monte Carlo simulation, uncertainty propagation

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Authors: Jorge Rodriguez-Guerra, Carlos Calleja, Aron Pujana, Ana Maria Macarulla

Abstract:

Hydraulic-press commissioning consumes a great amount of man-hours, due to the fact that it takes place several miles away from where it has been designed. This factor became exacerbated due to control designers’ lack of knowledge about which will be the final controller gains before they start working with it. Virtual commissioning has been postulated as an optimal solution to deal with this lack of knowledge. Here, a case study is presented in which a controller is set up against a real-time model based on a hydraulic-press. The press model is designed following manufacturer specifications and it is embedded in a real-time simulator. This methodology ensures that the model achieves similar responses as the real machine that would be placed on the industry. A deterministic communication protocol is in charge of the bidirectional information transmission between the real-time model and the controller. This platform allows the engineer to test and verify the final control responses with exactly the same hardware that is going to be installed in the hydraulic-press, in other words, realize a virtual commissioning of the electro-hydraulic actuator. The Hardware in the Loop (HiL) platform validates in laboratory conditions and harmless for the machine the control algorithms designed, which allows embedding them afterwards in the industrial environment without further modifications.

Keywords: deterministic communication protocol, electro-hydraulic actuator, hardware in the loop, real-time, virtual commissioning

Procedia PDF Downloads 111

Authors: Hanan Mikhael Dawood, Afaneen Anwer Abood Al-Khazraji

Abstract:

The paper presents an investigation of field oriented control strategy of Permanent Magnet Synchronous Motor (PMSM) based on hardware in the loop simulation (HIL) over a wide speed range. A sensorless rotor position estimation using sliding mode observer for permanent magnet synchronous motor is illustrated considering the effects of magnetic saturation between the d and q axes. The cross saturation between d and q axes has been calculated by finite-element analysis. Therefore, the inductance measurement regards the saturation and cross saturation which are used to obtain the suitable id-characteristics in base and flux weakening regions. Real time matrix multiplication in Field Programmable Gate Array (FPGA) using floating point number system is used utilizing Quartus-II environment to develop FPGA designs and then download these designs files into development kit. dSPACE DS1103 is utilized for Pulse Width Modulation (PWM) switching and the controller. The hardware in the loop results conducted to that from the Matlab simulation. Various dynamic conditions have been investigated.

Keywords: magnetic saturation, rotor position estimation, sliding mode observer, hardware in the loop (HIL)

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Authors: Heung Sun Yoon, Jong Tae Kim

Abstract:

In this paper, we present an activity diagram model for double-loop control self-adaptive braking system. Since activity diagram helps to improve visibility of self-adaption, we can easily find where improvement is needed on double-loop control. Double-loop control is adopted since the design conditions and actual conditions can be different. The system is reconfigured in runtime by using double-loop control. We simulated to verify and validate our model by using MATLAB. We compared single-loop control model with double-loop control model. Simulation results show that double-loop control provides more consistent brake power control than single-loop control.

Keywords: activity diagram, automotive, braking system, double-loop, self-adaptive, UML, vehicle

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Authors: Chinmay Shah

Abstract:

The project is all about development of a close loop traffic light control system using PLC (Programmable Logic Controller). This project is divided into two parts which are hardware and software. The hardware part for this project is a model of four way junction of a traffic light. Three indicator lamps (Red, Yellow and Green) are installed at each lane for represents as traffic light signal. This traffic control model is a replica of actuated traffic control. Actuated traffic control system is a close loop traffic control system which controls the timing of the indicator lamps depending on the fluidity of traffic for a particular lane. To make it autonomous, in each lane three IR sensors are placed which helps to sense the percentage of traffic present on any particular lane. The IR Sensors and Indicator lamps are connected to LG PLC XGB series. The PLC controls every signal which is coming from the inputs (IR Sensors) to software and display to the outputs (Indicator lamps). Default timing for the indicator lamps is 30 seconds for each lane. But depending on the percentage of traffic present, if the traffic is nearly 30-35%, green lamp will be on for 10 seconds, for 65-70% traffic it will be 20 seconds, for full 100% traffic it will be on for full 30 seconds. The software part that operates with LG PLC is “XG 5000” Programmer. Using this software, the ladder logic diagram is programmed to control the traffic light base on the flow chart. At the end of this project, the traffic light system is actuated successfully by PLC.

Keywords: close loop, IR sensor, PLC, light control system

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Authors: Shail N. Shah, K. K. Baraya, A. Madhusudan Achari

Abstract:

Loop Heat Pipe is a passive two-phase heat transfer device which can be used without any external power source to transfer heat from source to sink. The main aim of this paper is to have modelling of water-based LHP at varying heat loads. Through figures, how the fluid flow occurs within the loop has been explained. Energy Balance has been done in each section. IC (Iterative Convergence) scheme to find out the SSOT (Steady State Operating Temperature) has been developed. It is developed using Dev C++. To best of the author’s knowledge, hardly any detail is available in the open literature about how temperature distribution along the loop is to be evaluated. Results for water-based loop heat pipe is obtained and compared with open literature and error is found within 4%. Parametric study has been done to see the effect of different parameters on pressure drop and SSOT at varying heat loads.

Keywords: loop heat pipe, modelling of loop heat pipe, parametric study of loop heat pipe, functioning of loop heat pipe

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Authors: C. T. Cheung, R. K. P. Ng, T. Y. Lo, Zhou Jinyun

Abstract:

This paper aims at manipulating loop alignment in knitting a three-dimensional (3D) shape by its geometry. Two loop alignment methods are introduced to handle a surface with positive Gaussian curvature. As weft knitting is a two-dimensional (2D) knitting mechanism that the knitting cam carrying the feeders moves in two directions only, left and right, the knitted fabric generated grows in width and length but not in depth. Therefore, a 3D shape is required to be flattened to a 2D plane with surface area preserved for knitting. On this flattened plane, dimensional measurements are taken for loop alignment. The way these measurements being taken derived two different loop alignment methods. In this paper, only plain knitted structure was considered. Each knitted loop was taken as a basic unit for loop alignment in order to achieve the required geometric dimensions, without the inclusion of other stitches which give textural dimensions to the fabric. Two loop alignment methods were experimented and compared. Only one of these two can successfully preserve the dimensions of the shape.

Keywords: 3D knitting, 3D shape, loop alignment, positive Gaussian curvature

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Authors: Ali Kadivar, Kaveh Niayesh

Abstract:

The integration of green energy resources is a major focus, and the role of Medium Voltage Direct Current (MVDC) systems is exponentially expanding. However, the protection of MVDC systems against DC faults is a challenge that can have consequences on reliable and safe grid operation. This challenge reveals the need for MVDC circuit breakers (MVDC CB), which are in infancies of their improvement. Therefore will be a lack of MVDC CBs standards, including thresholds for acceptable power losses and operation speed. To establish a baseline for comparison purposes, a benchmark system for testing future MVDC CBs is vital. The literatures just give the timing sequence of each switch and the emphasis is on the topology, without in-depth study on the control algorithm of DCCB, as the circuit breaker control system is not yet systematic. A digital testing benchmark is designed for the Proof-of-concept of simulation studies using software models. It can validate studies based on real-time digital simulators and Transient Network Analyzer (TNA) models. The proposed experimental setup utilizes data accusation from the accurate sensors installed on the tested MVDC CB and through general purpose input/outputs (GPIO) from the microcontroller and PC Prototype studies in the laboratory-based models utilizing Hardware-in-the-Loop (HIL) equipment connected to real-time digital simulators is achieved. The improved control algorithm of the circuit breaker can reduce the peak fault current and avoid arc resignation, helping the coordination of DCCB in relay protection. Moreover, several research gaps are identified regarding case studies and evaluation approaches.

Keywords: DC circuit breaker, hardware-in-the-loop, real time digital simulation, testing benchmark

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Authors: Peter A. L’vov, Roman S. Konovalov, Alexey A. L’vov

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The paper presents the advanced digital modification of the conventional current loop circuit for pressure piezoelectric transducers. The optimal DSP algorithms of current loop responses by the maximum likelihood method are applied for diminishing of measurement errors. The loop circuit has some additional advantages such as the possibility to operate with any type of resistance or reactance sensors, and a considerable increase in accuracy and quality of measurements to be compared with AC bridges. The results obtained are dedicated to replace high-accuracy and expensive measuring bridges with current loop circuits.

Keywords: current loop, maximum likelihood method, optimal digital signal processing, precise pressure measurement

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Authors: Ravi Ande, Mousumi Hazari

Abstract:

One of the common geophysical techniques for mapping subsurface geo-electrical structures, extensive hydro-geological research, and engineering and environmental geophysics applications is the use of time domain electromagnetic (TDEM)/transient electromagnetic (TEM) soundings. A large transmitter loop for energising the ground and a small receiver loop or magnetometer for recording the transient voltage or magnetic field in the air or on the surface of the earth, with the receiver at the center of the loop or at any random point inside or outside the source loop, make up a large loop TEM system. In general, one can acquire data using one of the configurations with a large loop source, namely, with the receiver at the center point of the loop (central loop method), at an arbitrary in-loop point (in-loop method), coincident with the transmitter loop (coincidence-loop method), and at an arbitrary offset loop point (offset-loop method), respectively. Because of the mathematical simplicity associated with the expressions of EM fields, as compared to the in-loop and offset-loop systems, the central loop system (for ground surveys) and coincident loop system (for ground as well as airborne surveys) have been developed and used extensively for the exploration of mineral and geothermal resources, for mapping contaminated groundwater caused by hazardous waste and thickness of permafrost layer. Because a proper analytical expression for the TEM response over the layered earth model for the large loop TEM system does not exist, the forward problem used in this inversion scheme is first formulated in the frequency domain and then it is transformed in the time domain using Fourier cosine or sine transforms. Using the EMLCLLER algorithm, the forward computation is initially carried out in the frequency domain. As a result, the EMLCLLER modified the forward calculation scheme in NLSTCI to compute frequency domain answers before converting them to the time domain using Fourier Cosine and/or Sine transforms.

Keywords: time domain electromagnetic (TDEM), TEM system, geoelectrical sounding structure, Fourier cosine

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Authors: N. V. Kuznetsov, O. A. Kuznetsova, G. A. Leonov, M. V. Yuldashev, R. V. Yuldashev

Abstract:

Nonlinear analysis of the phase locked loop (PLL)-based circuits is a challenging task. Thus, the simulation is widely used for their study. In this work, we consider a mathematical model of the optical Costas loop and demonstrate the limitations of simulation approach related to the existence of so-called hidden oscillations in the phase space of the model.

Keywords: optical Costas loop, mathematical model, simulation, hidden oscillation

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Authors: Ajeevan Gautam, Gulam Anwer Khan, Pratibha Pokhrel

Abstract:

Introduction: Dermatoglyphics is the science which deals with the study of dermal ridge configuration on the digits, palms and soles. It is grooved by ridges and forms variety of configurations. The aim of the study was to identify dermal ridge patterns on fingertip of hypertensive patients and in normal population and to compare patterns among them. Methods: The subjects of the study were 130 hypertensives and 130 non-hypertensives cases of Kathmandu Valley aged between 40 to 80 years. Case history was recorded after consent finger prints were taken. Different parameters as whorl, loop, arch and composite patterns were studied and analysed. Result: It revealed, increased whorl pattern in hypertensive. It showed 65.69% whorl, 29.23% loop and 5.07% arch patterns in right hand of hypertensive people. In control, it was found to be 34.46% whorl, 58.15% loop and 5.38% arch patterns respectively. Similarly in left hand 63.69% whorl, 32% loop and 4.30% arch in hypertensive group. In control group it was 60.15% as loop, 35.69% as whorl and 15% as arch. Discussion: Based on findings of the result, it was concluded that the whorl, loop and arch patterns observed as 65.69%, 29.23% and 5.07% respectively in hypertensive cases in right hand. Similarly in left hand, it was found to be 4.30% as arch, 32% as loop and 63.69% as whorl patterns, but in normotensive subjects these patterns were recorded as 36.43%, 58.15%, 5.38% in right hand and 35.69%, 60.15%, 4.15% in left hand as whorl, loop and arch respectively.

Keywords: arch, dermatoglyphics, hypertension, loop, whorl

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Hanan Mikhael Dawood, Haider Salim, Jafar Al-Wash

Abstract:

This paper presents Proportional-Integral (PI) controller to improve the system performance which gives better torque and flux response. In addition, it reduces the undesirable torque ripple. The conventional DTC controller approach for induction machines, based on an improved torque and stator flux estimator, is implemented using Xilinx System Generator (XSG) for MATLAB/Simulink environment through Xilinx blocksets. The design was achieved in VHDL which is based on a MATLAB/Simulink simulation model. The hardware in the loop results are obtained considering the implementation of the proposed model on the Xilinx NEXYS2 Spartan 3E1200 FG320 Kit.

Keywords: induction motor, Direct Torque Control (DTC), Xilinx FPGA, motor drive

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: Kiran Kumar K., Ramesh Babu Bejjam, Atul Najan

Abstract:

A thermosyphon system is a heat transfer loop which operates on the basis of gravity and buoyancy forces. It guarantees a good reliability and low maintenance cost as it does not involve any mechanical pump. Therefore it can be used in many industrial applications such as refrigeration and air conditioning, electronic cooling, nuclear reactors, geothermal heat extraction, etc. But flow instabilities and loop configuration are the major problems in this system. Several previous researchers studied that stabilities can be suppressed by using nanofluids as loop fluid. In the present study a rectangular thermosyphon loop with end heat exchangers are considered for the study. This configuration is more appropriate for many practical applications such as solar water heater, geothermal heat extraction, etc. In the present work, steady-state analysis is carried out on thermosyphon loop with parallel flow coaxial heat exchangers at heat source and heat sink. In this loop nano fluid is considered as the loop fluid and water is considered as the external fluid in both hot and cold heat exchangers. For this analysis one-dimensional homogeneous model is developed. In this model, conservation equations like conservation of mass, momentum, energy are discretized using finite difference method. A computer code is written in MATLAB to simulate the flow in thermosyphon loop. A comparison in terms of heat transfer is made between water and nano fluid as working fluids in the loop.

Keywords: heat exchanger, heat transfer, nanofluid, thermosyphon loop

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Authors: S. Sadhu, M. Ramgopal, S. Bhattacharyya

Abstract:

Natural circulation loops (NCLs) are buoyancy driven flow systems without any moving components. NCLs have vast applications in geothermal, solar and nuclear power industry where reliability and safety are of foremost concern. Due to certain favorable thermophysical properties, especially near supercritical regions, carbon dioxide can be considered as an ideal loop fluid in many applications. In the present work, a high temperature NCL that uses supercritical carbon dioxide as loop fluid is analysed. The effects of relevant design and operating variables on loop performance are studied. The system operating under steady state is modelled taking into account the axial conduction through loop fluid and loop wall, and heat transfer with surroundings. The heat source is considered to be a heater with controlled heat flux and heat sink is modelled as an end heat exchanger with water as the external cold fluid. The governing equations for mass, momentum and energy conservation are normalized and are solved numerically using finite volume method. Results are obtained for a loop pressure of 90 bar with the power input varying from 0.5 kW to 6.0 kW. The numerical results are validated against the experimental results reported in the literature in terms of the modified Grashof number (Gr_m) and Reynolds number (Re). Based on the results, buoyancy and friction dominated regions are identified for a given loop. Parametric analysis has been done to show the effect of loop diameter, loop height, ambient temperature and insulation. The results show that for the high temperature loop, heat loss to surroundings affects the loop performance significantly. Hence this conjugate heat transfer between the loop and surroundings has to be considered in the analysis of high temperature NCLs.

Keywords: conjugate heat transfer, heat loss, natural circulation loop, supercritical carbon dioxide

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Authors: Jun Young Moon, Hyeonggeon Lee, Jong Tae Kim

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In this paper, we present Cortex-M3 based virtual platform which can virtualize wearable hardware platform and evaluate hardware performance. Cortex-M3 is very popular microcontroller in wearable devices, hardware sensors and display devices. This platform can be used to implement software layer for specific hardware architecture. By using the proposed platform the software development process can be parallelized with hardware development process. We present internal mechanism to implement the proposed virtual platform and describe how to use the proposed platform to develop software by using case study which is low cost wearable device that uses Cortex-M3.

Keywords: electronic system level design, software development, virtual platform, wearable device

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Authors: Hideyuki Shintani, Ichiro Koshijima

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In Cyber Physical System (CPS), if there are a large number of persons in the process, a role of person in CPS might be different comparing with the one-man system. It is also necessary to consider how Human-in-The-Loop Cyber Physical Systems (HiTLCPS) ensure safety of each person in the loop process. In this paper, the authors discuss a system safety framework with an illustrative example with STAMP model to clarify what point for safety should be considered and what role of person in the should have.

Keywords: cyber-physical-system, human-in-the-loop, safety, STAMP model

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Authors: Naheem Olakunle Adesina

Abstract:

The memristor is considered as one of the promising candidates for mamoelectronic engineering and applications. Owing to its high compatibility with CMOS, nanoscale size, and low power consumption, memristor has been employed in the design of commonly used circuits such as phase-locked loop (PLL). In this paper, we designed a memristor-based loop filter (LF) together with other components of PLL. Following this, we evaluated the noise-rejection feature of loop filter by comparing the noise levels of input and output signals of the filter. Our SPICE simulation results showed that memristor behaves like a linear resistor at high frequencies. The result also showed that loop filter blocks the high-frequency components from phase frequency detector so as to provide a stable control voltage to the voltage controlled oscillator (VCO). In addition, we examined the effects of temperature on the performance of the designed phase locked loop circuit. A critical temperature, where there is frequency drift of VCO as a result of variations in control voltage, is identified. In conclusion, the memristor is a suitable choice for nanoelectronic systems owing to a small area, low power consumption, dense nature, high switching speed, and endurance. The proposed memristor-based loop filter, together with other components of the phase locked loop, can be designed using memristive emulator and EDA tools in current CMOS technology and simulated.

Keywords: Fast Fourier Transform, hysteresis curve, loop filter, memristor, noise, phase locked loop, voltage controlled oscillator

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Authors: Muhammad Swilam

Abstract:

Solutions for the wrong division problem of the Extended Multi-Modulus Divider (EMMD) that occurs during modulus extension (i.e. switching the modulus value between two different ranges of division ratios), in open loop fractional dividers and fractional multiplying delay locked loop, is proposed. A detailed study for the MMD with Sigma-Delta is also presented. Moreover, extensive simulations for the divider are presented to ensure and verify its functionality and compared with the conventional dividers.

Keywords: extended multi-modulus divider (EMMD), fractional multiplying delay locked loop, open loop fractional divider, sigma delta modulator

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Authors: Yang Luo, Beibei Wang

Abstract:

In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Arnaud Nougues

Abstract:

This paper describes a two-stage methodology derived from internal model control (IMC) for tuning a proportional-integral-derivative (PID) controller for levels or other integrating processes in an industrial environment. Focus is the ease of use and implementation speed which are critical for an industrial application. Tuning can be done with minimum effort and without the need for time-consuming open-loop step tests on the plant. The first stage of the method applies to levels only: the vessel residence time is calculated from equipment dimensions and used to derive a set of preliminary proportional-integral (PI) settings with IMC. The second stage, re-tuning in closed-loop, applies to levels as well as other integrating processes: a tuning correction mechanism has been developed based on a series of closed-loop simulations with model errors. The tuning correction is done from a simple closed-loop step test and the application of a generic correlation between observed overshoot and integral time correction. A spin-off of the method is that an estimate of the vessel residence time (levels) or open-loop process gain (other integrating process) is obtained from the closed-loop data.

Keywords: closed-loop model identification, IMC-PID tuning method, integrating process control, on-line PID tuning adaptation

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Authors: Fariborz Ahmadi, Reza Tati

Abstract:

Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only do not this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.

Keywords: hardware, genetic algorithm, computer science, engineering

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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