Search results for: gate wrap around transistor

Authors: Nur Allisha Othman, Rosnah Shamsudin, Zaulia Othman, Siti Hajar Othman

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Mitigating short storage life of fruit like banana uses minimally process or known as fresh cut can contribute to the growing demand especially in South East Asian countries. The effect of different types of packaging material on fresh-cut Nipah (Musa acuminata balbisiana) were studied. Fresh cut banana cultivar (cv) Nipah are packed in polypropylene plastic (PP), low density polypropylene plastic (LDPE), polymer plastic film (shrink wrap) and polypropylene container as control for 12 days at low temperature (4ᵒC). Quality of physical and chemical evaluation such as colour, texture, pH, TA, TSS, and vitamin C were examined every 2 days interval for 12 days at 4ᵒC. Result shows that the PP is the most suitable packaging for banana cv Nipah because it can reduce respiration and physicochemical quality changes of banana cv Nipah. Different types of packaging significantly affected quality of fresh-cut banana cv Nipah. PP bag was the most suitable packaging to maintain quality and prolong storage life of fresh-cut banana cv Nipah for 12 days at 4ᵒC.

Keywords: physicochemical, PP, LDPE, shrink wrap, browning, respiration

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Authors: A. Ardianto, M. A. Putera Agung, S. Pramusandi

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Power waterway is one of dam structures and as an intake vertical tunnel or well function for hydroelectric power plants in Jatigede area, Sumedang, West Java. Gate shaft is also one of parts the power waterway system. The paper concerns some consideration in determining a critical state parameter on the back stability analysis of gate shaft or excavation wall stability during excavation. Study analysis was carried out using without and with reinforcement system. Results study showed that reinforcement shaft could reduce the total displacement and safety factor could increases significantly. Based on the back calculation results, it was recommended to install some reinforcement materials and drainage system to reduce pore water pressure.

Keywords: power waterway, reinforcement, displacement, safety

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Authors: Pejman Hosseinioun, Abolghasem Ghasempour, Elham Gholami, Hamed Sarbazi

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Considering the development in global semiconductor technology, it is anticipated that gadgets such as diodes and resonant transistor tunnels (RTD/RTT), Single electron transistors (SET) and quantum cellular automata (QCA) will substitute CMOS (Complementary Metallic Oxide Semiconductor) gadgets in many applications. Unfortunately, these new technologies cannot disembark the common Boolean logic efficiently and are only appropriate for liminal logic. Therefor there is no doubt that with the development of these new gadgets it is necessary to find new MacDraw technologies which are compatible with them. Resonant transistor tunnels (RTD/RTT) and circuit MacDraw with enhanced computing abilities are candida for accumulating Nano criterion in the future. Quantum cellular automata (QCA) are also advent Nano technological gadgets for electrical circuits. Advantages of these gadgets such as higher speed, smaller dimensions, and lower consumption loss are of great consideration. QCA are basic gadgets in manufacturing gates, fuses and memories. Regarding the complex Nano criterion physical entity, circuit designers can focus on logical and constructional design to decrease complication in MacDraw. Moreover Single electron technology (SET) is another noteworthy gadget considered in Nano technology. This article is a survey in future of Nano technology in digital MacDraw.

Keywords: nano technology, resonant transistor tunnels, quantum cellular automata, semiconductor

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Authors: Poonam A. Trambadia, Ashish V. Trambadia

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The architecture of sultanate period of Ahmedabad had evolved just before the establishment of Mughal rule in North India. After shifting the capital of the kingdom from Patan to Ahmedabad, when the buildings and structures were being built, an interesting cultural blend happened in architecture. Many sultanate buildings in Ahmedabad historic city have resemblance with Patan including the names. Outer fortification walls and Gates were built during the rule of the third ruler in the late 15th century. All the gates had sandstone slabs supported by three arched entrance in sandstone with wooden shutter. A restoration project of Khanpur Gate was initiated in 2016. The paper identifies some evidences and some hidden layers of structures as important elements of cultural interchange while some were just forgotten in the process. The recycling of pre-existing elements of structures are examined and compared. There were layers uncovered that were hidden behind later repairs using traditional brick arch, which was taken out in the process. As the gate had partially collapsed, the restoration included piece by piece dismantling and restoring in the same sequence wherever required. The recycled materials found in the process were recorded and provided the basis for this study. The gate after this discovery sets a new example of fortification Gate built in Sultanate era. The comparison excludes Maratha and British Period Gates to avoid further confusion and focuses on 15th – 16th century sultanate architecture of Ahmedabad.

Keywords: Ahmedabad World Heritage, fortification, Indo-Islamic style, Sultanate architecture, cultural interchange

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Authors: A. Boursali, A. Guen-Bouazza

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

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Authors: Kianoosh Ahadi, Mustafa Ergil

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In this study, the event of vibrations caused by vortexes and the distribution of induced hydrodynamic forces due to vortexes on the sliding gate valves has been investigated. For this reason, a sliding valve with the help of computational fluid dynamics (CFD) software was simulated in two-dimensional )2D(, where the flow and turbulence equations were solved for three different valve openings (full, half, and 16.7 %) models. The variety of vortexes formed within the vicinity of the valve structure was investigated based on time where the trend of fluctuations and their occurrence regions have been detected. From the gathered solution dataset of the numerical simulations, the pressure coefficient (CP), the lift force coefficient (CL), the drag force coefficient (CD), and the momentum coefficient due to hydrodynamic forces (CM) were examined, and relevant figures were generated were from these results, the vortex-induced vibrations were analyzed.

Keywords: induced vibrations, computational fluid dynamics, sliding gate valves, vortexes

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Authors: Z. Kourdi, B. Bouazza, M. Khaouani, A. Guen-Bouazza, Z. Djennati, A. Boursali

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/mm, a peak extrinsic transconductance of 590 mS/mm at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, Silvaco, field plate, genetic algorithm, quantum

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Authors: Nikhil Jain, Yang Xu, Bin Yu

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Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Samson Mil'shtein, Dhawal N. Asthana

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The presented heterostructure n-p-n bipolar transistor is comprised of Ge/GaAs heterojunctions consisting of 0.15µm thick emitter and 0.65µm collector junctions. High diffusivity of carriers in GaAs base was major motivation of current design. We avoided grading of the base which is common in heterojunction bipolar transistors, in order to keep the electron diffusivity as high as possible. The electrons injected into the 0.25µm thick p-type GaAs base with not very high doping (1017cm-3). The designed HBT enables cut off frequency on the order of 150GHz. The Ge/GaAs heterojunctions presented in our paper have proved to work better than comparable HBTs having GaAs bases and emitter/collector junctions made, for example, of AlGaAs/GaAs or other III-V compound semiconductors. The difference in lattice constants between Ge and GaAs is less than 2%. Therefore, there is no need of transition layers between Ge emitter and GaAs base. Significant difference in energy gap of these two materials presents new scope for improving performance of the emitter. With the complete structure being modelled and simulated using TCAD SILVACO, the collector/ emitter offset voltage of the device has been limited to a reasonable value of 63 millivolts by the dint of low energy band gap value associated with Ge emitter. The efficiency of the emitter in our HBT is 86%. Use of Germanium in the emitter and collector regions presents new opportunities for integration of this vertical device structure into silicon substrate.

Keywords: Germanium, Gallium Arsenide, heterojunction bipolar transistor, high cut-off frequency

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Authors: Syakirin O. Yong, Nasrudin A. Rahim, Bilal M. Eid, Buray Tankut

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The aim of this paper is to develop an ultra-fast gate driver for Silicon Carbide (SiC) based switching device applications such as AC/DC DC/AC converters. Wide bandgap semiconductors such as SiC switches are growing rapidly nowadays due to their numerous capabilities such as faster switching, higher power density and higher voltage level. Wide band-gap switches can work properly on high frequencies such 50-250 kHz which is very useful for many power electronic applications such as solar inverters. Increasing the frequency minimizes the output filter size and system complexity however, this causes huge spike between MOSFET’s drain and source leg which leads to the failure of MOSFET if the voltage rating is exceeded. This paper investigates and concludes the optimum design for a gate drive board for SiC MOSFET switches without causing spikes and noises.

Keywords: PV system, lithium-ion, charger, constant current, constant voltage, renewable energy

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Authors: Indre Brazauskaite, Vilte Auruskeviciene

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The paper explores the Stage-Gate framework application for innovation maturity among small and medium-sized enterprises (SMEs). Innovation management becomes an essential business survival process for all sizes of organizations that can be evaluated and audited systemically. This research systemically defines and assesses the innovation process from the perspective of the company’s top management. Empirical research explores attitudes and existing practices of innovation management in SMEs in Baltic countries. It structurally investigates the current innovation management practices, level of standardization, and potential challenges in the area. Findings allow to structure of existing practices based on an institutionalized model and contribute to a more advanced understanding of the innovation process among SMEs. Practically, findings contribute to advanced decision-making and business planning in the process.

Keywords: innovation measure, innovation process, SMEs, stage-gate framework

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Authors: Peihao Huang, Chun Zhao

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Thin-film transistors(TFTs) have the advantages of low power consumption, short reaction time, and have high research value in the field of semiconductors, based on this reason, people have focused on gallium oxide-indium oxide thin-film transistors, a relatively common thin-film transistor, elaborated and analyzed his production process, "aqueous solution method", explained the purpose of each step of operation, and finally explored the influence of potassium ions doped in the channel layer on the electrical properties of the device, as well as the effect of oxygen vacancies on its switching ratio and memory, and summarized the conclusions.

Keywords: aqueous solution, oxygen vacancies, switch ratio, thin-film transistor(TFT)

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Authors: G. S. Dangayach, Gaurav Gaurav, Alok Bihari Singh

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The popularity of vehicles in both industrialized and developing economies led to a rise in the production of tyres. People have become increasingly concerned about the tyre industry's possible environmental impact in the last two decades. The life cycle assessment (LCA) methodology was used to assess the environmental impacts of industrial tyres throughout their life cycle, which included four stages: manufacture, transportation, consumption, and end-of-life. The majority of prior studies focused on tyre recycling and disposal. Only a few studies have been conducted on the environmental impact of tyre production process. LCA methodology was employed to determine the environmental impact of tyre manufacture process (gate to gate) at an Indian firm. Comparative analysis was also conducted to identify the environmental hotspots in various stages of tire manufacturing. This study is limited to gate-to-gate analysis of manufacturing processes with the functional unit of a single tyre weighing 50 kg. GaBi software was used to do both qualitative and quantitative analysis. Different environmental impact indicators are measured in terms of CO2, SO2, NOx, GWP (global warming potential), AP (acidification potential), EP (eutrophication potential), POCP (photochemical oxidant formation potential), and HTP (toxic human potential). The results demonstrate that the major contributor to environmental pollution is electricity. The Banbury process has a very high negative environmental impact, which causes respiratory problems to workers and operators.

Keywords: life cycle assessment (LCA), environmental impact indicators, tyre manufacturing process, environmental impact assessment

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

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Authors: Mehdi Moayyedian, Kazem Abhary, Romeo Marian

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This paper presents an evaluation of a plastic defect in injection molding before it occurs in the process; it is known as the short shot defect. The evaluation of different parameters which affect the possibility of short shot defect is the aim of this paper. The analysis of short shot possibility is conducted via SolidWorks Plastics and Taguchi method to determine the most significant parameters. Finite Element Method (FEM) is employed to analyze two circular flat polypropylene plates of 1 mm thickness. Filling time, part cooling time, pressure holding time, melt temperature and gate type are chosen as process and geometric parameters, respectively. A methodology is presented herein to predict the possibility of the short-shot occurrence. The analysis determined melt temperature is the most influential parameter affecting the possibility of short shot defect with a contribution of 74.25%, and filling time with a contribution of 22%, followed by gate type with a contribution of 3.69%. It was also determined the optimum level of each parameter leading to a reduction in the possibility of short shot are gate type at level 1, filling time at level 3 and melt temperature at level 3. Finally, the most significant parameters affecting the possibility of short shot were determined to be melt temperature, filling time, and gate type.

Keywords: injection molding, plastic defects, short shot, Taguchi method

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Authors: Phanumas Khumsat, Chalermchai Janmane

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Low-voltage instrumentation amplifier has been proposed for 3-lead electrocardiogram measurement system. The circuit’s interference rejection technique is based upon common-mode feed-forwarding where common-mode currents have cancelled each other at the output nodes. The common-mode current for cancellation is generated by means of common-mode sensing and emitter or source followers with resistors employing only one transistor. Simultaneously this particular transistor also provides common-mode feedback to the patient’s right/left leg to further reduce interference entering the amplifier. The proposed designs have been verified with simulations in 0.18-µm CMOS process operating under 1.0-V supply with CMRR greater than 80dB. Moreover ECG signals have experimentally recorded with the proposed instrumentation amplifiers implemented from discrete BJT (BC547, BC558) and MOSFET (ALD1106, ALD1107) transistors working with 1.5-V supply.

Keywords: electrocardiogram, common-mode feedback, common-mode feedforward, communication engineering

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Authors: Pranjali Sharma, Swati Neogi

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Composite pressure vessels are low weight structures mainly used in a variety of applications such as automobiles, aeronautics and chemical engineering. Fiber reinforced polymer (FRP) composite materials offer the simplicity of design and use, high fuel storage capacity, rapid refueling capability, excellent shelf life, minimal infrastructure impact, high safety due to the inherent strength of the pressure vessel, and little to no development risk. Apart from these preliminary merits, the subsidized weight of composite vessels over metallic cylinders act as the biggest asset to the automotive industry, increasing the fuel efficiency. The result is a lightweight, flexible, non-explosive, and non-fragmenting pressure vessel that can be tailor-made to attune with specific applications. The winding pattern of the composite over-wrap is a primary focus while designing a pressure vessel. The critical stresses in the system depend on the thickness, angle and sequence of the composite layers. The composite over-wrap is wound over a plastic liner, whose geometry can be varied for the ease of winding. In the present study, we aim to optimize the FRP vessel geometry that provides an ease in winding and also aids in weight reduction for enhancing the vessel performance. Finite element analysis is used to study the effect of dome geometry, yielding a design with maximum value of burst pressure and least value of vessel weight. The stress and strain analysis of different dome ends along with the cylindrical portion is carried out in ANSYS 19.2. The failure is predicted using different failure theories like Tsai-Wu theory, Tsai-Hill theory and Maximum stress theory. Corresponding to a given winding sequence, the optimum dome geometry is determined for a fixed internal pressure to identify the theoretical value of burst pressure. Finally, this geometry is used to decrease the number of layers to reach the set value of safety in accordance with the available safety standards. This results in decrease in the weight of the composite over-wrap and manufacturing cost of the pressure vessel. An improvement in the overall weight performance of the pressure vessel gives higher fuel efficiency for its use in automobile applications.

Keywords: Compressed Gas Storage, Dome geometry, Theoretical Analysis, Type-4 Composite Pressure Vessel, Improvement in Vessel Weight Performance

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Authors: Hassane Ouazzani Chahdi, Omar Helli, Bourzgui Nour Eddine, Hassan Maher, Ali Soltani

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The real-time knowledge of the NO, NO₂ concentration at high temperature, would allow manufacturers of automobiles to meet the upcoming stringent EURO7 anti-pollution measures for diesel engines. Knowledge of the concentration of each of these species will also enable engines to run leaner (i.e., more fuel efficient) while still meeting the anti-pollution requirements. Our proposed technology is promising in the field of automotive sensors. It consists of nanostructured semiconductors based on gallium nitride and zirconia dioxide. The development of new technologies for selective detection of NO and NO₂ gas species would be a critical enabler of superior depollution. The current response was well correlated to the NO concentration in the range of 0–2000 ppm, 0-2500 ppm NO₂, and 0-300 ppm NH₃ at a temperature of 600.

Keywords: NOₓ sensors, HEMT transistor, anti-pollution, gallium nitride, gas sensor

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Authors: Noha Al Majid, Said Mazer, Moulhime El Bekkali, Catherine Algani, Mahmoud Mehdi

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A low noise figure (NF) and high linearity V-band Low Noise Amplifier (LNA) is reported in this article. The LNA compromises a three-stage cascode configuration. This LNA will be used as a part of a WPAN (Wireless Personal Area Network) receiver in the millimeter-wave band at 60 GHz. It is designed according to the MMIC technology (Monolithic Microwave Integrated Circuit) in PH 15 process from UMS foundry and uses a 0.15 μm GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor). The particularity of this LNA compared to other LNAs in literature is its very low noise figure which is equal to 1 dB and its high linearity (IIP3 is about 22 dB). The LNA consumes 0.24 Watts, achieving a high gain which is about 23 dB, an input return loss better than -10 dB and an output return loss better than -8 dB.

Keywords: low noise amplifier, V-band, MMIC technology, LNA, amplifier, cascode, pseudomorphic high electron mobility transistor (PHEMT), high linearity

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Authors: Jong-Bae Lee, Seongsoo Lee

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Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: local interconnect network, controller, transceiver, processor

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Authors: Karan R. Chavan, Paula Saavalainen, Kumudini V. Marathe, Riitta L. Keiski, Ganapati D. Yadav

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Co-contamination of groundwaters by arsenic in different forms is often observed around the globe. Arsenic is introduced into the waters by several mechanisms and different technologies are proposed and practiced for effective removal. The assessment of three prominent technologies, namely, adsorption, ion exchange and nanofiltration was carried out in this study based on lifecycle methodology. The life of the technologies was divided into two stages: cradle to gate (C-G) and gate to gate (G-G), in order to find out the impacts in different categories of environmental burdens, human health and resource consumption. Life cycle inventory was estimated by use of models and design equations concerning with the different technologies. Regeneration was considered for each technology and over the course of its full lifetime. The impact values of adsorption technology for the C-G stage are greater by thousand times (103) and million times (106) compared to ion exchange and nanofiltration technologies, respectively. The impact of G-G stage of the lifecycle is the major contributor of the impact for all the 3 technologies due to electricity consumption during the operation. Overall, the ion Exchange technology fares well in this study of removal of As (V) only.

Keywords: arsenic, nanofiltration, lifecycle assessment, membrane technology

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Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

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Gate Assignment Problem (GAP) is one of the most substantial issues in airport operation. In principle, GAP intends to maintain the maximum capacity of the airport through the best possible allocation of the resources (gates) in order to reach the optimum outcome. The problem involves a wide range of dependent and independent resources and their limitations, which add to the complexity of GAP from both theoretical and practical perspective. In this study, GAP was mathematically formulated as a three-objective problem. The preliminary goal of multi-objective formulation was to address a higher number of objectives that can be simultaneously optimized and therefore increase the practical efficiency of the final solution. The problem is solved by applying the second version of Non-dominated Sorting Genetic Algorithm (NSGA-II). Results showed that the proposed mathematical model could address most of major criteria in the decision-making process in airport management in terms of minimizing both airport/airline cost and passenger walking distance time. Moreover, the proposed approach could properly find acceptable possible answers.

Keywords: airport management, gate assignment problem, mathematical modeling, genetic algorithm, NSGA-II

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Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

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Assigning aircrafts’ activities to appropriate gates is one the most challenging issues in airport authorities’ multiple criteria decision making. The potential financial loss due to imbalances of demand and supply in congested airports, higher occupation rates of gates, and the existing restrictions to expand facilities provide further evidence for the need for an optimal supply allocation. Passengers walking distance, towing movements, extra fuel consumption (as a result of awaiting longer to taxi when taxi conflicts happen at the apron area), etc. are the major traditional components involved in GAP models. In particular, the total cost associated with gate assignment problem highly depends on the airport terminal layout. The study herein presents a well-elaborated literature review on the topic focusing on major concerns, applicable variables and objectives, as well as proposing a three-objective mathematical model for the gate assignment problem. The model has been tested under different concourse layouts in order to check its performance in different scenarios. Results revealed that terminal layout pattern is a significant parameter in airport and that the proposed model is capable of dealing with key constraints and objectives, which supports its practical usability for future decision making tools. Potential solution techniques were also suggested in this study for future works.

Keywords: airport management, terminal layout, gate assignment problem, mathematical modeling

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Authors: Xuerui Niu, Bolin Wang, Xinchuang Zhang, Xiaohua Ma, Bin Hou, Ling Yang

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The application of discrete GaN-based power switches requires the collaboration of silicon-based peripheral circuit structures. However, the packages and interconnection between the Si and GaN devices can introduce parasitic effects to the circuit, which has great impacts on GaN power transistors. GaN-based monolithic power integration technology is an emerging solution which can improve the stability of circuits and allow the GaN-based devices to achieve more functions. Complementary logic circuits consisting of GaN-based E-mode p-channel heterostructure field-effect transistors (p-HFETs) and E-mode n-channel HEMTs can be served as the gate drivers. E-mode p-HFETs with recessed gate have attracted increasing interest because of the low leakage current and large gate swing. However, they suffer from a poor interface between the gate dielectric and polarized nitride layers. The reliability of p-HFETs is analyzed and discussed in this work. In circuit applications, the inverter is always operated with dynamic gate voltage (VGS) rather than a constant VGS. Therefore, dynamic electrical stress has been simulated to resemble the operation conditions for E-mode p-HFETs. The dynamic electrical stress condition is as follows. VGS is a square waveform switching from -5 V to 0 V, VDS is fixed, and the source grounded. The frequency of the square waveform is 100kHz with the rising/falling time of 100 ns and duty ratio of 50%. The effective stress time is 1000s. A number of stress tests are carried out. The stress was briefly interrupted to measure the linear IDS-VGS, saturation IDS-VGS, As VGS switches from -5 V to 0 V and VDS = 0 V, devices are under negative-bias-instability (NBI) condition. Holes are trapped at the interface of oxide layer and GaN channel layer, which results in the reduction of VTH. The negative shift of VTH is serious at the first 10s and then changes slightly with the following stress time. However, different phenomenon is observed when VDS reduces to -5V. VTH shifts negatively during stress condition, and the variation in VTH increases with time, which is different from that when VDS is 0V. Two mechanisms exists in this condition. On the one hand, the electric field in the gate region is influenced by the drain voltage, so that the trapping behavior of holes in the gate region changes. The impact of the gate voltage is weakened. On the other hand, large drain voltage can induce the hot holes generation and lead to serious hot carrier stress (HCS) degradation with time. The poor-quality interface between the oxide layer and GaN channel layer at the gate region makes a major contribution to the high-density interface traps, which will greatly influence the reliability of devices. These results emphasize that the improved etching and pretreatment processes needs to be developed so that high-performance GaN complementary logics with enhanced stability can be achieved.

Keywords: GaN-based E-mode p-HFETs, dynamic electric stress, threshold voltage, monolithic power integration technology

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Authors: Lin Gong, Holger Göbel

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In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

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Authors: Ghania Zerari, Abderrezak Guessoum, Rachid Beguenane

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This paper introduces high-performance architecture for fully parallel stochastic Low-Density Parity-Check (LDPC) field programmable gate array (FPGA) based LDPC decoder. The new approach is designed to decrease the decoding latency and to reduce the FPGA logic utilisation. To accomplish the target logic utilisation reduction, the routing of the proposed sub-variable node (VN) internal memory is designed to utilize one slice distributed RAM. Furthermore, a VN initialization, using the channel input probability, is achieved to enhance the decoder convergence, without extra resources and without integrating the output saturated-counters. The Xilinx FPGA implementation, of IEEE 802.3an standard LDPC code, shows that the proposed decoding approach attain high performance along with reduction of FPGA logic utilisation.

Keywords: low-density parity-check (LDPC) decoder, stochastic decoding, field programmable gate array (FPGA), IEEE 802.3an standard

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Authors: Deepika Sharma, Bal Krishan

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In this paper, the structure of N-channel VDMOS was designed and analyzed using Silvaco TCAD tools by varying N+ source doping concentration, P-Body doping concentration, gate oxide thickness and the diffuse time. VDMOS is considered to be ideal power switches due to its high input impedance and fast switching speed. The performance of the device was analyzed from the Ids vs Vgs curve. The electrical characteristics such as threshold voltage, gate oxide thickness and breakdown voltage for the proposed device structures were extarcted. Effect of epitaxial layer on various parameters is also observed.

Keywords: on-resistance, threshold voltage, epitaxial layer, breakdown voltage

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Authors: Chingwen Yeh, Yu Ru Chen

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This paper aims to explore the growth and development of children in the creative dance class of Cloud Gate Dance School in Taichung Taiwan. Professor Chingwen Yeh’s qualitative research method was applied in this study. First of all, application of Dalcroze Eurhythmic teaching materials such as music, teaching aids, speaking language through classroom situation was collected and exam. Second, the in-class observation on the participation of the young children's learning situation was recorded both by words and on video screen as the research data. Finally, data analysis was categorized into the following aspects: children's body movement coordination, children’s mind concentration and imagination and children’s verbal expression. Through the in-depth interviews with the in-class teachers, parents of participating children and other in class observers were conducted from time to time; this research found the children's body rhythm, language skills, and social learning growth were improved in certain degree through the creative dance training. These authors hope the study can contribute as the further research reference on the related topic.

Keywords: Cloud Gate Dance School, creative dance, Dalcroze, Eurhythmic

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Authors: Daniel Bülz, Franziska Lüttich, Sreetama Banerjee, Georgeta Salvan, Dietrich R. T. Zahn

Abstract:

For the development of electronics, organic semiconductors are of great interest due to their adjustable optical and electrical properties. Especially for spintronic applications they are interesting because of their weak spin scattering, which leads to longer spin life times compared to inorganic semiconductors. It was shown that some organic materials change their resistance if an external magnetic field is applied. Pentacene is one of the materials which exhibit the so called photoinduced magnetoresistance which results in a modulation of photocurrent when varying the external magnetic field. Also the soluble derivate of pentacene, the 6,13-bis (triisopropylsilylethynyl)-pentacene (TIPS-pentacene) exhibits the same negative magnetoresistance. Aiming for simpler fabrication processes, in this work, we compare TIPS-pentacene organic field effect transistors (OFETs) made from solution with those fabricated by thermal evaporation. Because of the different processing, the TIPS-pentacene thin films exhibit different morphologies in terms of crystal size and homogeneity of the substrate coverage. On the other hand, the interface treatment is known to have a high influence on the threshold voltage, eliminating trap states of silicon oxide at the gate electrode and thereby changing the electrical switching response of the transistors. Therefore, we investigate the influence of interface treatment using octadecyltrichlorosilane (OTS) or using a simple cleaning procedure with acetone, ethanol, and deionized water. The transistors consist of a prestructured OFET substrates including gate, source, and drain electrodes, on top of which TIPS-pentacene dissolved in a mixture of tetralin and toluene is deposited by drop-, spray-, and spin-coating. Thereafter we keep the sample for one hour at a temperature of 60 °C. For the transistor fabrication by thermal evaporation the prestructured OFET substrates are also kept at a temperature of 60 °C during deposition with a rate of 0.3 nm/min and at a pressure below 10-6 mbar. The OFETs are characterized by means of optical microscopy in order to determine the overall quality of the sample, i.e. crystal size and coverage of the channel region. The output and transfer characteristics are measured in the dark and under illumination provided by a white light LED in the spectral range from 450 nm to 650 nm with a power density of (8±2) mW/cm2.

Keywords: organic field effect transistors, solution processed, surface treatment, TIPS-pentacene

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Authors: Mert Kıranç, Ekrem Duman, Murat Özbilen

Abstract:

In order to achieve new product development (NPD) activities on time and within budgetary constraints, the NPD managers need a well-designed methodology. This study intends to create an integrated project management methodology for the ones who focus on new product development projects. In the scope of the study, four different management systems are combined. These systems are called as 'Schedule-oriented Stage-Gate Method, Risk Management, Change Management and Earned Value Management'. New product development term is quite common in many different industries such as defense industry, construction, health care/dental, higher education, fast moving consumer goods, white goods, electronic devices, marketing and advertising and software development. All product manufacturers run against each other’s for introducing a new product to the market. In order to achieve to produce a more competitive product in the market, an optimum project management methodology is chosen, and this methodology is adapted to company culture. The right methodology helps the company to present perfect product to the customers at the right time. The benefits of proposed methodology are discussed as an application by a company. As a result, how the integrated methodology improves the efficiency and how it achieves the success of the project are unfolded.

Keywords: project, project management, management methodology, new product development, risk management, change management, earned value, stage-gate

Procedia PDF Downloads 291