Search results for: Shobha.K.R.

Authors: G. N. Srinivasan, G. Shobha

Abstract:

This paper presents an overview of the methodologies and algorithms for statistical texture analysis of 2D images. Methods for digital-image texture analysis are reviewed based on available literature and research work either carried out or supervised by the authors.

Keywords: Image Texture, Texture Analysis, Statistical Approaches, Structural approaches, spectral approaches, Morphological approaches, Fractals, Fourier Transforms, Gabor Filters, Wavelet transforms.

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Authors: D. Shobha Rani, M. Muralidhar

Abstract:

Solar photovoltaic (SPV) power systems can be employed as electrical power sources to meet the daily residential energy needs of rural areas that have no access to grid systems. In view of this, a standalone SPV powered air cooling system is proposed in this paper, which constitutes a dc-dc boost converter, two voltage source inverters (VSI) connected to two brushless dc (BLDC) motors which are coupled to a centrifugal water pump and a fan blower. A simple and efficient Maximum Power Point Tracking (MPPT) technique based on Silver Mean Method (SMM) is utilized in this paper. The air cooling system is developed and simulated using the MATLAB / Simulink environment considering the dynamic and steady state variation in the solar irradiance.

Keywords: Boost converter, solar photovoltaic array, voltage source inverter, brushless DC motor, solar irradiance, Maximum Power Point Tracking, Silver Mean Method.

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Authors: Shobha Sharma, Amita Dev, Akanksha Kant

Abstract:

Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.

Keywords: Detection of edges, Vedic multiplier, image processing, Urdhva Tiryakbhyam sutra.

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Authors: Shobha.K.R., K. Rajanikanth

Abstract:

An on-demand routing protocol for wireless ad hoc networks is one that searches for and attempts to discover a route to some destination node only when a sending node originates a data packet addressed to that node. In order to avoid the need for such a route discovery to be performed before each data packet is sent, such routing protocols must cache routes previously discovered. This paper presents an analysis of the effect of intelligent caching in a non clustered network, using on-demand routing protocols in wireless ad hoc networks. The analysis carried out is based on the Dynamic Source Routing protocol (DSR), which operates entirely on-demand. DSR uses the cache in every node to save the paths that are learnt during route discovery procedure. In this implementation, caching these paths only at intermediate nodes and using the paths from these caches when required is tried. This technique helps in storing more number of routes that are learnt without erasing the entries in the cache, to store a new route that is learnt. The simulation results on DSR have shown that this technique drastically increases the available memory for caching the routes discovered without affecting the performance of the DSR routing protocol in any way, except for a small increase in end to end delay.

Keywords: Caching, DSR, on demand routing, MANET.

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Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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