Search results for: optoelectronic hardware

Authors: Abdullah Bal, Sevdenur Bal

Abstract:

This paper purposes a new type of hardware application for training of cellular neural networks (CNN) using optical joint transform correlation (JTC) architecture for image feature extraction. CNNs require much more computation during the training stage compare to test process. Since optoelectronic hardware applications offer possibility of parallel high speed processing capability for 2D data processing applications, CNN training algorithm can be realized using Fourier optics technique. JTC employs lens and CCD cameras with laser beam that realize 2D matrix multiplication and summation in the light speed. Therefore, in the each iteration of training, JTC carries more computation burden inherently and the rest of mathematical computation realized digitally. The bipolar data is encoded by phase and summation of correlation operations is realized using multi-object input joint images. Overlapping properties of JTC are then utilized for summation of two cross-correlations which provide less computation possibility for training stage. Phase-only JTC does not require data rearrangement, electronic pre-calculation and strict system alignment. The proposed system can be incorporated simultaneously with various optical image processing or optical pattern recognition techniques just in the same optical system.

Keywords: CNN training, image processing, joint transform correlation, optoelectronic hardware

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Authors: Der-Feng Guo

Abstract:

Optoelectronic switches have attracted a considerable attention in the semiconductor research field due to their potential applications in optical computing systems and optoelectronic integrated circuits (OEICs). With high gains and high-speed operations, npn heterostructures can be used to produce promising optoelectronic switches. It is known that the bulk barrier and heterostructure-induced potential spike act important roles in the characteristics of the npn heterostructures. To investigate the effects of bulk barrier and potential spike heights on the optoelectronic switching of the npn heterostructures, GaAs/InGaP and AlGaAs/GaAs/InAlGaP npn heterostructural optoelectronic switches (HSOSs) have been fabricated in this work. It is seen that the illumination decreases the switching voltage Vs and increases the switching current Is, and thus the OFF state is under dark and ON state under illumination in the optical switching of the GaAs/InGaP HSOS characteristics. But in the AlGaAs/GaAs/InAlGaP HSOS characteristics, the Vs and Is present contrary trends, and the OFF state is under illumination and ON state under dark. The studied HSOSs show quite different switching variations with incident light, which are mainly attributed to the bulk barrier and potential spike heights affected by photogenerated carriers.

Keywords: bulk barrier, heterostructure, optoelectronic switch, potential spike

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Authors: Mohamed Achehboune, Mohammed Khenfouch, Issam Boukhoubza, Bakang Mothudi, Izeddine Zorkani, Anouar Jorio

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Zinc Oxide (ZnO) nanostructures have been attracting growing interest in recent years; their optical and electrical properties make them useful as attractive and promising materials for optoelectronic applications. In this study, pure and Hafnium doped ZnO nanostructures were synthesized using a green processing method. The structural, optical and electrical properties of samples were investigated structural and optical spectroscopies and electrical measurements. The synthesis and chemical composition of pure and Hafnium doped ZnO were confirmed by SEM observation. The XRD studies of Hafnium doped ZnO demonstrate the formation of wurtzite structure with preferred c-axis orientation. Moreover, the optical and electrical properties of doped material have improved after the doping process. The experimental results obtained for our material show that Hf doped ZnO nanostructures could be a promising material in optoelectronic applications such as photovoltaic cell and light emitting diode devices.

Keywords: green synthesis, hafnium-doped-zinc oxide, nanostructures, optoelectronic

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Authors: B. Bouktif, M. Gaidi, M. Benrabha

Abstract:

Metal-nano particle-assisted chemical etching is an extraordinary developed wet etching method of producing uniform semiconductor nanostructure (nanowires) from the patterned metallic film on the crystalline silicon surface. The metal films facilitate the etching in HF and H2O2 solution and produce silicon nanowires (SiNWs). Creation of different SiNWs morphologies by changing the etching time and its effects on optical and optoelectronic properties was investigated. Combination effect of formed SiNWs and stain etching treatment in acid (HF/HNO3/H2O) solution on the surface morphology of Si wafers as well as on the optical and optoelectronic properties are presented in this paper.

Keywords: semiconductor nanostructure, chemical etching, optoelectronic property, silicon surface

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Authors: Issam Derkaoui, Mohammed Khenfouch, Bakang M. Mothudi, Malik Maaza, Izeddine Zorkani, Anouar Jorio

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Transition metal oxides nanoparticles with different morphologies have attracted a lot of attention recently owning to their distinctive geometries, and demonstrated promising electrical properties for various applications. In this paper, we discuss the time and annealing effects on the structural and electrical properties of vanadium oxides nanoparticles (VO-NPs) prepared by microwave method. In this sense, transmission electron microscopy (TEM), X-ray diffraction (XRD), Raman Spectroscopy, Ultraviolet-visible absorbance spectra (Uv-Vis) and electrical conductivity were investigated. Hence, the annealing state and the time are two crucial parameters for the improvement of the optoelectronic properties. The use of these nanostructures is promising way for the development of technological applications especially for energy storage devices.

Keywords: Vanadium oxide, Microwave, Electrical conductivity, Optoelectronic properties

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: B. Bouadjemia, M. Houaria, S. Haida, Y. B. Idriss, A, Akham, M. Matouguia, A. Gasmia, T. Lantria, S. Bentataa

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It have investigated the structural, optoelectronic, elastic and thermodynamic properties of KGeX₃ (X = F, Cl and Br) using the density functional theory (DFT) with generalized gradient approximation (GGA) for potential exchange correlation. The modified Becke-Johnson (mBJ-GGA) potential approximation is also used for calculating the optoelectronic properties of the material.The results show that the band structure of the metalloid halide perovskites KGeX₃ (X = F, Cl and Br) have a semiconductor behavior with direct band gap at R-R direction, the gap energy values for each compound as following: 2.83, 1.27 and 0.79eV respectively. The optical properties, such as real and imaginary parts of the dielectric functions, refractive index, reflectivity and absorption coefficient, are investigated. As results, these compounds are competent candidates for optoelectronic and photovoltaic devices in this range of the energy spectrum.

Keywords: density functional theory (DFT), semiconductor behavior, metalloid halide perovskites, optical propertie and photovoltaic devices

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Authors: Seyong Oh, Jin-Hong Park

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Recently, neuromorphic computing based on brain-inspired artificial neural networks (ANNs) has attracted huge amount of research interests due to the technological abilities to facilitate massively parallel, low-energy consuming, and event-driven computing. In particular, research on artificial synapse that imitate biological synapses responsible for human information processing and memory is in the spotlight. Here, we demonstrate a photosynaptic device, wherein a synaptic weight is governed by a mixed spike consisting of voltage and light spikes. Compared to the device operated only by the voltage spike, ∆G in the proposed photosynaptic device significantly increased from -2.32nS to 5.95nS with no degradation of nonlinearity (NL) (potentiation/depression values were changed from 4.24/8 to 5/8). Furthermore, the Modified National Institute of Standards and Technology (MNIST) digit pattern recognition rates improved from 36% and 49% to 50% and 62% in ANNs consisting of the synaptic devices with 20 and 100 weight states, respectively. We expect that the photosynaptic device technology processed by optoelectronic spike will play an important role in implementing the neuromorphic computing systems in the future.

Keywords: optoelectronic synapse, IGZO (Indium-Gallium-Zinc Oxide) photosynaptic device, optoelectronic spiking process, neuromorphic computing

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Authors: Jun Young Moon, Hyeonggeon Lee, Jong Tae Kim

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In this paper, we present Cortex-M3 based virtual platform which can virtualize wearable hardware platform and evaluate hardware performance. Cortex-M3 is very popular microcontroller in wearable devices, hardware sensors and display devices. This platform can be used to implement software layer for specific hardware architecture. By using the proposed platform the software development process can be parallelized with hardware development process. We present internal mechanism to implement the proposed virtual platform and describe how to use the proposed platform to develop software by using case study which is low cost wearable device that uses Cortex-M3.

Keywords: electronic system level design, software development, virtual platform, wearable device

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Fariborz Ahmadi, Reza Tati

Abstract:

Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only do not this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.

Keywords: hardware, genetic algorithm, computer science, engineering

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Ziyuan Wu, Yulong Jia, Xiang Zhang, Wanting Zhou, Lei Li

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The Internet of Things (IoT) is a rapidly evolving field involving a large number of interconnected embedded devices. In the design of embedded System-on-Chip (SoC), the key issues are power consumption, performance, and security. However, the easy-to-implement software and untrustworthy third-party IP cores may threaten the safety of hardware assets. Considering that illegal access and malicious attacks against SoC resources pass through the bus that integrates IPs, we propose a Lightweight Hardware Firewall (LHF) to protect SoC, which monitors and disallows the offending bus transactions based on physical addresses. Furthermore, under the LHF architecture, this paper refines two types of firewalls: Destination Hardware Firewall (DHF) and Source Hardware Firewall (SHF). The former is oriented to fine-grained detection and configuration, whose core technology is based on the method of dynamic grading units. In addition, we design the SHF based on static entries to achieve lightweight. Finally, we evaluate the hardware consumption of the proposed method by both Field-Programmable Gate Array (FPGA) and IC. Compared with the exciting efforts, LHF introduces a bus latency of zero clock cycles for every read or write transaction implemented on Xilinx Kintex-7 FPGAs. Meanwhile, the DC synthesis results based on TSMC 90nm show that the area is reduced by about 25% compared with the previous method.

Keywords: IoT, security, SoC, bus architecture, lightweight hardware firewall, FPGA

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Authors: Tarek El-Derini, Ahmed El-Shenawy

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This paper presents the hardware implemented and validation for a special system to assist the unprofessional users of car with back trailers. The system consists of two platforms; the front car platform (C) and the trailer platform (T). The main objective is to control the Trailer platform using the actuators found in the front platform (c). The mobility of the platform (C) is investigated and inverse and forward kinematics model is obtained for both platforms (C) and (T). The system is simulated using Matlab M-file and the simulation examples results illustrated the system performance. The system is constructed with a hardware setup for the front and trailer platform. The hardware experimental results and the simulated examples outputs showed the validation of the hardware setup.

Keywords: kinematics, modeling, robot, MATLAB

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Authors: Nikolaos Georgoulopoulos, Alkis Hatzopoulos, Konstantinos Karamitsios, Konstantinos Kotrotsios, Alexandros I. Metsai

Abstract:

In modern server systems, business critical applications run in different types of infrastructure, such as cloud systems, physical machines and virtualization. Often, due to high load and over time, various hardware faults occur in servers that translate to errors, resulting to malfunction or even server breakdown. CPU, RAM and hard drive (HDD) are the hardware parts that concern server administrators the most regarding errors. In this work, selected RAM, HDD and CPU errors, that have been observed or can be simulated in kernel ring buffer log files from two groups of Linux servers, are investigated. Moreover, a severity characterization is given for each error type. Better understanding of such errors can lead to more efficient analysis of kernel logs that are usually exploited for fault diagnosis and prediction. In addition, this work summarizes ways of simulating hardware errors in RAM and HDD, in order to test the error detection and correction mechanisms of a Linux server.

Keywords: hardware errors, Kernel logs, Linux servers, RAM, hard disk, CPU

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Authors: Qingqing Gai, Junxing Shen, Yu Luo

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Due to the hardware architecture characteristics, some operators tend to acquire better performance if the input/output tensor dimensions are aligned to a certain minimum granularity, such as convolution and deconvolution commonly used in deep learning. Furthermore, if the requirements are not met, the general strategy is to pad with 0 to satisfy the requirements, potentially leading to the under-utilization of the hardware resources. Therefore, for the convolution and deconvolution whose input and output channels do not meet the minimum granularity alignment, we propose to transfer the W-dimensional data to the C-dimension for computation (W2C) to enable the C-dimension to meet the hardware requirements. This scheme also reduces the number of computations in the W-dimension. Although this scheme substantially increases computation, the operator’s speed can improve significantly. It achieves remarkable speedups on multiple hardware accelerators, including Nvidia Tensor cores, Qualcomm digital signal processors (DSPs), and Huawei neural processing units (NPUs). All you need to do is modify the network structure and rearrange the operator weights offline without retraining. At the same time, for some operators, such as the Reducemax, we observe that transferring the Cdimensional data to the W-dimension(C2W) and replacing the Reducemax with the Maxpool can accomplish acceleration under certain circumstances.

Keywords: convolution, deconvolution, W2C, C2W, alignment, hardware accelerator

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Authors: Ashish Soni, Suman Kalyan Pal

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Transition metal dichalcogenides (TMDCs) are an emerging paradigm for the generation of advanced materials which are capable of utilizing in future device applications. In recent years TMDCs have attracted researchers for their unique band structure in monolayers. Large-area monolayers could become the most appropriate candidate for flexible and thin optoelectronic devices. For this purpose, it is crucial to understand the generation and transport of charge carriers in low dimensions. A deep understanding of photo-generated hot charges and trapped charges is essential to improve the performance of optoelectronic devices. Carrier trapping by the defect states that are introduced during the growth process of the monolayer could influence the dynamical behaviour of charge carriers. Herein, we investigated some aspects of the ultrafast evolution of the initially generated hot carriers and trapped charges in large-area monolayer WS₂ by measuring transient absorption at energies above and below the band gap energy. Our excitation density and energy-dependent measurements reveal the trapping of the initially generated charge carrier. Our results could be beneficial for the development of TMDC-based optoelectronic devices.

Keywords: transient absorption, optoelectronics, 2D materials, TMDCs, exciton

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Authors: Ha Thi Nguyen, Guangya Yang, Arne Hejde Nielsen, Peter Højgaard Jensen

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Automatic voltage regulator (AVR) plays an important role in volt/var control of synchronous condenser (SC) in power systems. Test AVR performance in steady-state and dynamic conditions in real grid is expensive, low efficiency, and hard to achieve. To address this issue, we implement hardware-in-the-loop (HiL) test for the AVR of SC to test the steady-state and dynamic performances of AVR in different operating conditions. Startup procedure of the system and voltage set point changes are studied to evaluate the AVR hardware response. Overexcitation, underexcitation, and AVR set point loss are tested to compare the performance of SC with the AVR hardware and that of simulation. The comparative results demonstrate how AVR will work in a real system. The results show HiL test is an effective approach for testing devices before deployment and is able to parameterize the controller with lower cost, higher efficiency, and more flexibility.

Keywords: automatic voltage regulator, hardware-in-the-loop, synchronous condenser, real time digital simulator

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Authors: B. Bouadjemi, S. Bentata, T. Lantri, Souidi Amel, W.Bensaali, A. Zitouni, Z. Aziz

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We performed first-principle calculations, the full-potential linearized augmented plane wave (FP-LAPW) method is used to calculate structural, optoelectronic and magnetic properties of cubic halide perovskites CsPbX3 (X= F,I). We employed for this study the GGA approach and for exchange is modeled using the modified Becke-Johnson (mBJ) potential to predicting the accurate band gap of these materials. The optical properties (namely: the real and imaginary parts of dielectric functions, optical conductivities and absorption coefficient absorption make this halide perovskites promising materials for solar cells applications.

Keywords: halide perovskites, mBJ, solar cells, FP-LAPW, optoelectronic properties, absorption coefficient

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Authors: Seda Yavuz, Anıl Çelebi, Aysun Taşyapı Çelebi, Oğuzhan Urhan

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Nowadays, demand for using real-time video transmission capable devices is ever-increasing. So, high resolution videos have made efficient video compression techniques an essential component for capturing and transmitting video data. Motion estimation has a critical role in encoding raw video. Hence, various motion estimation methods are introduced to efficiently compress the video. Low bit‑depth representation based motion estimation methods facilitate computation of matching criteria and thus, provide small hardware footprint. In this paper, a hardware implementation of a two-bit transformation based low-complexity motion estimation method using local binary pattern approach is proposed. Image frames are represented in two-bit depth instead of full-depth by making use of the local binary pattern as a binarization approach and the binarization part of the hardware architecture is explained in detail. Experimental results demonstrate the difference between the proposed hardware architecture and the architectures of well-known low-complexity motion estimation methods in terms of important aspects such as resource utilization, energy and power consumption.

Keywords: binarization, hardware architecture, local binary pattern, motion estimation, two-bit transform

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Authors: Harmel Meriem

Abstract:

The optoelectronic properties and high power conversion efficiency make lead halide perovskites ideal material for solar cell applications. However, the toxic nature of lead and the instability of organic cation are the two key challenges in the emerging perovskite solar cells. To overcome these challenges, we present our study about finding potential alternatives to lead in the form of A2BX6 perovskite using the first principles DFT-based calculations. The highly accurate modified Becke Johnson (mBJ) and hybrid functional (HSE06) have been used to investigate the Main Document Click here to view linked References to optoelectronic and thermoelectric properties of A2PdBr6 (A = K, Rb, and Cs) perovskite. The results indicate that different A-cations in A2PdBr6 can significantly alter their electronic and optical properties. Calculated band structures indicate semiconducting nature, with band gap values of 1.84, 1.53, and 1.54 eV for K2PdBr6, Rb2PdBr6, and Cs2PdBr6, respectively. We find strong optical absorption in the visible region with small effective masses for A2PdBr6. The ideal band gap and optimum light absorption suggest Rb2PdBr6 and Cs2PdBr6 potential candidates for the light absorption layer in perovskite solar cells. Additionally.

Keywords: soler cell, double perovskite, optoelectronic properties, ab-inotio study

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Authors: Jade Martínez-Llinàs, Pere Colet

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By exploring the possible dynamical regimes in a prototypical model for mutually delay-coupled OEOs, here it is shown that two mutually coupled non-identical OEOs, besides in- and out-of-phase square-waves, can generate stable square-wave pulses synchronized at a quarter of the period (T/4) in a broad parameter region. The key point to obtain T/4 solutions is that the two OEO operate with mixed feedback, namely with negative feedback in one and positive in the other. Furthermore, the coexistence of multiple solutions provides a large degree of flexibility for tuning the frequency in the GHz range without changing any parameter. As a result the two coupled OEOs system is good candidate to be implemented for information encoding as a high-capacity memory device.

Keywords: nonlinear optics, optoelectronic oscillators, square waves, synchronization

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Authors: M. Zyczkowski, P. Markowski, M. Karol

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The team from IOE MUT is developing fiber optic sensors for the security systems for 15 years. The conclusions of the work indicate that these sensors are complicated. Moreover, these sensors are expensive to produce and require sophisticated signal processing methods.We present the results of the investigations of three different applications of the modalmetric sensor: • Protection of museum collections and heritage buildings, • Protection of fiber optic transmission lines, • Protection of objects of critical infrastructure. Each of the presented applications involves different requirements for the system. The results indicate that it is possible to developed a fiber optic sensor based on a single fiber. Modification of optoelectronic parts with a change of the length of the sensor and the method of reflections of propagating light at the end of the sensor allows to adjust the system to the specific application.

Keywords: modalmetric fiber optic sensor, security sensor, optoelectronic parts, signal processing

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Authors: Kyung-Jung Lee, Hyun-Sik Ahn

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This paper suggests a design methodology for the hardware and software of the Electronic Control Unit (ECU) of safety-critical vehicle applications such as braking and steering. The architecture of the hardware is a high integrity system such that it incorporates a high performance 32-bit CPU and a separate Peripheral Control-Processor (PCP) together with an external watchdog CPU. Communication between the main CPU and the PCP is executed via a common area of RAM and events on either processor which are invoked by interrupts. Safety-related software is also implemented to provide a reliable, self-testing computing environment for safety critical and high integrity applications. The validity of the design approach is shown by using the Hardware-in-the-Loop Simulation (HILS) for Electric Power Steering (EPS) systems which consists of the EPS mechanism, the designed ECU, and monitoring tools.

Keywords: electronic control unit, electric power steering, functional safety, hardware-in-the-loop simulation

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Authors: T. Damak, S. Houidi, M. A. Ben Ayed, N. Masmoudi

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The Versatile Video Coding standard (VVC) is actually under development by the Joint Video Exploration Team (or JVET). An Adaptive Multiple Transforms (AMT) approach was announced. It is based on different transform modules that provided an efficient coding. However, the AMT solution raises several issues especially regarding the complexity of the selected set of transforms. This can be an important issue, particularly for a future industrial adoption. This paper proposed an efficient hardware implementation of the most used transform in AMT approach: the DCT II. The developed circuit is adapted to different block sizes and can reach a minimum frequency of 192 MHz allowing an optimized execution time.

Keywords: adaptive multiple transforms, AMT, DCT II, hardware, transform, versatile video coding, VVC

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Authors: Ahmed Raza Khan

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Local-strain engineering is an exciting approach to tune the optoelectronic properties of materials and enhance the performance of devices. Two dimensional (2D) materials such as 2D transition metal dichalcogenides (TMDCs) are particularly well-suited for this purpose because they have high flexibility and can withstand high deformations before rupture. Wrinkles on thick TMDC layers have been reported to show the interesting photoluminescence enhancement due to bandgap modulation and funneling effect. However, the wrinkles in ultrathin TMDCs have not been investigated, because the wrinkles can easily fall down to form folds in these ultrathin layers of TMDCs. Here, we have achieved both wrinkle and fold nano-structures simultaneously on 1-3L WS₂ using a new fabrication technique. The comparable layer dependent reduction in surface potential is observed for both folded layers and corresponding perfect pack layers due to the dominant interlayer screening effect. The strains produced from the wrinkle nanostructures considerably vary semi conductive junction properties. Thermo-ionic modelling suggests that the strained (1.6%) wrinkles can lower the Schottky barrier height (SBH) by 20%. The photo-generated carriers would further significantly lower the SBH. These results present an important advance towards controlling the optoelectronic properties of atomically thin WS₂ using strain engineering, with important implications for practical device applications.

Keywords: strain engineering, folding, WS₂, Kelvin probe force microscopy, KPFM, surface potential, photo current, layer dependence

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Authors: Arslan Usman, Abdul Sattar, Hamid Latif, Afshan Ashfaq, Muhammad Rafique, Martin Koch

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Two-dimensional materials have promising applications in optoelectronic and photonics; MoS₂ is the pioneer 2D material in the family of transition metal dichalcogenides. Its optical, optoelectronic, and structural properties are of practical importance along with its exciton dynamics. Exciton, along with exciton complexes, plays a vital role in realizing quantum devices. MoS₂ monolayers were synthesized using chemical vapour deposition (CVD) technique on SiO₂ and hBN substrates. Photoluminescence spectroscopy (PL) was used to identify the monolayer, which also reflects the substrate based peak broadening due to screening effects. In-plane and out of plane characteristic vibrational modes E¹₂g and A₁g, respectively, were detected in a different configuration on the substrate. The B-excitons and trions showed a dominant feature at low temperatures due to electron-phonon coupling effects, whereas their energies are separated by 100 meV.

Keywords: 2D materials, photoluminescence, AFM, excitons

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Authors: Melissa Chavez Portillo, Hector Juarez Santiesteban, Mauricio Pacio Castillo, Oscar Portillo Moreno

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Nanocrystalline Li-doped PbS thin films have been deposited by chemical bath deposition technique. The goal of this work is to study the modification of the optoelectronic and structural properties of Lithium incorporation. The increase of Li doping in PbS thin films leads to an increase of band gap in the range of 1.4-2.3, consequently, quantum size effect becomes pronounced in the Li-doped PbS films, which lead to a significant enhancement in the optical band gap. Doping shows influence in the film growth and results in a reduction of crystallite size from 30 to 14 nm. The refractive index was calculated and a relationship with dielectric constant was investigated. The dc conductivities of Li-doped and undoped samples were measured in the temperature range 290-340K, the conductivity increase with increase of Lithium content in the PbS films.

Keywords: doping, quantum confinement, optical band gap, PbS

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Authors: Reza Karami, Ali Akbar Ebrahimi

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This paper discusses concurrent engineering of robot manipulators, based on the Holistic Concurrent Design (HCD) methodology and by using a hardware-in-the-loop simulation platform. The methodology allows for considering numerous design variables with different natures concurrently. It redefines the ultimate goal of design based on the notion of satisfaction, resulting in the simplification of the multi-objective constrained optimization process. It also formalizes the effect of designer’s subjective attitude in the process. To enhance modeling efficiency for both computation and accuracy, a hardware-in-the-loop simulation platform is used, which involves physical joint modules and the control unit in addition to the software modules. This platform is implemented in the HCD design architecture to reliably evaluate the design attributes and performance super criterion during the design process. The resulting overall architecture is applied to redesigning kinematic, dynamic and control parameters of an industrial robot manipulator.

Keywords: concurrent engineering, hardware-in-the-loop simulation, robot manipulator, multidisciplinary systems, mechatronics

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