Search results for: Parallel Pipeline Router Architecture
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 1519

Search results for: Parallel Pipeline Router Architecture

1189 Data Mining Approach for Commercial Data Classification and Migration in Hybrid Storage Systems

Authors: Mais Haj Qasem, Maen M. Al Assaf, Ali Rodan

Abstract:

Parallel hybrid storage systems consist of a hierarchy of different storage devices that vary in terms of data reading speed performance. As we ascend in the hierarchy, data reading speed becomes faster. Thus, migrating the application’ important data that will be accessed in the near future to the uppermost level will reduce the application I/O waiting time; hence, reducing its execution elapsed time. In this research, we implement trace-driven two-levels parallel hybrid storage system prototype that consists of HDDs and SSDs. The prototype uses data mining techniques to classify application’ data in order to determine its near future data accesses in parallel with the its on-demand request. The important data (i.e. the data that the application will access in the near future) are continuously migrated to the uppermost level of the hierarchy. Our simulation results show that our data migration approach integrated with data mining techniques reduces the application execution elapsed time when using variety of traces in at least to 22%.

Keywords: Data mining, hybrid storage system, recurrent neural network, support vector machine.

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1188 Privacy-Preserving Location Sharing System with Client/Server Architecture in Mobile Online Social Network

Authors: Xi Xiao, Chunhui Chen, Xinyu Liu, Guangwu Hu, Yong Jiang

Abstract:

Location sharing is a fundamental service in mobile Online Social Networks (mOSNs), which raises significant privacy concerns in recent years. Now, most location-based service applications adopt client/server architecture. In this paper, a location sharing system, named CSLocShare, is presented to provide flexible privacy-preserving location sharing with client/server architecture in mOSNs. CSLocShare enables location sharing between both trusted social friends and untrusted strangers without the third-party server. In CSLocShare, Location-Storing Social Network Server (LSSNS) provides location-based services but do not know the users’ real locations. The thorough analysis indicates that the users’ location privacy is protected. Meanwhile, the storage and the communication cost are saved. CSLocShare is more suitable and effective in reality.

Keywords: Client/server architecture, location sharing, mobile online social networks, privacy-preserving.

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1187 Service Architecture for 3rd Party Operator's Participation

Authors: F. Sarabchi, A. H. Darvishan, H. Yeganeh, H. Ahmadian

Abstract:

Next generation networks with the idea of convergence of service and control layer in existing networks (fixed, mobile and data) and with the intention of providing services in an integrated network, has opened new horizon for telecom operators. On the other hand, economic problems have caused operators to look for new source of income including consider new services, subscription of more users and their promotion in using morenetwork resources and easy participation of service providers or 3rd party operators in utilizing networks. With this requirement, an architecture based on next generation objectives for service layer is necessary. In this paper, a new architecture based on IMS model explains participation of 3rd party operators in creation and implementation of services on an integrated telecom network.

Keywords: Service model, IMS, API, Scripting language, JAIN, Parlay.

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1186 Requirements Driven Multiple View Paradigm for Developing Security Architecture

Authors: K. Chandra Sekaran

Abstract:

This paper describes a paradigmatic approach to develop architecture of secure systems by describing the requirements from four different points of view: that of the owner, the administrator, the user, and the network. Deriving requirements and developing architecture implies the joint elicitation and describing the problem and the structure of the solution. The view points proposed in this paper are those we consider as requirements towards their contributions as major parties in the design, implementation, usage and maintenance of secure systems. The dramatic growth of the technology of Internet and the applications deployed in World Wide Web have lead to the situation where the security has become a very important concern in the development of secure systems. Many security approaches are currently being used in organizations. In spite of the widespread use of many different security solutions, the security remains a problem. It is argued that the approach that is described in this paper for the development of secure architecture is practical by all means. The models representing these multiple points of view are termed the requirements model (views of owner and administrator) and the operations model (views of user and network). In this paper, this multiple view paradigm is explained by first describing the specific requirements and or characteristics of secure systems (particularly in the domain of networks) and the secure architecture / system development methodology.

Keywords: Multiple view paradigms, requirements model, operations model, secure system, owner, administrator, user, network.

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1185 Quality Function Deployment Application in Sewer Pipeline Assessment

Authors: Khalid Kaddoura, Tarek Zayed

Abstract:

Infrastructure assets are essential in urban cities; their purpose is to facilitate the public needs. As a result, their conditions and states shall always be monitored to avoid any sudden malfunction. Sewer systems, one of the assets, are an essential part of the underground infrastructure as they transfer sewer medium to designated areas. However, their conditions are subject to deterioration due to ageing. Therefore, it is of great significance to assess the conditions of pipelines to avoid sudden collapses. Current practices of sewer pipeline assessment rely on industrial protocols that consider distinct defects and grades to conclude the limited average or peak score of the assessed assets. This research aims to enhance the evaluation by integrating the Quality Function Deployment (QFD) and the Decision-Making Trial and Evaluation Laboratory (DEMATEL) methods in assessing the condition of sewer pipelines. The methodology shall study the cause and effect relationship of the systems’ defects to deduce the relative influence weights of each defect. Subsequently, the overall grade is calculated by aggregating the WHAT’s and HOW’s of the House of Quality (HOQ) using the computed relative weights. Thus, this study shall enhance the evaluation of the assets to conclude informative rehabilitation and maintenance plans for decision makers.

Keywords: Condition assessment, DEMATEL, QFD, sewer pipelines.

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1184 FPGA Implementation of the “PYRAMIDS“ Block Cipher

Authors: A. AlKalbany, H. Al hassan, M. Saeb

Abstract:

The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: FPGA, VHDL, micro-architecture, encryption, cryptography, algorithm, data communication security.

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1183 Analytical Approach of the In-Pipe Robot on Branched Pipe Navigation and Its Solution

Authors: Yoon Koo Kang, Jung wan Park, Hyun Seok Yang

Abstract:

This paper determines most common model of in-pipe robots to derive its degree of freedom in order to compare with the necessary degree of freedom required for a system to move inside pipelines freely in order to derive analytical reason for losing control of in-pipe robots at branched pipe. DOF of most common mechanism in in-pipe robots can be calculated by considering the robot as a parallel manipulator. A new design based on previously researched in-pipe robot PAROYS has been suggested, and its possibility to overcome branched section has been simulated.

Keywords: Branched pipe, Degree of freedom, In-pipe robot, Parallel manipulator.

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1182 Parallel Pipelined Conjugate Gradient Algorithm on Heterogeneous Platforms

Authors: Sergey Kopysov, Nikita Nedozhogin, Leonid Tonkov

Abstract:

The article presents a parallel iterative solver for large sparse linear systems which can be used on a heterogeneous platform. Traditionally, the problem of solving linear systems do not scale well on cluster containing multiple Central Processing Units (multi-CPUs cluster) or cluster containing multiple Graphics Processing Units (multi-GPUs cluster). For example, most of the attempts to implement the classical conjugate gradient method were at best counted in the same amount of time as the problem was enlarged. The paper proposes the pipelined variant of the conjugate gradient method (PCG), a formulation that is potentially better suited for hybrid CPU/GPU computing since it requires only one synchronization point per one iteration, instead of two for standard CG (Conjugate Gradient). The standard and pipelined CG methods need the vector entries generated by current GPU and other GPUs for matrix-vector product. So the communication between GPUs becomes a major performance bottleneck on miltiGPU cluster. The article presents an approach to minimize the communications between parallel parts of algorithms. Additionally, computation and communication can be overlapped to reduce the impact of data exchange. Using pipelined version of the CG method with one synchronization point, the possibility of asynchronous calculations and communications, load balancing between the CPU and GPU for solving the large linear systems allows for scalability. The algorithm is implemented with the combined use of technologies: MPI, OpenMP and CUDA. We show that almost optimum speed up on 8-CPU/2GPU may be reached (relatively to a one GPU execution). The parallelized solver achieves a speedup of up to 5.49 times on 16 NVIDIA Tesla GPUs, as compared to one GPU.

Keywords: Conjugate Gradient, GPU, parallel programming, pipelined algorithm.

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1181 Service-Based Application Adaptation Strategies: A Survey

Authors: Sahba Paktinat, Afshin Salajeghe, Mir Ali Seyyedi, Yousef Rastegari

Abstract:

Service Oriented Architecture (SOA) allows modeling of dynamic interaction between incongruous providers, which enables governing the development of complex applications. However, implementation of SOA comes with some challenges, including its adaptability and robustness. Dynamism is inherent to the nature of service based applications and of their running environment. These factors lead to necessity for dynamic adaptation. In this paper we try to describe basics and main structure of SOA adaptation process with a conceptual view to this issue. In this survey we will review the relevant adaptation approaches. This paper allows studying how different approaches deal with service oriented architecture adaptation life-cycle and provides basic guidelines for their analysis, evaluation and comparison.

Keywords: Context-aware, Dynamic Adaptation, Quality of Services, Service Oriented Architecture, Service Based Application.

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1180 Classification Based on Deep Neural Cellular Automata Model

Authors: Yasser F. Hassan

Abstract:

Deep learning structure is a branch of machine learning science and greet achievement in research and applications. Cellular neural networks are regarded as array of nonlinear analog processors called cells connected in a way allowing parallel computations. The paper discusses how to use deep learning structure for representing neural cellular automata model. The proposed learning technique in cellular automata model will be examined from structure of deep learning. A deep automata neural cellular system modifies each neuron based on the behavior of the individual and its decision as a result of multi-level deep structure learning. The paper will present the architecture of the model and the results of simulation of approach are given. Results from the implementation enrich deep neural cellular automata system and shed a light on concept formulation of the model and the learning in it.

Keywords: Cellular automata, neural cellular automata, deep learning, classification.

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1179 Implementation Issues of Industrial PID Controller and Their Remedies

Authors: C. B. Vishwakarma

Abstract:

We elaborated the parallel and series Proportional, Integral and Derivative (PID) controllers, which are being used in industries. Various issues, which are very often faced by control engineers while designing the PID controllers for industrial systems are described. The effect of measurement noise on the actuator due to derivative term of a PID controller has been explained in detail. Similarly, proportional kick, derivative kick, saturation tendency of the actuator and reverse phenomena of an industrial process have been summarized. Moreover, we meticulously explained the remedies of the all issues of the parallel industrial PID controller.

Keywords: Band-width limited derivative control, derivative kick, proportional kick, reverse acting controller, series PID controller.

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1178 Programming Aid Tool for Detecting Common Mistakes of Novice Programmers in OpenMP Code

Authors: Jae Young Park, Seung Wook Lee, Jong Tae Kim

Abstract:

OpenMP is an API for parallel programming model of shared memory multiprocessors. Novice OpenMP programmers often produce the code that compiler cannot find human errors. It was investigated how compiler coped with the common mistakes that can occur in OpenMP code. The latest version(4.4.3) of GCC is used for this research. It was found that GCC compiled the codes without any errors or warnings. In this paper the programming aid tool is presented for OpenMP programs. It can check 12 common mistakes that novice programmer can commit during the programming of OpenMP. It was demonstrated that the programming aid tool can detect the various common mistakes that GCC failed to detect.

Keywords: Parallel programming, OpenMP, programming aid.

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1177 A Fully Parallel Reverse Converter

Authors: Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi

Abstract:

The residue number system (RNS) is popular in high performance computation applications because of its carry-free nature. The challenges of RNS systems design lie in the moduli set selection and in the reverse conversion from residue representation to weighted representation. In this paper, we proposed a fully parallel reverse conversion algorithm for the moduli set {rn - 2, rn - 1, rn}, based on simple mathematical relationships. Also an efficient hardware realization of this algorithm is presented. Our proposed converter is very faster and results to hardware savings, compared to the other reverse converters.

Keywords: Reverse converter, residue to weighted converter, residue number system, multiple-valued logic, computer arithmetic.

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1176 School Architecture of the Future Supported by Evidence-Based Design and Design Patterns

Authors: Pedro Padilha Gonçalves, Doris C. C. K. Kowaltowski, Benjamin Cleveland

Abstract:

Trends in education affect schooling, needing incorporation into design concepts to support desired learning processes with appropriate and stimulating environments. A design process for school architecture demands research, debates, reflections, and efficient decision-making methods. This paper presents research on evidence-based design, related to middle schools, based on a systematic literature review and the elaboration of a set of architectural design patterns, through a graphic translation of new concepts for classroom configurations, to support programming debates and the synthesis phase of design. The investigation resulted in nine patterns that configure the concepts of boundaries, flexibility, levels of openness, mindsets, neighborhoods, movement and interaction, territories, opportunities for learning, and sightlines for classrooms. The research is part of a continuous investigation of design methods, on contemporary school architecture to produce an architectural pattern matrix based on scientific information translated into an insightful graphic design language.

Keywords: School architecture, design process, design patterns, evidence-based design.

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1175 Effective Sonar Target Classification via Parallel Structure of Minimal Resource Allocation Network

Authors: W.S. Lim, M.V.C. Rao

Abstract:

In this paper, the processing of sonar signals has been carried out using Minimal Resource Allocation Network (MRAN) and a Probabilistic Neural Network (PNN) in differentiation of commonly encountered features in indoor environments. The stability-plasticity behaviors of both networks have been investigated. The experimental result shows that MRAN possesses lower network complexity but experiences higher plasticity than PNN. An enhanced version called parallel MRAN (pMRAN) is proposed to solve this problem and is proven to be stable in prediction and also outperformed the original MRAN.

Keywords: Ultrasonic sensing, target classification, minimalresource allocation network (MRAN), probabilistic neural network(PNN), stability-plasticity dilemma.

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1174 Impact of Fair Share and its Configurations on Parallel Job Scheduling Algorithms

Authors: Sangsuree Vasupongayya

Abstract:

To provide a better understanding of fair share policies supported by current production schedulers and their impact on scheduling performance, A relative fair share policy supported in four well-known production job schedulers is evaluated in this study. The experimental results show that fair share indeed reduces heavy-demand users from dominating the system resources. However, the detailed per-user performance analysis show that some types of users may suffer unfairness under fair share, possibly due to priority mechanisms used by the current production schedulers. These users typically are not heavy-demands users but they have mixture of jobs that do not spread out.

Keywords: Fair share, Parallel job scheduler, Backfill, Measures

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1173 Affine Combination of Splitting Type Integrators, Implemented with Parallel Computing Methods

Authors: Adrian Alvarez, Diego Rial

Abstract:

In this work we present a family of new convergent type methods splitting high order no negative steps feature that allows your application to irreversible problems. Performing affine combinations consist of results obtained with Trotter Lie integrators of different steps. Some examples where applied symplectic compared with methods, in particular a pair of differential equations semilinear. The number of basic integrations required is comparable with integrators symplectic, but this technique allows the ability to do the math in parallel thus reducing the times of which exemplify exhibiting some implementations with simple schemes for its modularity and scalability process.

Keywords: Lie Trotter integrators, Irreversible Problems, Splitting Methods without negative steps, MPI, HPC.

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1172 A Self Supervised Bi-directional Neural Network (BDSONN) Architecture for Object Extraction Guided by Beta Activation Function and Adaptive Fuzzy Context Sensitive Thresholding

Authors: Siddhartha Bhattacharyya, Paramartha Dutta, Ujjwal Maulik, Prashanta Kumar Nandi

Abstract:

A multilayer self organizing neural neural network (MLSONN) architecture for binary object extraction, guided by a beta activation function and characterized by backpropagation of errors estimated from the linear indices of fuzziness of the network output states, is discussed. Since the MLSONN architecture is designed to operate in a single point fixed/uniform thresholding scenario, it does not take into cognizance the heterogeneity of image information in the extraction process. The performance of the MLSONN architecture with representative values of the threshold parameters of the beta activation function employed is also studied. A three layer bidirectional self organizing neural network (BDSONN) architecture comprising fully connected neurons, for the extraction of objects from a noisy background and capable of incorporating the underlying image context heterogeneity through variable and adaptive thresholding, is proposed in this article. The input layer of the network architecture represents the fuzzy membership information of the image scene to be extracted. The second layer (the intermediate layer) and the final layer (the output layer) of the network architecture deal with the self supervised object extraction task by bi-directional propagation of the network states. Each layer except the output layer is connected to the next layer following a neighborhood based topology. The output layer neurons are in turn, connected to the intermediate layer following similar topology, thus forming a counter-propagating architecture with the intermediate layer. The novelty of the proposed architecture is that the assignment/updating of the inter-layer connection weights are done using the relative fuzzy membership values at the constituent neurons in the different network layers. Another interesting feature of the network lies in the fact that the processing capabilities of the intermediate and the output layer neurons are guided by a beta activation function, which uses image context sensitive adaptive thresholding arising out of the fuzzy cardinality estimates of the different network neighborhood fuzzy subsets, rather than resorting to fixed and single point thresholding. An application of the proposed architecture for object extraction is demonstrated using a synthetic and a real life image. The extraction efficiency of the proposed network architecture is evaluated by a proposed system transfer index characteristic of the network.

Keywords: Beta activation function, fuzzy cardinality, multilayer self organizing neural network, object extraction,

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1171 FPGA Based Longitudinal and Lateral Controller Implementation for a Small UAV

Authors: Hafiz ul Azad, Dragan V.Lazic, Waqar Shahid

Abstract:

This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Keywords: Field Programmable gate array (FPGA), Hardwaredescriptive Language (HDL), PID, Pipelining, Retiming, XilinxSystem Generator.

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1170 Vortex Shedding at the End of Parallel-plate Thermoacoustic Stack in the Oscillatory Flow Conditions

Authors: Lei Shi, Zhibin Yu, Artur J. Jaworski, Abdulrahman S. Abduljalil

Abstract:

This paper investigates vortex shedding processes occurring at the end of a stack of parallel plates, due to an oscillating flow induced by an acoustic standing wave within an acoustic resonator. Here, Particle Image Velocimetry (PIV) is used to quantify the vortex shedding processes within an acoustic cycle phase-by-phase, in particular during the “ejection" of the fluid out of the stack. Standard hot-wire anemometry measurement is also applied to detect the velocity fluctuations near the end of the stack. Combination of these two measurement techniques allowed a detailed analysis of the vortex shedding phenomena. The results obtained show that, as the Reynolds number varies (by varying the plate thickness and drive ratio), different flow patterns of vortex shedding are observed by the PIV measurement. On the other hand, the time-dependent hot-wire measurements allow obtaining detailed frequency spectra of the velocity signal, used for calculating characteristic Strouhal numbers. The impact of the plate thickness and the Reynolds number on the vortex shedding pattern has been discussed. Furthermore, a detailed map of the relationship between the Strouhal number and Reynolds number has been obtained and discussed.

Keywords: Oscillatory flow, Parallel-plate thermoacoustic stack, Strouhal numbers, Vortex shedding.

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1169 Performance Analysis of Selective Adaptive Multiple Access Interference Cancellation for Multicarrier DS-CDMA Systems

Authors: Maged Ahmed, Ahmed El-Mahdy

Abstract:

In this paper, Selective Adaptive Parallel Interference Cancellation (SA-PIC) technique is presented for Multicarrier Direct Sequence Code Division Multiple Access (MC DS-CDMA) scheme. The motivation of using SA-PIC is that it gives high performance and at the same time, reduces the computational complexity required to perform interference cancellation. An upper bound expression of the bit error rate (BER) for the SA-PIC under Rayleigh fading channel condition is derived. Moreover, the implementation complexities for SA-PIC and Adaptive Parallel Interference Cancellation (APIC) are discussed and compared. The performance of SA-PIC is investigated analytically and validated via computer simulations.

Keywords: Adaptive interference cancellation, communicationsystems, multicarrier signal processing, spread spectrum

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1168 Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network

Authors: MooSeop Kim, Juhan Kim, Yongje Choi

Abstract:

Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues such as authentication and data integrity are major requirements to construct sensor network systems. Advanced Encryption Standard (AES) is considered as one of candidate algorithms for data encryption in wireless sensor networks. In this paper, we will present the hardware architecture to implement low power AES crypto module. Our low power AES crypto module has optimized architecture of data encryption unit and key schedule unit which could be applicable to wireless sensor networks. We also details low power design methods used to design our low power AES crypto module.

Keywords: Algorithm, Low Power Crypto Circuit, AES, Security.

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1167 A Standalone WebGL Supporting Architecture

Authors: Nakhoon Baek

Abstract:

WebGL is typically used with web browsers. In this paper, we represent a standalone WebGL execution environment, where the original WebGL source codes show the same result to those of WebGL-capable web browsers. This standalone environment enables us to run WebGL programs without web browsers and/or internet connections. Our implementation shows the same rendering results with typical web browser outputs. This standalone environment is suitable for low-tier devices and/or debugging purposes.

Keywords: WebGL, OpenGL ES, stand-alone, architecture

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1166 Solving 94-bit ECDLP with 70 Computers in Parallel

Authors: Shunsuke Miyoshi, Yasuyuki Nogami, Takuya Kusaka, Nariyoshi Yamai

Abstract:

Elliptic curve discrete logarithm problem(ECDLP) is one of problems on which the security of pairing-based cryptography is based. This paper considers Pollard’s rho method to evaluate the security of ECDLP on Barreto-Naehrig(BN) curve that is an efficient pairing-friendly curve. Some techniques are proposed to make the rho method efficient. Especially, the group structure on BN curve, distinguished point method, and Montgomery trick are well-known techniques. This paper applies these techniques and shows its optimization. According to the experimental results for which a large-scale parallel system with MySQL is applied, 94-bit ECDLP was solved about 28 hours by parallelizing 71 computers.

Keywords: Pollard’s rho method, BN curve, Montgomery multiplication.

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1165 Performances Comparison of Neural Architectures for On-Line Speed Estimation in Sensorless IM Drives

Authors: K.Sedhuraman, S.Himavathi, A.Muthuramalingam

Abstract:

The performance of sensor-less controlled induction motor drive depends on the accuracy of the estimated speed. Conventional estimation techniques being mathematically complex require more execution time resulting in poor dynamic response. The nonlinear mapping capability and powerful learning algorithms of neural network provides a promising alternative for on-line speed estimation. The on-line speed estimator requires the NN model to be accurate, simpler in design, structurally compact and computationally less complex to ensure faster execution and effective control in real time implementation. This in turn to a large extent depends on the type of Neural Architecture. This paper investigates three types of neural architectures for on-line speed estimation and their performance is compared in terms of accuracy, structural compactness, computational complexity and execution time. The suitable neural architecture for on-line speed estimation is identified and the promising results obtained are presented.

Keywords: Sensorless IM drives, rotor speed estimators, artificial neural network, feed- forward architecture, single neuron cascaded architecture.

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1164 An Ultra-Low Output Impedance Power Amplifier for Tx Array in 7-Tesla Magnetic Resonance Imaging

Authors: Ashraf Abuelhaija, Klaus Solbach

Abstract:

In Ultra high-field MRI scanners (3T and higher), parallel RF transmission techniques using multiple RF chains with multiple transmit elements are a promising approach to overcome the high-field MRI challenges in terms of inhomogeneity in the RF magnetic field and SAR. However, mutual coupling between the transmit array elements disturbs the desirable independent control of the RF waveforms for each element. This contribution demonstrates a 18 dB improvement of decoupling (isolation) performance due to the very low output impedance of our 1 kW power amplifier.

Keywords: EM coupling, Inter-element isolation, Magnetic resonance imaging (MRI), Parallel Transmit.

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1163 Software Architecture Recovery

Authors: Ghulam Rasool, Nadim Asif

Abstract:

The advent of modern technology shadows its impetus repercussions on successful Legacy systems making them obsolete with time. These systems have evolved the large organizations in major problems in terms of new business requirements, response time, financial depreciation and maintenance. Major difficulty is due to constant system evolution and incomplete, inconsistent and obsolete documents which a legacy system tends to have. The myriad dimensions of these systems can only be explored by incorporating reverse engineering, in this context, is the best method to extract useful artifacts and by exploring these artifacts for reengineering existing legacy systems to meet new requirements of organizations. A case study is conducted on six different type of software systems having source code in different programming languages using the architectural recovery framework.

Keywords: Reverse Engineering, Architecture recovery, Architecture artifacts, Reengineering.

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1162 Analyzing the Impact of Indian Architecture on the Architecture of Cambodia, Thailand and Indonesia

Authors: Sriranjani Srinivasan

Abstract:

To appreciate Indian art and architecture by studying it in India alone will only lead to partial understanding of the whole story and the variety of the statement has been amply proved by subsequent decades of patient research. The results of the work of the Archaeological Survey of India forms only one half of the picture, the other half emerges with the studies of the archaeology and art of the Far East that progressed almost simultaneously under the Archaeological Survey of the Dutch East Indies, the École française d'Extrême-Orient (EFEO), or French School of Asian Studies, and allied institutions. The conclusions arrived at have only rendered the assertion that India produced her ultimate master pieces only through foreign influences and in foreign lands (the South-Eastern peninsular and archipelagic regions) almost axiomatic. Angkor in Cambodia and Borobudur in Java, undoubtedly the two greatest architectural marvels of Indian genius, for in content and spirit these (and other monuments of varying magnitudes), are purely Indian, would well illustrate the statement mentioned earlier. Stimulated research followed the discoveries and among the many studies and publications of such pioneers like Coedes, Parmentier, Coomaraswamy and many others in Dutch, French and English made growing contributions to the subject. This paper will discuss in detail the impact of India on the architecture of South East Asia by detailed comparison of architectural styles, elements, and construction materials of a few specific architectural master pieces, in both India and South East Asian countries. It will also analyze the reasoning behind the influence of India on South East Asian countries in spite of them being exposed to the equally culturally rich and civilized kingdoms of China. The intention of this paper is to understand that, conquest by war is not always the only reason for architectural influences and impacts.

Keywords: Architectural influence, Buddhist architecture, Indian architecture, Southeast Asian architecture.

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1161 An Improvement of PDLZW implementation with a Modified WSC Updating Technique on FPGA

Authors: Perapong Vichitkraivin, Orachat Chitsobhuk

Abstract:

In this paper, an improvement of PDLZW implementation with a new dictionary updating technique is proposed. A unique dictionary is partitioned into hierarchical variable word-width dictionaries. This allows us to search through dictionaries in parallel. Moreover, the barrel shifter is adopted for loading a new input string into the shift register in order to achieve a faster speed. However, the original PDLZW uses a simple FIFO update strategy, which is not efficient. Therefore, a new window based updating technique is implemented to better classify the difference in how often each particular address in the window is referred. The freezing policy is applied to the address most often referred, which would not be updated until all the other addresses in the window have the same priority. This guarantees that the more often referred addresses would not be updated until their time comes. This updating policy leads to an improvement on the compression efficiency of the proposed algorithm while still keep the architecture low complexity and easy to implement.

Keywords: lossless data compression, LZW algorithm, PDLZW algorithm, WSC and dictionary update.

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1160 Enhanced Parallel-Connected Comb Filter Method for Multiple Pitch Estimation

Authors: Taro Matsuno, Yuta Otani, Ryo Tanaka, Kaori Ikezaki, Hitoshi Yamamoto, Masaru Fujieda, Yoshihisa Ishida

Abstract:

This paper presents an improvement method of the multiple pitch estimation algorithm using comb filters. Conventionally the pitch was estimated by using parallel -connected comb filters method (PCF). However, PCF has problems which often fail in the pitch estimation when there is the fundamental frequency of higher tone near harmonics of lower tone. Therefore the estimation is assigned to a wrong note when shared frequencies happen. This issue often occurs in estimating octave 3 or more. Proposed method, for solving the problem, estimates the pitch with every harmonic instead of every octave. As a result, our method reaches the accuracy of more than 80%.

Keywords: music transcription, pitch estimation, comb filter, fractional delay

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