Search results for: High-speed VCSELs

Authors: Ahmad Al-Omari, Osama Khreis, Ahmad M. K. Dagamseh, Abdullah Ababneh, Kevin Lear

Abstract:

High-speed infrared vertical-cavity surface-emitting laser diodes (VCSELs) with Cu-plated heat sinks were fabricated and tested. VCSELs with 10 mm aperture diameter and 4 mm of electroplated copper demonstrated a -3dB modulation bandwidth (f_-3dB) of 14 GHz and a resonance frequency (f_R) of 9.5 GHz at a bias current density (J_bias) of only 4.3 kA/cm², which corresponds to an improved f_-3dB²/J_bias ratio of 44 GHz²/kA/cm². At higher and lower bias current densities, the f_-3dB²/ J_bias ratio decreased to about 30 GHz²/kA/cm² and 18 GHz²/kA/cm², respectively. Examination of the analogue modulation response demonstrated that the presented VCSELs displayed a steady f_-3dB/ f_R ratio of 1.41±10% over the whole range of the bias current (1.3I_th to 6.2I_th). The devices also demonstrated a maximum modulation bandwidth (f_{-3dB max}) of more than 16 GHz at a bias current less than the industrial bias current standard for reliability by 25%.

Keywords: Current density, High-speed VCSELs, Modulation bandwidth, Small-Signal Characteristics, Thermal impedance, Vertical-cavity surface-emitting lasers.

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Authors: Mountassar Maamoun, Mehdi Neggazi, Abdelhamid Meraghni, Daoud Berkani

Abstract:

This paper presents a VLSI design approach of a highspeed and real-time 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. Furthermore, an advanced twodimensional (2-D) discrete wavelet transform (DWT) implementation, with an efficient memory area, is designed to produce one output in every clock cycle. As a result, a very highspeed is attained. The system is verified, using JPEG2000 coefficients filters, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory. The resulting computing rate is up to 270 M samples/s and the (9,7) 2-D wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out memory) with 256×256 image size. In this way, the developed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.

Keywords: Discrete Wavelet Transform (DWT), Fast Convolution, FPGA, VLSI.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: L. Tani, N. El Ouzzani

Abstract:

Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Keywords: Multiconductor transmission line, Crosstalk, Finite difference time domain (FDTD), printed-circuit board (PCB), Rise time, Statistical analysis.

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Authors: Somayeh Timarchi, Keivan Navi

Abstract:

Efficient modulo 2n+1 adders are important for several applications including residue number system, digital signal processors and cryptography algorithms. In this paper we present a novel modulo 2n+1 addition algorithm for a recently represented number system. The proposed approach is introduced for the reduction of the power dissipated. In a conventional modulo 2n+1 adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit circuits, the diminished-1 and carry save diminished-1 number systems can be effectively used in applications. In the paper, we also derive two new architectures for designing modulo 2n+1 adder, based on n-bit ripple-carry adder. The first architecture is a faster design whereas the second one uses less hardware. In the proposed method, the special treatment required for zero operands in Diminished-1 number system is removed. In the fastest modulo 2n+1 adders in normal binary system, there are 3-operand adders. This problem is also resolved in this paper. The proposed architectures are compared with some efficient adders based on ripple-carry adder and highspeed adder. It is shown that the hardware overhead and power consumption will be reduced. As well as power reduction, in some cases, power-delay product will be also reduced.

Keywords: Modulo 2n+1 arithmetic, residue number system, low power, ripple-carry adders.

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Authors: S. Nazhan, Hassan K. Al-Musawi, Khalid A. Humood

Abstract:

This paper reports on an experimental investigation into the influence of current modulation on the properties of a vertical-cavity surface-emitting laser (VCSEL) with a direct square wave modulation. The optical output power response, as a function of the pumping current, modulation frequency, and amplitude, is measured for an 850 nm VCSEL. We demonstrate that modulation frequency and amplitude play important roles in reducing the VCSEL’s power consumption for optical generation. Indeed, even when the biasing current is below the static threshold, the VCSEL emits optical power under the square wave modulation. The power consumed by the device to generate light is significantly reduced to > 50%, which is below the threshold current, in response to both the modulation frequency and amplitude. An operating VCSEL device at low power is very desirable for less thermal effects, which are essential for a high-speed modulation bandwidth.

Keywords: VCSELs, optical power generation, power consumption, square wave modulation.

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