Search results for: Costas Galiotis

Authors: Konstantinos G. Dassios, Guillaume Bonnefont, Gilbert Fantozzi, Theodore E. Matikas, Costas Galiotis

Abstract:

We report herein the development and preliminary mechanical characterization of fully-dense multi-wall carbon nanotube (MWCNT)-reinforced ceramics and glasses based on a completely new methodology termed High Shear Compaction (HSC). The tubes are introduced and bound to the matrix grains by aid of polymeric binders to form flexible green bodies which are sintered and densified by spark plasma sintering to unprecedentedly high densities of 100% of the pure-matrix value. The strategy was validated across a PyrexTM glass / MWCNT composite while no identifiable factors limit application to other types of matrices. Nondestructive evaluation, based on ultrasonics, of the dynamic mechanical properties of the materials including elastic, shear and bulk modulus as well as Poisson’s ratio showed optimum property improvement at 0.5 %wt tube loading while evidence of nanoscalespecific energy dissipative characteristics acting complementary to nanotube bridging and pull-out indicate a high potential in a wide range of reinforcing and multifunctional applications. 

Keywords: Carbon nanotubes, ceramic matrix composites, toughening, ultrasonics.

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Authors: Costas S. Iliopoulos, Spiros Michalakopoulos

Abstract:

A new, combinatorial model for analyzing and inter- preting an electrocardiogram (ECG) is presented. An application of the model is QRS peak detection. This is demonstrated with an online algorithm, which is shown to be space as well as time efficient. Experimental results on the MIT-BIH Arrhythmia database show that this novel approach is promising. Further uses for this approach are discussed, such as taking advantage of its small memory requirements and interpreting large amounts of pre-recorded ECG data.

Keywords: Combinatorics, ECG analysis, MIT-BIH Arrhythmia Database, QRS Detection, String Algorithms

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Authors: Kapil Dev Sharma, Kirat Pal, Costas Psychalinos

Abstract:

A new first order all-pass filter topology realized using current controlled current conveyors (CCCIIs) is introduced in this paper. Offered benefits are the high-impedance of the input node, the absence of external resistors because of the usage of CCCIIs with positive and negative intrinsic resistances, the presence of only grounded capacitors, and the capability of electronic adjustment of the phase shift through a single bias current. The correct operation of the introduced topology is conformed through simulation results, while its behavior is evaluated through comparison results.

Keywords: Active filters, All-pass filters, Analog signal processing, Current conveyors.

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Authors: Grigorios D. Dimitroulakos, N. D. Zervas, N. Sklavos, Costas E. Goutis

Abstract:

In this paper, the implementation of low power, high throughput convolutional filters for the one dimensional Discrete Wavelet Transform and its inverse are presented. The analysis filters have already been used for the implementation of a high performance DWT encoder [15] with minimum memory requirements for the JPEG 2000 standard. This paper presents the design techniques and the implementation of the convolutional filters included in the JPEG2000 standard for the forward and inverse DWT for achieving low-power operation, high performance and reduced memory accesses. Moreover, they have the ability of performing progressive computations so as to minimize the buffering between the decomposition and reconstruction phases. The experimental results illustrate the filters- low power high throughput characteristics as well as their memory efficient operation.

Keywords: Discrete Wavelet Transform; JPEG2000 standard; VLSI design; Low Power-Throughput-optimized filters

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Authors: Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis

Abstract:

Speedups from mapping four real-life DSP applications on an embedded system-on-chip that couples coarsegrained reconfigurable logic with an instruction-set processor are presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A design flow for improving application-s performance is proposed. Critical software parts, called kernels, are accelerated on the Coarse-Grained Reconfigurable Array. The kernels are detected by profiling the source code. For mapping the detected kernels on the reconfigurable logic a prioritybased mapping algorithm has been developed. Two 4x4 array architectures, which differ in their interconnection structure among the Processing Elements, are considered. The experiments for eight different instances of a generic system show that important overall application speedups have been reported for the four applications. The performance improvements range from 1.86 to 3.67, with an average value of 2.53, compared with an all-software execution. These speedups are quite close to the maximum theoretical speedups imposed by Amdahl-s law.

Keywords: Reconfigurable computing, Coarse-grained reconfigurable array, Embedded systems, DSP, Performance

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