Search results for: inverses

Authors: Faisal Yousafzai, Murad-ul-Islam Khan, Kar Ping Shum

Abstract:

We introduce the concept of partially inverse AG**-groupoids which is almost parallel to the concepts of E-inversive semigroups and E-inversive E-semigroups. Some characterization problems are provided on partially inverse AG**-groupoids. We give necessary and sufficient conditions for a partially inverse AG**-subgroupoid E to be a rectangular band. Furthermore, we determine the unitary congruence η on a partially inverse AG**-groupoid and show that each partially inverse AG**-groupoid possesses an idempotent separating congruence μ. We also study anti-separative commutative image of a locally associative AG**-groupoid. Finally, we give the concept of completely N-inverse AG**-groupoid and characterize a maximum idempotent separating congruence.

Keywords: AG**-groupoids, congruences, inverses, rectangular band

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Authors: Hamdy M. Youssef, Mowffaq Oreijah, Hunaydi S. Alsharif

Abstract:

In this paper, a three-dimensional model of the generalized thermoelasticity with one relaxation time and variable thermal conductivity has been constructed. The resulting non-dimensional governing equations together with the Laplace and double Fourier transforms techniques have been applied to a three-dimensional half-space subjected to thermal loading with rectangular pulse and traction free in the directions of the principle co-ordinates. The inverses of double Fourier transforms, and Laplace transforms have been obtained numerically. Numerical results for the temperature increment, the invariant stress, the invariant strain, and the displacement are represented graphically. The variability of the thermal conductivity has significant effects on the thermal and the mechanical waves.

Keywords: thermoelasticity, thermal conductivity, Laplace transforms, Fourier transforms

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Authors: Malika Yaici, Kamel Hariche

Abstract:

In control engineering, systems described by matrix fractions are studied through properties of block roots, also called solvents. These solvents are usually dealt with in a block Vandermonde matrix form. Inverses and determinants of Vandermonde matrices and block Vandermonde matrices are used in solving problems of numerical analysis in many domains but require costly computations. Even though Vandermonde matrices are well known and method to compute inverse and determinants are many and, generally, based on interpolation techniques, methods to compute the inverse and determinant of a block Vandermonde matrix have not been well studied. In this paper, some properties of these matrices and iterative algorithms to compute the determinant and the inverse of a block Vandermonde matrix are given. These methods are deducted from the partitioned matrix inversion and determinant computing methods. Due to their great size, parallelization may be a solution to reduce the computations cost, so a parallelization of these algorithms is proposed and validated by a comparison using algorithmic complexity.

Keywords: block vandermonde matrix, solvents, matrix polynomial, matrix inverse, matrix determinant, parallelization

Procedia PDF Downloads 240

Authors: Hamdi Belgacem, Fradi Aymen

Abstract:

In this paper we present a low power, low cost differential logic unit (LU). The proposed LU receives dual-rail inputs and generates dual-rail outputs. The proposed circuit can be used in Arithmetic and Logic Units (ALU) of processor. It can be also dedicated for self-checking applications based on dual duplication code. Four logic functions as well as their inverses are implemented within a single Logic Unit. The hardware overhead for the implementation of the proposed LU is lower than the hardware overhead required for standard LU implemented with standard CMOS logic style. This new implementation is attractive as fewer transistors are required to implement important logic functions. The proposed differential logic unit can perform 8 Boolean logical operations by using only 16 transistors. Spice simulations using a 32 nm technology was utilized to evaluate the performance of the proposed circuit and to prove its acceptable electrical behaviour.

Keywords: differential logic unit, double pass transistor logic, low power CMOS design, low cost CMOS design

Procedia PDF Downloads 452