Search results for: Si Mon Kueh

Authors: Shi Qi Koo, Ahmad Beng Hong Kueh

Abstract:

In the present work, the finite element formulation for the investigation of the effects of a localized interfacial degeneration on the dynamic behavior of the [90°/0°] laminated composite plate employing the state-space technique is performed. The stiffness of the laminate is determined by assembling the stiffnesses of subelements. This includes an introduction of an interface layer adopting the virtually zero-thickness formulation to model the interfacial degeneration. Also, the kinematically consistent mass matrix and proportional damping have been formulated to complete the free vibration governing expression. To simulate the interfacial degeneration of the laminate, the degenerated areas are defined from the center propagating outwards in a localized manner. It is found that the natural frequency, damped frequency and damping ratio of the plate decreases as the degenerated area of the interface increases. On the contrary, the loss factor increases correspondingly.

Keywords: Dynamic finite element, localized interface degeneration, proportional damping, state-space modeling.

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Authors: Si Mon Kueh, Tom J. Kazmierski

Abstract:

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

Keywords: Artificial Neural Networks, bit-serial neural processor, FPGA, Neural Processing Element.

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