Search results for: Paramasivam Rajeswari
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 7

Search results for: Paramasivam Rajeswari

7 Ameliorative Effect of Calocybe indica, a Tropical Indian Edible Mushroom on Hyperglycemia Induced Oxidative Stress

Authors: Shanmugasundaram Krishnakumari, Paramasivam Rajeswari, Subramanian Kathiravan

Abstract:

Mushrooms are a group of fleshy macroscopic fungi. They have been valued throughout the world as both edible and medicine. They are highly nutritious with good amount of quality proteins, vitamins and minerals. An edible mushroom, Calocybe indica was selected to validate its nutritional and medicinal properties. Since tissue damage in hyperglycemia has been related to oxidative stress, we evaluated the enzymatic and non-enzymatic antioxidant status in the serum, liver and kidney since they are the target organs in diabetic complications. From the results, increased oxidative stress and decreased antioxidants might be related to the causation of diabetes mellitus. The treatment in the diabetic rats with the Calocybe indica showed an increase in the antioxidant system and decrease in the production of free radicals. The mushrooms which contain antioxidant phytochemicals has potential free radical scavenging capacity and hence can induce the antioxidant system in the body significantly reduces the generated free radicals thereby maintaining the normal levels of the antioxidants

Keywords: Antioxidants, Calocybe indica, diabetes mellitus, edible mushroom, oxidative stress.

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6 SATA: A Web Based Scheduling Support System

Authors: Rajeswari Raju, Saiful Nizam Warris, Hazlifah Mohd Rusli

Abstract:

Developing a university course schedule is difficult. This is due to the limitations in the resources available. The process is made even harder with different faculties or departments having different ways of stating their schedule requirements. The person in charge of taking the schedule requirements and turning them into a proper course schedule is not only burden with the task of allocating the appropriate classes and time to lecturers and students, they also need to understand the schedule requirements. Therefore a scheduling support system named SATA is developed to assist ICRESS in the course scheduling process. SATA has been put to use for several semesters and the results have been encouraging. It won a bronze medal in the 2008 Invention, Innovation and Design competition (IID-08) and has been submitted to be patented in October 2008

Keywords: Course Scheduling, Scheduling Tool Aid.

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5 Test Data Compression Using a Hybrid of Bitmask Dictionary and 2n Pattern Runlength Coding Methods

Authors: C. Kalamani, K. Paramasivam

Abstract:

In VLSI, testing plays an important role. Major problem in testing are test data volume and test power. The important solution to reduce test data volume and test time is test data compression. The Proposed technique combines the bit maskdictionary and 2n pattern run length-coding method and provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. This method has been implemented using Mat lab and HDL Language to reduce test data volume and memory requirements. This method is applied on various benchmark test sets and compared the results with other existing methods. The proposed technique can achieve a compression ratio up to 86%.

Keywords: Bit Mask dictionary, 2n pattern run length code, system-on-chip, SOC, test data compression.

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4 Diagnosis of Inter Turn Fault in the Stator of Synchronous Generator Using Wavelet Based ANFIS

Authors: R. Rajeswari, N. Kamaraj

Abstract:

In this paper, Wavelet based ANFIS for finding inter turn fault of generator is proposed. The detector uniquely responds to the winding inter turn fault with remarkably high sensitivity. Discrimination of different percentage of winding affected by inter turn fault is provided via ANFIS having an Eight dimensional input vector. This input vector is obtained from features extracted from DWT of inter turn faulty current leaving the generator phase winding. Training data for ANFIS are generated via a simulation of generator with inter turn fault using MATLAB. The proposed algorithm using ANFIS is giving satisfied performance than ANN with selected statistical data of decomposed levels of faulty current.

Keywords: Winding InterTurn fault, ANN, ANFIS, and DWT.

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3 Improved Rare Species Identification Using Focal Loss Based Deep Learning Models

Authors: Chad Goldsworthy, B. Rajeswari Matam

Abstract:

The use of deep learning for species identification in camera trap images has revolutionised our ability to study, conserve and monitor species in a highly efficient and unobtrusive manner, with state-of-the-art models achieving accuracies surpassing the accuracy of manual human classification. The high imbalance of camera trap datasets, however, results in poor accuracies for minority (rare or endangered) species due to their relative insignificance to the overall model accuracy. This paper investigates the use of Focal Loss, in comparison to the traditional Cross Entropy Loss function, to improve the identification of minority species in the “255 Bird Species” dataset from Kaggle. The results show that, although Focal Loss slightly decreased the accuracy of the majority species, it was able to increase the F1-score by 0.06 and improve the identification of the bottom two, five and ten (minority) species by 37.5%, 15.7% and 10.8%, respectively, as well as resulting in an improved overall accuracy of 2.96%.

Keywords: Convolutional neural networks, data imbalance, deep learning, focal loss, species classification, wildlife conservation.

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2 A Modified Run Length Coding Technique for Test Data Compression Based on Multi-Level Selective Huffman Coding

Authors: C. Kalamani, K. Paramasivam

Abstract:

Test data compression is an efficient method for reducing the test application cost. The problem of reducing test data has been addressed by researchers in three different aspects: Test Data Compression, Built-in-Self-Test (BIST) and Test set compaction. The latter two methods are capable of enhancing fault coverage with cost of hardware overhead. The drawback of the conventional methods is that they are capable of reducing the test storage and test power but when test data have redundant length of runs, no additional compression method is followed. This paper presents a modified Run Length Coding (RLC) technique with Multilevel Selective Huffman Coding (MLSHC) technique to reduce test data volume, test pattern delivery time and power dissipation in scan test applications where redundant length of runs is encountered then the preceding run symbol is replaced with tiny codeword. Experimental results show that the presented method not only improves the test data compression but also reduces the overall test data volume compared to recent schemes. Experiments for the six largest ISCAS-98 benchmarks show that our method outperforms most known techniques.

Keywords: Modified run length coding, multilevel selective Huffman coding, built-in-self-test modified selective Huffman coding, automatic test equipment.

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1 Modified Scaling-Free CORDIC Based Pipelined Parallel MDC FFT and IFFT Architecture for Radix 2^2 Algorithm

Authors: C. Paramasivam, K. B. Jayanthi

Abstract:

An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.

Keywords: Coordinate Rotational Digital Computer(CORDIC), Complex multiplier, Fast Fourier transform (FFT), Inverse fast Fourier transform (IFFT), Multipath delay Commutator (MDC), modified scaling free CORDIC, complex multiplier, pipelining, parallel processing, radix-2^2.

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