Search results for: Kuhelee Chandel

Authors: Kuhelee Chandel, Julia Åhlén, Stefan Seipel

Abstract:

This study evaluates the accuracy of Microsoft HoloLens (Version 1) for small-scale industrial activities, comparing its measurements to ground truth data from a Kuka Robotics arm. Two experiments were conducted to assess its position-tracking capabilities, revealing that the HoloLens device is effective for measuring the position of dynamic objects with small dimensions. However, its precision is affected by the velocity of the trajectory and its position within the device's field of view. While the HoloLens device may be suitable for small-scale tasks, its limitations for more complex and demanding applications requiring high precision and accuracy must be considered. The findings can guide the use of HoloLens devices in industrial applications and contribute to the development of more effective and reliable position-tracking systems.

Keywords: Augmented Reality, AR, Microsoft HoloLens, object tracking, industrial processes.

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Authors: Sandeep Singh Gill, Rajeevan Chandel, Ashwani Chandel

Abstract:

This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-partitioning. Ant colony optimization is an optimization method based on behaviour of social insects [27] whereas Genetic algorithm is an evolutionary optimization technique based on Darwinian Theory of natural evolution and its concept of survival of the fittest [19]. Both the methods are stochastic in nature and have been successfully applied to solve many Non Polynomial hard problems. Results obtained show that Genetic algorithms out perform Ant Colony optimization technique when tested on the VLSI circuit bi-partitioning problem.

Keywords: Partitioning, genetic algorithm, ant colony optimization, non-polynomial hard, netlist, mutation.

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Authors: Sunil Jadav, Rajeevan Chandel Munish Vashishath

Abstract:

Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Keywords: Current Mode, Voltage Mode, VLSI Interconnect.

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