Search results for: A.Ghamari
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 3

Search results for: A.Ghamari

3 Bond Strength in Thermally Sprayed Gas Turbine Shafts

Authors: M.Jalali Azizpour, S.Norouzi, D.Sajedipour, H.Mohammadi majd, S.A.Hosseini, H.Talebi, A.Ghamari

Abstract:

In this paper, the bond strength of thermal spray coatings in high speed shafts has been studied. The metallurgical and mechanical studies has been made on the coated samples and shaft using optical microscopy, scanning electron microscopy (SEM).

Keywords: Thermal spray, Residual stress, Wear mechanism, HVOF, Gas compressor shafts

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2 Application of HVOF Thermal Spraying inHigh Speed Gas Compressor Shafts

Authors: M.Jalali Azizpour, S.norouzi, H.mohammadi majd, H.Talebi, A.Ghamari

Abstract:

In this paper, the application of thermal spray coatings in high speed shafts by a revolution up to 23000 RPM has been studied. Gas compressor shafts are worn in contact zone with journal therefore will be undersized. Wear mechanisms of compressor shaft were identified. The predominant wear mechanism is abrasion wear. The worn surface was coated by hard WC-Co cermets using high velocity oxy fuel (HVOF) after preparation. The shafts were in satisfactory service in 8000h period. The metallurgical and Tribological studies has been made on the worn and coated shaft using optical microscopy, scanning electron microscopy (SEM) and X-ray diffraction.

Keywords: Thermal spray, Residual stress, Wear mechanism, HVOF, Gas compressor shafts.

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1 Lowering Error Floors by Concatenation of Low-Density Parity-Check and Array Code

Authors: Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare

Abstract:

Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error-ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss.

Keywords: Concatenated coding, low–density parity–check codes, array code, error floors.

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