Performance Comparison of Real Time EDAC Systems for Applications On-Board Small Satellites

Authors: Y. Bentoutou

Abstract:

On-board Error Detection and Correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer and its local memory. This paper presents a comparison of the performance of four low complexity EDAC techniques for application in Random Access Memories (RAMs) on-board small satellites. The performance of a newly proposed EDAC architecture is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given for a period of 8 years

Keywords: Error Detection and Correction; On-board computer; small satellite missions

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1072680

References:

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