TY - JFULL AU - Y. Bentoutou PY - 2011/6/ TI - Performance Comparison of Real Time EDAC Systems for Applications On-Board Small Satellites T2 - International Journal of Electrical and Computer Engineering SP - 465 EP - 469 VL - 5 SN - 1307-6892 UR - https://publications.waset.org/pdf/9391 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 53, 2011 N2 - On-board Error Detection and Correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer and its local memory. This paper presents a comparison of the performance of four low complexity EDAC techniques for application in Random Access Memories (RAMs) on-board small satellites. The performance of a newly proposed EDAC architecture is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given for a period of 8 years ER -