Gate Tunnel Current Calculation for NMOSFET Based on Deep Sub-Micron Effects

Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.

Keywords: Gate tunneling current, analytical model, gate dielectrics, non uniform poly gate doping, MOSFET, fringing field effect and image charges.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1083029

References:

[1] H.S.P. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann, J.J. Welser, Proc. IEEE 87 (4) (1999) 537.
[2] SIA: ITRS Roadmap, 2005 Edition.
[3] C. -H. Choi, K. Y. Nam, Z. Yu, and R. W. Dutton, "Impact of gate direct tunneling current on circuit performance: A simulation study," IEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec. 2001.
[4] F. Rana, S. Tiwari, and D. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, pp. 1104-1106, 1996.
[5] S. -H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantummechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
[6] W. -K. Shih et al., "Modeling gate leakage current in nmos structures due to tunneling through an ultra-thin oxide," Solid State Electron., vol. 42, pp. 997-1006, June 1998.
[7] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[8] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Tech. Dig. VLSI Sym., 2000, pp. 174-175.
[9] Y. Ando and T. Itoh, "Calculation of transmission tunneling current across arbitrary potential barriers," J. Appl. Phys., vol. 61, no. 4, p. 1497, 1987
[10] K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-thin silicon dioxide leakage current and scaling limit," Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19, 1992.
[11] K. F. Schuegraf and C. Hu, "Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation," IEEE Transactions on Electron Devices, vol. 41, no. 5, May 1994.
[12] W. -C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling," Symposium on VLSI Technology Digest of Technical Papers, pp. 198, 2000.
[13] W. -C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling," IEEE Transactions on Electron Devices, vol. 48, no. 7, Jul. 2001.
[14] Xin (Ben) Gu, Ten-Lon Chen, Gennady Gildenblat,, Glenn O. Workman, Surya Veeraraghavan, Shye Shapira, and Kevin Stiles, "A Surface Potential-Based Compact Model of n-MOSFET Gate- Tunneling Current," IEEE Transactions on Electron Devices, vol. 51, no. 1, January 2004
[15] Chang-Hoon Choi, P. R. Chidambaram, Rajesh Khamankar, Charles F. Machala, Zhiping Yu, and Robert W. Dutton, "Dopant Profile and Gate Geometric Effects on Polysilicon Gate Depletion in Scaled MOS,"IEEE Transactions on Electron Devices, vol. 49, no. 7, July 2002(2)
[16] H. J. Wen, R. Ludeke, D. M. Newns, and S. H. Lo, J. Vac. Sci. Technol. A 15(3), May/Jun 1997.
[17] L. E. Calvet, R. G. Wheeler, and M. A. Reed, Applied Physics Letters, vol 80, No 10, March 2002.
[18] S. M. Sze, "Metal-Semiconductor Contacts", in Physics of Semiconductor Devices, (Publishers: J Wiley & Sons, Singapore), 2nd Edition 1981, pp 250 - 254
[19] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Tech. Dig. VLSI Sym., 2000, pp. 174-175
[20] Fabien Pr_egaldiny , Christophe Lallement, Daniel Mathiot," Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface potential-based MOSFET model," Solid-State Electronics 48 (2004) 781-787
[21] Taur, Y., and Ning, T.H, (Cambridge University Press, New York, 1998
[22] Santaurus Process and Device Simulator