Search results for: non uniform poly gate doping

Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.

Keywords: Gate tunneling current, analytical model, gate dielectrics, non uniform poly gate doping, MOSFET, fringing field effect and image charges.

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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Authors: Hardik Vaghela, Mamta Khosla, Balwindar Raj

Abstract:

In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (I_ON / I_OFF) of 2.66 × 10¹⁴ (I_ON at V_GS=1.5V, V_DS=1V and I_OFF at V_GS=0V, V_DS=1V) for gate length of 20nm and HfO₂ as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.

Keywords: Ambipolar effect, double gate PN diode based tunnel field effect transistor, high-κ dielectric material, subthreshold slope, tunnel field effect transistor.

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Authors: Malgorzata Kurleto

Abstract:

This study is trying to analyse the organization of the anti-doping system globally (particularly in Poland). The analysis is going to show the concept of doping, indicating the types of doping, and list of banned substances and methods. The paper discusses ethical aspects of the global anti-doping system. The analysis is focusing on organization of global Anti-Doping Agency. The paper will try to describe the basic assumptions of regulations adopted by WADA, called "standards” as well organization and functioning of the Polish Anti-Doping Agency (including the legal basis: POLADA). The base for this discuss will be the Polish 2018 annual report, which shows the most important assumptions, implementation and the number of anti-doping proceedings conducted in Poland. The aim of this paper is to show ethical arguments on anti-doping management strategies.

Keywords: Anti-doping, ethical dilemmas, sports doping, WADA, POLADA.

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Authors: F. Halabchi, A. Esteghamati, A. Razzaghi, A. Noori

Abstract:

Nowadays, doping is an intricate dilemma. Wrestling is the nationally popular sport in Iran. Also the prevalence of doping may be high, due to its power demanding characteristics. So, we aimed to assess the knowledge and attitudes toward doping among the club wrestlers. In a cross sectional study, 426 wrestlers were studied. For this reason, a researcher made questionnaire was used. In this study, researchers selected the clubs by randomized clustered sampling and distributed the questionnaire among wrestlers. Knowledge of wrestlers in three categories of doping definitions, recognition of prohibited drugs and side effects was poor or moderate in 70.8%, 95.8% and 99.5%, respectively. Wrestlers have poor knowledge in doping. Furthermore, they believe some myths which are unfavorable. It seems necessary to design a comprehensive educational program for all of the athletes and coaches.

Keywords: Attitude, Doping, Knowledge, Wrestling

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Authors: Paniz Tafakori, Ali A. Orouji

Abstract:

In this paper the features of multiple material gate silicon-on-insulator MOSFETs are presented and compared with single material gate silicon-on-insulator MOSFET structures. The results indicate that the multiple material gate structures reduce short channel effects such as drain induce barrier lowering, hot electron effect and better current characteristics in comparison with single material structures

Keywords: Short-channel effects (SCEs), Dual material gate (DMG), Triple material gate (TMG), Pentamerous material gate (PMG).

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Authors: Muhibul Haque Bhuyan

Abstract:

This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO₂), aluminum silicate (Al₂SiO₅), silicon nitride (Si₃N₄), alumina (Al₂O₃), hafnium silicate (HfSiO₄), tantalum pentoxide (Ta₂O₅), hafnium dioxide (HfO₂), zirconium dioxide (ZrO₂), and lanthanum oxide (La₂O₃) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.

Keywords: Linear symmetric pocket profile, pocket implanted n-MOS Device, model, impact of gate material, insulator thickness.

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Authors: Bu Jianhui, Bi Jinshun, Liu Mengxin, Luo Jiajun, Han Zhengsheng

Abstract:

The floating body effect is a serious problem for the PDSOI MOSFET, and the H-gate layout is frequently used as the body contact to eliminate this effect. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with finger gate, the necessity of the new models for the H-gate device arises. A simulation model for the H-gate PDSOI MOSFET is proposed based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and then the model is well verified by the ring-oscillator.

Keywords: PDSOI H-gate Device model Body contact.

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Authors: Yun-Hsuan Yu, Chi-Shung Tang, Nzar Rauf Abdullah, Vidar Gudmundsson

Abstract:

Spin-orbit gap feature in energy dispersion of one-dimensional devices is revealed via strong spin-orbit interaction (SOI) effects under Zeeman field. We describe the utilization of a finger-gate or a top-gate to control the spin-dependent transport characteristics in the SOI-Zeeman influenced split-gate devices by means of a generalized spin-mixed propagation matrix method. For the finger-gate system, we find a bound state in continuum for incident electrons within the ultra-low energy regime. For the top-gate system, we observe more bound-state features in conductance associated with the formation of spin-associated hole-like or electron-like quasi-bound states around band thresholds, as well as hole bound states around the reverse point of the energy dispersion. We demonstrate that the spin-dependent transport behavior of a top-gate system is similar to that of a finger-gate system only if the top-gate length is less than the effective Fermi wavelength.

Keywords: Spin-orbit, Zeeman, top-gate, finger-gate, bound state.

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Authors: A. Douara, N. Kermas, B. Djellouli

Abstract:

In this study, we report calculations of gate capacitance of AlGaN/GaN HEMTs with nextnano device simulation software. We have used a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. These simulations explore various device structures with different values of barrier thickness and channel thickness. A detailed understanding of the impact of gate capacitance in HEMTs will allow us to determine their role in future 10 nm physical gate length node.

Keywords: AlGaN/GaN, centroid capacitance, gate capacitance, HEMT, quantum capacitance.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

This paper presents a new compact analytical model of the gate leakage current in high-k based nano scale MOSFET by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of high-k gate dielectric in place of SiO2.

Keywords: Analytical model, High-k gate dielectrics, inelastic trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.

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Authors: M. Khaouani, A. Guen-Bouazza, B. Bouazza, Z. Kourdi

Abstract:

The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable I_ON/I_OFF ratio of (10⁴) and low drain induced barrier lowering (DIBL) of 39 mV/V.

Keywords: GAA, SILVACO, QUANTUM, MOSFETs.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, triple gate, and gate all around nano wires were studied to investigate the impact of increasing the number of gates on the control of the short channel effect which is important in nanoscale devices. Also in the case of triple gate rectangular SNWT inserting extra gates on the bottom of device can improve the application of device. The results indicate that by using gate all around structures short channel effects such as DIBL, subthreshold swing and delay reduces.

Keywords: SNWT (silicon nanowire transistor), non equilibriumGreen's function (NEGF), double gate (DG), triple gate (TG), multiple gate, cylindrical nano wire (CW), rectangular nano wire(RW), Poisson_ Schrödinger solver, drain induced barrier lowering(DIBL).

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Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Pujarini Ghosh A, Rishu Chaujar B, Subhasis Haldar C, R.S Gupta D, Mridula Gupta E

Abstract:

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material work function difference on drain current noise spectral density of the device reflecting its applicability for circuit design applications.

Keywords: Cylindrical/Surrounded gate (SGT/CGT) MOSFET, Gate Material Engineering (GME), Spectral Noise and short channeleffect (SCE).

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Authors: Porag Jyoti Ligira, Gargi Khanna

Abstract:

The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthreshold slope of ~60 mV/decade can be achieved by using highk dielectric. The effects of variation of spacer length and material on the electrical characteristic of BPJLT are also investigated in the paper. The ION / IOFF ratio improvement is of the order of 107 and the OFF current reduction of 10-4 is obtained by using gate dielectric of HfO2 instead of SiO2.

Keywords: BPJLT, double gate, high-k, spacer.

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Authors: V. Barbakadze, L. Gogilashvili, L. Amiranashvili, M. Merlani, K .Mulkijanyan

Abstract:

According to IR, 13C and 1H NMR, APT, 1D NOE, 2D heteronuclear 1H/13C HSQC and 2D DOSY experiments the main chemical constituent of high-molecular preparations from Symphytum asperum, S. caucasicum, S. officinale and Anchusa italica (Boraginaceae) was found to be caffeic acid-derived polyether, namely poly[3-(3,4-dihydroxyphenyl)glyceric acid] (PDPGA) or poly[oxy-1-carboxy-2-(3,4-dihydroxyphenyl)ethylene]. Most carboxylic groups of this polymer of A. italica are methylated.

Keywords: Anchusa, poly[3-(3, 4-dihydroxyphenyl)glyceric acid], poly[oxy-1-carboxy-2-(3, 4-dihydroxyphenyl)ethylene], Symphytum.

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Authors: Kankeyanathan Kannan

Abstract:

The uniform Roe C*-algebra (also called uniform translation)C^*- algebra provides a link between coarse geometry and C^*- algebra theory. The uniform Roe algebra has a great importance in geometry, topology and analysis. We consider some of the elementary concepts associated with coarse spaces. 

Keywords: Invariant Approximation Property, Uniform Roe algebras.

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

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Authors: Smaali Assia, Outemzabet Ratiba, Media El Mahdi, Kadi Mohamed

Abstract:

Films of pure tin oxide SnO2 and in presence of antimony atoms (SnO2-Sb) deposited onto glass substrates have shown a sufficiently high energy gap to be transparent in the visible region, a high electrical mobility and a carrier concentration which displays a good electrical conductivity [1]. In this work, the effects of polycrystalline silicon substrate on the optical properties of pure and Sb doped tin oxide is investigated. We used the APCVD (atmospheric pressure chemical vapour deposition) technique, which is a low-cost and simple technique, under nitrogen ambient, for growing this material. A series of SnO2 and SnO2-Sb have been deposited onto polycrystalline silicon substrates with different contents of antimony atoms at the same conditions of deposition (substrate temperature, flow oxygen, duration and nitrogen atmosphere of the reactor). The effect of the substrate in terms of morphology and nonlinear optical properties, mainly the reflectance, was studied. The reflectance intensity of the device, compared to the reflectance of tin oxide films deposited directly on glass substrate, is clearly reduced on the overall wavelength range. It is obvious that the roughness of the poly-c silicon plays an important role by improving the reflectance and hence the optical parameters. A clear shift in the minimum of the reflectance upon doping level is observed. This minimum corresponds to strong free carrier absorption, resulting in different plasma frequency. This effect is followed by an increase in the reflectance depending of the antimony doping. Applying the extended Drude theory to the combining optical and electrical obtained results these effects are discussed.

Keywords: Doping, oxide, reflectance.

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Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: CMOS transistor, direct-tunneling current, floatinggate, gate-leakage current, simulation model.

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Authors: A. A. Akande, B. P. Dhonge, B. W. Mwakikunga, A. G. J. Machatine

Abstract:

This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH₄VO₃ precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO₂ (B) with V₂O₅ and an amorphous phase. The BET surface area is found to be 67.67 m²/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO₂ sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO₂ sensors which normally show response and recovery times of the order of 5 minutes (300 s).

Keywords: VO2, VO2 (B), V2O5, MOSFET, gate voltage, humidity sensor.

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Authors: Omid Mirmotahari, Yngvar Berg

Abstract:

In this paper we promote the Ultra Low Voltage (ULV) NAND gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack.

Keywords: Differential Power Analysis (DPA), Low Voltage (LV), Ultra Low Voltage (ULV), Floating-Gate (FG), supply current analysis.

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Authors: Asma M. Milad, Mohammad B. Kassim, Wan R. Daud

Abstract:

Highly ordered TiO2 nanotube (TNT) arrays were fabricated onto a pre-treated titanium foil by anodic oxidation with a voltage of 20V in phosphoric acid/sodium fluoride electrolyte. A pretreatment of titanium foil involved washing with acetone, isopropanol, ethanol and deionized water. Carbon doped TiO2 nanotubes (C-TNT) was fabricated 'in-situ' with the same method in the presence of polyvinyl alcohol and urea as carbon sources. The affects of polyvinyl alcohol concentration and oxidation time on the composition, morphology and structure of the C-TN were studied by FE-SEM, EDX and XRD techniques. FESEM images of the nanotubes showed uniform arrays of C-TNTs. The density and microstructures of the nanotubes were greatly affected by the content of PVA. The introduction of the polyvinyl alcohol into the electrolyte increases the amount of C content inside TiO2 nanotube arrays uniformly. The influence of carbon content on the photo-current of C-TNT was investigated and the I-V profiles of the nanotubes were established. The preliminary results indicated that the 'in-situ' doping technique produced a superior quality nanotubes compared to post doping techniques.

Keywords: Anodization, photoelectrochemical cell, 'in-situ', post doping, thin film, and titania nanotube arrays.

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Authors: A.Doustgani, E.Vasheghani- Farahani, M. Soleimani, S. Hashemi-Najafabadi

Abstract:

Aligned and random nanofibrous scaffolds of PVA/PCL/nHA were fabricated by electrospinning method. The composite nanofibrous scaffolds were subjected to detailed analysis. Morphological investigations revealed that the prepared nanofibers have uniform morphology and the average fiber diameters of aligned and random scaffolds were 135.5 and 290 nm, respectively. The obtained scaffolds have a porous structure with porosity of 88 and 76% for random and aligned nanofibers, respectively. Furthermore, FTIR analysis demonstrated that there were strong intramolecular interactions between the molecules of PVA/PCL/nHA. On the other hand, mechanical characterizations show that aligning the nanofibers, could significantly improve the rigidity of the resultant biocomposite nanofibrous scaffolds.

Keywords: Electrospinnig, nanofibrous scaffold, poly (vinyl alcohol), polycaprolactone.

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Authors: Aliakbar Sayadi, Thomas R. Neitzert, G. Charles Clifton, Min Cheol Han

Abstract:

The present study aims to assess the performance of vermiculite concrete containing poly-lactic acid beads as an eco-friendly aggregate. Vermiculite aggregate was replaced by poly-lactic acid in percentages of 0%, 20%, 40%, 60% and 80%. Mechanical and thermal properties of concrete were investigated. Test results indicated that the inclusion of poly-lactic acid decreased the PH value of concrete and all the poly-lactic acid particles were dissolved due to the formation of sodium lactide and lactide oligomers when subjected to the high alkaline environment of concrete. In addition, an increase in thermal conductivity value of concrete was observed as the ratio of poly-lactic acid increased. Moreover, a set of equations was proposed to estimate the water-cement ratio, cement content and water absorption ratio of concrete.

Keywords: Poly-lactic acid, PLA, vermiculite, concrete, eco-friendly, mechanical properties.

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Authors: Prakash Chand, Anurag Gaur, Ashavani Kumar

Abstract:

In the present study, we have synthesized Cr and Fe doped zinc oxide (ZnO) nanostructures (Zn1-δCraFebO; where δ = a + b = 20%, a = 5, 6, 8 & 10% and b = 15, 14, 12 & 10%) via sol-gel method at different doping concentrations. The synthesized samples were characterized for structural properties by X-ray diffractrometer and field emission scanning electron microscope and the optical properties were carried out through photoluminescence and UVvisible spectroscopy. The particle size calculated through field emission scanning electron microscope varies from 41 to 96 nm for the samples synthesized at different doping concentrations. The optical band gaps calculated through UV-visible spectroscopy are found to be decreasing from 3.27 to 3.02 eV as the doping concentration of Cr increases and Fe decreases.

Keywords: Nanostructures, Optical Properties, Sol-gel method.

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Authors: A. Kamath, Z. X. Chen, C. J. Gu, F. Zheng, X. P. Wang, N. Singh, G-Q. Lo

Abstract:

In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET.  The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.

Keywords: LFN analysis, junctionless, Current conduction path, FinFET.

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