**Commenced**in January 2007

**Frequency:**Monthly

**Edition:**International

**Paper Count:**32794

##### Doping Profile Measurement and Characterization by Scanning Capacitance Microscope for PocketImplanted Nano Scale n-MOSFET

**Authors:**
Muhibul Haque Bhuyan,
Farseem Mannan Mohammedy,
Quazi Deen Mohd Khosru

**Abstract:**

**Keywords:**
Linear Pocket Profile,
Pocket Implanted n-MOSFET,
Scanning Capacitance Microscope,
Atomic Force Microscope.

**Digital Object Identifier (DOI):**
doi.org/10.5281/zenodo.1078727

**References:**

[1] M. Nishida and H. Onodera, "An anomalous increase of threshold voltage with shortening the channel lengths for deeply boron-implanted n-channel MOSFETs," IEEE Transactions on Electron Devices, vol. 48, pp. 1101, 1981.

[2] M. Orlowski, C. Mazure, and F. Lau, "Submicron short-channel effects due to gate reoxidation induced lateral interstitial diffusion," in IEEE IEDM Technical Digest, 1987, pp. 87-632.

[3] C. Rafferty, H. Vuong, S. Eshraghi, M. Giles, M. Pinto, and S. Hillenius, "Explanation of reverse short-channel effect by defect gradients," in IEEE IEDM Technical Digest, 1993, pp. 93-311.

[4] G.G. Shahidi, J. Warnock, S. Fischer, P. A. McFarland, A. Acovic, S. Subbanna, E. Ganin, E. Crabbe, J. Comfort, J. Y.-C. Sun, T. H. Ning, and B. Davari, "High-performance devices for a 0.15-╬╝m CMOS technology," IEEE Electron Device Letters, vol. 14, pp. 466-468, Oct. 1993.

[5] B. Yu, C. H. J. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET-s," IEEE Transactions on Electron Devices, vol. 44, pp. 627- 634, April 1997.

[6] S. M. Sze, "Physics of Semiconductor Devices," 2nd Edition, John Wiley and Sons, New York, ch. 8, 1981.

[7] P. C. Zalm, "The application of dynamic SIMS in silicon semiconductor technology," Philips Journal of Research, vol. 47, nos. 3-5, pp. 287-302, 1993.

[8] G. J. L. Ouwerling, "A problem-specific inverse method for twodimensional doping profile determination from capacitance-voltage measurements," Solid State Electronics, vol. 34, no. 2, pp. 197-214, 1991.

[9] N. Khalil, J. Faricelli, D. Bell, and Selberherr, "The extraction of twodimensional MOS transistor doping via inverse modeling," IEEE Electron Device Lett., vol. 16, pp. 17-19, Jan. 1995.

[10] Z. K. Lee, M. B. McIlrath and D. A. Antoniadis, "Two dimensional doping profile characterization of MOSFET-s by inverse modeling using I-V characteristics in the subthreshold region," IEEE Transactions on Electron Devices, vol. 46, pp. 1640-1649, Aug. 1999.

[11] R. N. Kleiman, M. L. O-Malley, F. H. Baumann, J. P. Garno and G. L. Timp, "Junction delineation of 0.15 m MOS devices using scanning capacitance mircoscopy," in IEDM Technical Digest, 1997, pp. 691-694.

[12] W. Rosner, W. Hansch, B. Moore, M. Orlowski, A. Spitzer, and C. Werner, DRC Proceedings, p. 9, 1990.

[13] S. T. Ahn and W. A. Tiller, Journal of Electrochemical Society, vol. 135, p. 2370, 1988.

[14] S. H. Goodwin-Johnson, R. Subrahmanyan, C.E. Floyd and H. Z. Massoud, "Two-dimensional impurity profiling with emission computed tomography techniques," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 8, no. 4, pp. 323-335, 1989.

[15] C.C. Williams, J. Slinkman, W.P. Hough, and H.K. Wickramasinghe, "Lateral dopant profiling with 200 nm resolution by scanning capacitance microscopy," Applied Physics Letters, Vol. 55, no.16, p. 1662-1664, Oct. 1989.

[16] D. W. Abraham, C. Williams, J. Slikman, and H. K. Wickramasinghe, "Lateral dopant profiling in semiconductors by force microscopy using capacitive detection," Journal of Vacuum Science and Technology, vol. B9, pp. 703, 1991.

[17] S. Hosaka, S. Hosoki, K. Takata, K. Horiuchi, and N. Natsuaki, "Observation of pn junctions on implanted silicon using a scanning tunneling microscope," Applied Physics Letters, vol. 53, pp. 487, 1988.

[18] S. Kordic, E.J. Van Loenon, D. Dijkkamp, A.J. Hoeven and H.K. Moraai, "Scanning tunneling microscopy on cleaved silicon pn junctions," IEEE IEDM Technical Digest, pp. 277-280, 1989.

[19] J. R. Matey and J. Blanc, "Scanning capacitance microscopy," Journal of Applied Physics, vol. 57, no. 5, pp. 1437-1444, 1985.

[20] C. C. Williams, W. P. Hough and S. A. Rishton, "Scanning capacitance microscopy on a 25 nm scale," Applied Physics Letters, vol. 55, pp. 203 - 205, 1989.

[21] Y. Huang and C. C. Williams, "Capacitance-voltage measurement and modeling on a nanometer scale by scanning C-V microscopy," Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, vol. 12, no. 1, pp. 369-372, 1994.

[22] H. Edwards, R. McGlothlin, R. S. Martin, Elisa U, M. Gribelyuk, R. Mahaffy, C. K. Shih, R. S. List and V. A. Ukraintsev, "Scanning Capacitance Spectroscopy: An analytical technique for p-n junction delineation in Si devices," Applied Physics Letters vol. 72, 1998, pp. 698-700.

[23] W. Van Gelder and E.H. Nicollian, "Silicon impurity distribution as revealed by pulsed MOS C-V measurements," Solid State Science, Journal of Electrochemical Society, vol. 118, p. 138-141, 1971.

[24] M. H. Bhuyan and Q. D. M. Khosru, "Linear pocket profile based threshold voltage model for sub-100 nm n-MOSFET incorporating substrate and drain bias effects," in Proc. of the 5th International Conference on Electrical and Computer Engineering (ICECE 2008), 20-22 December 2008, Dhaka, Bangladesh, pp. 447-451.

[25] M. H. Bhuyan and Q. D. M. Khosru, "Linear profile based analytical surface potential model for pocket implanted sub-100 nm n-MOSFET," Journal of Electron Devices, France, ISSN 1682-3427, vol. 7, 2010, pp 235-240.

[26] M. H. Bhuyan and Q. D. M. Khosru, "Inversion layer effective mobility model for pocket implanted nano scale n-MOSFET," International Journal of Electrical and Electronics Engineering, ISSN 2010-3972, vol. 5, no. 1, Januay 2011, pp. 50-57.

[27] Muhibul Haque Bhuyan and Q. D. M. Khosru, "An Analytical Subthreshold Drain Current Model for Pocket Implanted Nano Scale n- MOSFET," Journal of Electron Devices, France, ISSN 1682-3427, vol. 8, October 2010, pp. 263-267.

[28] M. H. Bhuyan and Q. D. M. Khosru, "Low frequency drain current flicker noise model for pocket implanted nano scale n-MOSFET," in Proc. of the IEEE Nanotechnology Materials and Devices Conference (NMDC 2010), 12-15 October 2010, California, USA, pp. 295-299.