Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30458
Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies

Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: simulation model, CMOS transistor, direct-tunneling current, gate-leakage current, floatinggate

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1108302

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2487

References:


[1] J. Ramirez-Angulo, S. C. Choi and G. Gonzalez-Altamirano. Lowvoltage circuits building blocks using multiple-input floating-gate transistors. Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on 42(11), pp. 971-974. 1995.
[2] S. Sharma, S. S. Rajput, L. K. Magotra and S. S. Jamuar. FGMOS based wide range low voltage current mirror and its applications. Presented at Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference On. 2002,. DOI: 10.1109/APCCAS.2002.1115251.
[3] D. I. R. Chavez, J. de la Cruz Alejo and J. C. S. Garcia. Design of S? Modulators using FGMOS transistors. Presented at Electrical Engineering Computing Science and Automatic Control (CCE), 2011 8th International Conference On. 2011, DOI: 10.1109/ICEEE.2011.6106599.
[4] J. Ramirez-Angulo, G. Gonzalez-Altamirano and S. C. Choi. Modeling multiple-input floating-gate transistors for analog signal processing. Presented at Circuits and Systems, 1997. ISCAS '97. Proceedings of 1997 IEEE International Symposium On. 1997.
[5] Liming Yin, S. H. K. Embabi and E. Sanchez-Sinencio. A floating-gate MOSFET D/A converter. Presented at Circuits and Systems, 1997. ISCAS '97. Proceedings of 1997 IEEE International Symposium On. 1997.
[6] Ai Chen Low and P. Hasler. Cadence-based simulation of floating-gate circuits using the EKV model. Presented at Circuits and Systems, 1999. 42nd Midwest Symposium On. 1999, DOI: 10.1109/MWSCAS.1999.867228.
[7] Dongwoo Lee, W. Kwong, D. Blaauw and D. Sylvester. Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design. Presented at Quality Electronic Design, 2003. Proceedings. Fourth International Symposium On. 2003. DOI: 10.1109/ISQED.2003.1194747.
[8] C. Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu and R. W. Dutton. Direct tunneling current model for circuit simulation. Presented at Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International. 1999. DOI: 10.1109/IEDM.1999.824256.
[9] C. Choi, Ki-Young Nam, Zhiping Yu and R. W. Dutton. Impact of gate direct tunneling current on circuit performance: A simulation study. Electron Devices, IEEE Transactions On 48(12), pp. 2823-2829. 2001. . DOI: 10.1109/16.974710.
[10] Z. Saheb and E. El-Masry, "Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies," Analog Integrated Circuits and Signal Processing, 2015.