World Academy of Science, Engineering and Technology

Authors: Lida Haghnegahdar, Ezzatollah Asgharizadeh

Abstract:

Value engineering is an efficacious contraption for administrators to make up their minds. Value perusals proffer the gaffers a suitable instrument to decrease the expenditures of the life span, quality amelioration, structural improvement, curtailment of the construction schedule, longevity prolongation or a merging of the aforementioned cases. Subjecting organizers to pressures on one hand and their accountability towards their pertinent fields together with inherent risks and ambiguities of other options on the other hand set some comptrollers in a dilemma utilization of risk management and the value engineering in projects manipulation with regard to complexities of implementing projects can be wielded as a contraption to identify and efface each item which wreaks unnecessary expenses and time squandering sans inflicting any damages upon the essential project applications. Of course It should be noted that implementation of risk management and value engineering with regard to the betterment of efficiency and functions may lead to the project implementation timing elongation. Here time revamping does not refer to time diminishing in the whole cases. his article deals with risk and value engineering conceptualizations at first. The germane reverberations effectuated due to its execution in Iran Khodro Corporation are regarded together with the joint features and amalgamation of the aforesaid entia; hence the proposed blueprint is submitted to be taken advantage of in engineering and industrial projects including Iran Khodro Corporation.

Keywords: Management, risk engineering, value engineering, project manipulation, Iran Khodro.

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Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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