Search results for: K. Baskaran
2 Nepros- An Innovated Crystal Necklace
Authors: Amir A. N, Fadzilan A. M, Baskaran G.
Abstract:
In this paper, we proposed an invention of an accessory into a communication device that will help humans to be connected universally. Generally, this device will be made up of crystal and will combine many technologies that will enable the user to run various applications and software anywhere and everywhere. Bringing up the concept of from being user friendly, we had used the crystal as the main material of the device that will trap the surrounding lights to produce projection of its screen. This leads to a lesser energy consumption and allows smaller sized battery to be used, making the device less bulky. Additionally, we proposed the usage of micro batteries as our energy source. Thus, researches regarding crystal were made along with explanations in details of specification and function of the technology used in the device. Finally, we had also drawn several views of the invention from different sides to be visualized.
Keywords: Crystal, Communication Technology, Future concept device, Micro batteries.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 15331 Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology
Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan
Abstract:
Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2436