A New Performance Characterization of Transient Analysis Method
Commenced in January 2007
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A New Performance Characterization of Transient Analysis Method

Authors: José Peralta, Gabriela Peretti, Eduardo Romero, Carlos Marqués

Abstract:

This paper proposes a new performance characterization for the test strategy intended for second order filters denominated Transient Analysis Method (TRAM). We evaluate the ability of the addressed test strategy for detecting deviation faults under simultaneous statistical fluctuation of the non-faulty parameters. For this purpose, we use Monte Carlo simulations and a fault model that considers as faulty only one component of the filter under test while the others components adopt random values (within their tolerance band) obtained from their statistical distributions. The new data reported here show (for the filters under study) the presence of hard-to-test components and relatively low fault coverage values for small deviation faults. These results suggest that the fault coverage value obtained using only nominal values for the non-faulty components (the traditional evaluation of TRAM) seem to be a poor predictor of the test performance.

Keywords: testing, fault analysis, analog filter test, parametric faults detection.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1074293

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References:


[1] B Vinnakota, Analog and mixed signal test. Upper Saddle River, NJ: Prentice Hall, 1998.
[2] M.L. Bushnell and V.D. Agrawal, Essentials of electronic testing for digital, memory and mixed-signal circuits. New York, NJ: Kluwer Academic Publishers, 2000.
[3] J. Calvano, V. Alves, and M. Lubaszeswski, "Fault detection methodology for second order filters using compact test vectors transient analysis," in 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Puerto Vallarta, Mexico, pp 18- 24, 1999.
[4] J. Calvano, V. Alves, and M. Lubaszeswski, "Fault detection methodology and BIST method for 2nd order Butterworth, Chebyshev and Bessel approximations," in Proceedings 18th IEEE VLSI Test Symposium, Montreal, Canada, pp. 319-324, 2000.
[5] F. Liu and S. Ozev, "Statistical Test Development for Analog Circuits Under High Process Variations", IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 36, no.8, pp. 1465-1477, August 2007.
[6] K. Saab, N. Ben-Hamida, and B. Kaminska, "Parametric fault simulation and test vector generation," in Proceedings Conference on Design, Automation and Test in Europe 2000, Paris, France, pp. 650-656.
[7] A. Khouas and A. Derieux, "Fault simulation for analog circuits under parameter variations," J. of Electronic Testing, vol. 16 no. 3, pp. 269- 278, June 2000.
[8] S. Chang, C. Lee, and J. Chen, "Structural fault based specification reduction for testing analog circuits," J. of Electronic Testing, vol. 18, no. 16, pp.571-581, Dec. 2002.
[9] E. Acar and S. Ozev, "Parametric test development for RF circuits targeting physical faults locations and using specification-based fault definitions," in Proceedings IEEE-ACM International Conference on Computer Aided Design, San Jose, CA, pp. 73-79, 2005
[10] A. Raghunathan, J. Chun, J. Abraham, and A. Chatterjee, "Quasi- Oscillation Based Test for Improved Prediction of Analog Performance Parameters," in Proceedings International Test Conference, Charlotte, NC, pp. 252-261, 2004
[11] A. Chaehoi, Y. Bertrand, L. Latorre, and P. Nouet, "Improving the efficiency of the oscillation based test methodology for parametric faults," in IEEE Latin American Test Workshop, Natal, Brazil, pp. 234- 237, 2003.
[12] A. Chaehoi, L. Latorre, F. Azais, and P. Nouet, "Use of a statistical approach for efficient implementation of oscillation based test strategy," in Proceedings 9th International Mixed Signal Test Workshop, Seville, Spain, pp. 99-103, 2003.
[13] S. Sunter and N. Nagi, "Test metrics for analog parametric faults," in Proceedings of the 17th VLSI Test Symposium, San Diego, CA, pp. 226- 234, 1999.
[14] A. Bounceur, S. Mir, E. Simeu and L. Rolíndez, "Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing", J. Electron Test, vol. 23, no. 6, pp 471-484, December 2007.
[15] A. Mitra, Fundamentals of quality control and improvement. Upper Saddle River, NJ: Prentice Hall, 1998.
[16] S. Spinks, C. Chalk, I. Bell, and M. Zwolinski, "Generation and verification of tests for analog circuits subject to process parameter deviations," J. of Electronic Testing, vol. 20, no. 1, pp. 11-23, Feb. 2004
[17] B. Kaminska, K. Arabi, I. Bell, P. Goteti, J. Huertas, B. Kim, A. Rueda, and M. Soma, "Analog and mixed-signal benchmark circuits - first release," in Proceedings of the International Test Conference, Washington, DC, pp.183-190, 1997.
[18] J. Savir and Z. Guo, "Test limitations of parametric faults in analog circuits," IEEE Trans. Instrum. Meas., vol. 52, no. 5, pp. 1444-1454, Oct. 2003.