Using the Monte Carlo Simulation to Predict the Assembly Yield
Electronics Products that achieve high levels of integrated communications, computing and entertainment, multimedia features in small, stylish and robust new form factors are winning in the market place. Due to the high costs that an industry may undergo and how a high yield is directly proportional to high profits, IC (Integrated Circuit) manufacturers struggle to maximize yield, but today-s customers demand miniaturization, low costs, high performance and excellent reliability making the yield maximization a never ending research of an enhanced assembly process. With factors such as minimum tolerances, tighter parameter variations a systematic approach is needed in order to predict the assembly process. In order to evaluate the quality of upcoming circuits, yield models are used which not only predict manufacturing costs but also provide vital information in order to ease the process of correction when the yields fall below expectations. For an IC manufacturer to obtain higher assembly yields all factors such as boards, placement, components, the material from which the components are made of and processes must be taken into consideration. Effective placement yield depends heavily on machine accuracy and the vision of the system which needs the ability to recognize the features on the board and component to place the device accurately on the pads and bumps of the PCB. There are currently two methods for accurate positioning, using the edge of the package and using solder ball locations also called footprints. The only assumption that a yield model makes is that all boards and devices are completely functional. This paper will focus on the Monte Carlo method which consists in a class of computational algorithms (information processed algorithms) which depends on repeated random samplings in order to compute the results. This method utilized in order to recreate the simulation of placement and assembly processes within a production line.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1070649Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1970
 C. Y. Huang, "Reducing Solder Paste Inspection in Surface Mount Assembly through Mahalanobis-Taguchi Analysis," IEEE Transactions on Electronics Packaging Manufacturing, Vol. 33, No. 4, pp. 265-274, 2010.
 S. H. Mannan, N. N. Ekere, "Predicting Scooping and Skipping in Solder Paste Printing for Reflow Soldering of SMT Devices," Soldering and Surface Mount Technology Journal, Vol. 15, pp. 14-17, 1993.
 C. Y. Huang, M. S. Li, J. L. Ku, H. C. Hsieh, "Chemical Characterization of Failures And Process Materials for Microelectronics Assembly," Microelectronics International, Vol. 26, No. 3, pp. 41-48, August 2009.
 S. Chada, A. Herrmann, W. Laub, R. Fournelle, D. Shangguan, and A. Achari, "Microstructural Investigation of Sn-Ag and Sn-Ag Solder Joints," Soldering and Surface Mount Tech. Vol. 9, Iss. 2, pp. 9, 1997.
 A. Fazzi, L. Magagni, M. De Dominicis, P. Zoffoli, R. Canegallo1, P.L. Rolandi1, A. Sangiovanni-Vincentelli2 and R. Guerrieri, "Yield Prediction for 3D Capacitive Interconnections," Conference on Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM Internationa, pp.809 - 814.