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An Embedded System Design for SRAM SEU Test

Authors: Kyoung Kun Lee, Soongyu Kwon, Jong Tae Kim

Abstract:

An embedded system for SEU(single event upset) test needs to be designed to prevent system failure by high-energy particles during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which manages the DUT and measures the occurrence of SEU. It needs to have considerations for preventing system failure while managing the DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.

Keywords: Embedded system, single event upset, SRAM

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1334387

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