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Evaluating the Impact of Replacement Policies on the Cache Performance and Energy Consumption in Different Multicore Embedded Systems
Authors: Sajjad Rostami-Sani, Mojtaba Valinataj, Amir-Hossein Khojir-Angasi
Abstract:The cache has an important role in the reduction of access delay between a processor and memory in high-performance embedded systems. In these systems, the energy consumption is one of the most important concerns, and it will become more important with smaller processor feature sizes and higher frequencies. Meanwhile, the cache system dissipates a significant portion of energy compared to the other components of a processor. There are some elements that can affect the energy consumption of the cache such as replacement policy and degree of associativity. Due to these points, it can be inferred that selecting an appropriate configuration for the cache is a crucial part of designing a system. In this paper, we investigate the effect of different cache replacement policies on both cache’s performance and energy consumption. Furthermore, the impact of different Instruction Set Architectures (ISAs) on cache’s performance and energy consumption has been investigated.
Keywords: L1-cache, energy consumption, replacement policy, Instruction set architecture, multicore processor.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 768
 J. L. Hennessy, D. A. Patterson. “Computer architecture: a quantitative approach.” Elsevier; 2011.
 H. Esmaeilzadeh, T. Cao, X. Yang, S. Blackburn, K. McKinley, “Looking back to the language and hardware revolutions: measured power, performance, and scaling”, Proc. 16th Int’l. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2011.
 A. Vakil-Ghahani, S. Mahdizadeh-Shahri, M. Lotfi-Namin, et al. “Cache replacement policy based on expected hit count”, IEEE computer architecture letters, 2017.
 R. Olanrewaju, A. Baba, B. Khan, et al. “A study on performance evaluation of conventional cache replacement algorithms: A review”, International conference on parallel, distributed and grid computing (PDGC), 2016.
 D. Swain, S. Marar, N. Motwani, et al. “CWRP: An efficient and classical weight ranking policy for enhancing cache performance”, International conference on image information processing (ICIIP), 2017.
 G. Einziger, R. Friedman, B. Manes, “TinyLFU: A highly efficient cache admission policy”, ACM Transactions on storage (TOS), 2017.
 J. Reineke, D. Grund, C. Berg, R. Wilhelm. “Timing predictability of cache replacement policies”, Real-Time Systems, Volume 37, Issue 2, 2007.
 H. Al-Zoubi, A. Milenkovic, M. Milenkovic. “Performance Evaluation of cache Replacement Policies for the SPEC CPU2000 Benchmark Suite”, In Proc. of the 42nd ACM Southeast Conf, April 2004.
 M. Hai-feng, Y. Nian-min, F. Hong-bo. “Cache Performance Simulations and Analysis under Simplescalar Platform”, International conference on new trends in information and service science, 2009.
 D. Grund, J. Reineke, “Estimating the Performance of Cache Replacement Policies”, IEEE international conference on formal methods and models for Co-Design, 2008.
 M. Zahran, “Cache Replacement Policy”, Proc. Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) held in conjunction with the international Symposium on Computer Architecture (ISCA), 2007.
 N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, et al. “The gem5 simulator”, ACM SIGARCH Computer Architecture News, 39 (2) (2011) 1-7.
 N. Muralimanohar, R. Balasubramonian, N. P. Jouppi. CACTI 6.0: A tool to model large caches. HP Laboratories, 22-31, 2009.
 CACTI, An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model, Available:
 M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown. MiBench: a free, commercially representative embedded benchmark suite. IEEE International Workshop on Workload Characterization, WWC-4. pp. 3-14, 2001.