Commenced in January 2007
Paper Count: 31515
A Thirteen-Level Asymmetrical Cascaded H-Bridge Single Phase Inverter
Abstract:This paper presents a thirteen-level asymmetrical cascaded H-bridge single phase inverter. In this configuration, the desired output voltage level is achieved by connecting the DC sources in different combinations by triggering the switches. The modes of operation are explained well for positive level generations. Moreover, a comparison is made with conventional topologies of diode clamped, flying capacitors and cascaded-H-bridge and some recently proposed topologies to show the significance of the proposed topology in terms of reduced part counts. The simulation work has been carried out in MATLAB/Simulink environment. The experimental work is also carried out for lower rating to verify the performance and feasibility of the proposed topology. Further the results are presented for different loading conditions.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1474599Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 419
 K.K. Gupta, A. Ranjan, P. Bhatnagar, L.K. Sahu and S. Jain, “Multilevel Inverter Topologies with Reduced Device Count: A Review,” IEEE Transactions on Power Electronics, vol.31, no.1, pp.135-151, 2016.
 A. Kirubakaran, and D. Vijayakumar, “Development of Labview based multilevel inverter with reduced number of switches,” International Journal of Power Electronics, vol.6, no.1, pp.88-102, 2014.
 K. Surya Suresh and M. Vishnu Prasad, “Analysis and Simulation of New Seven Level Inverter Topology,” International Journal of Scientific and Research Publications, vol.2. no.4, pp. 1-6, 2012.
 M. A. Chulan and A.H. M. Yatim, “Design and Implementation of a New H-Bridge Multilevel Inverter for 7-Level Symmetric with Less Number of Switches,” IEEE International Conference on Power and Energy, pp.1-6, 2014.
 X. Sun, B. Wang, Y. Zhou, W. Wang, H. Du and Z. Lu, “A Single DC Source Cascaded Seven-Level Inverter Integrating Switched-Capacitor Techniques,” IEEE Transactions on Industrial Electronics, vol. 63, pp. 7184-7194, 2016.
 C. Rech, and J. R. Pinheiro, “Hybrid multilevel converters: Unified analysis and design considerations,” IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 1092-1104, 2007.
 E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haque and M. Sabahi, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology,” Electric Power Systems Research, vol. 77, no.8, pp. 1073-1085, 2007.
 E. Babaei, “Optimal Topologies for Cascaded Sub-Multilevel Converters,” Journal of Power Electronics, vol.10, no. 3, pp. 251-261, 2010.
 E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology with minimum number of switches,” Energy Conversion and Management, vol. 50, no.11, pp. 2761-2767, 2009.
 M.F. Kangarlu, S. H. Hosseini, E. Babaei, and A. Khoshkbar Sadigh, “Transformer Less DVR topology based on multilevel inverter with reduced number of switches,” Power Electronic & Drive Systems & Technologies Conference (PEDSTC), pp. 371-375, 2010.
 M. R. Banaei and E. Salary, “Analysis of a generalized symmetrical multilevel inverter,” Journal of Circuits, Systems, and Computers, vol. 20, no. 2, pp. 299-311, 2011.
 N. Sandeep, and U.R. Yaragatti, “A Switched-Capacitor-Based Multilevel Inverter Topology With Reduced Components,” IEEE Transactions on Power Electronics, vol. 33, No. 7, pp. 5538-5542, 2018.
 K.S. Gayathri Devi, S. Arun, and C Sreeja, “Comparison of Capacitor Voltage Balancing Techniques in Multilevel Inverters,” International Conference on Magnetics, Machines & Drives, pp.1-6, 2014.