FPGA Implementation of Adaptive Clock Recovery for TDMoIP Systems

Authors: Semih Demir, Anil Celebi

Abstract:

Circuit switched networks widely used until the end of the 20^th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.

Keywords: Clock recovery on TDMoIP, FPGA, MATLAB reference model, clock synchronization.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1314867

References:

[1] Lewandowskı W., Azoubıb J., and Klepczynskı W. J. “GPS: Primary Tool for Time Transfer”, Proceedings of the IEEE, vol. 87, no. 1, January 1999.
[2] Giorgi G., Narduzzi C. “Performance Analysis of Kalman-Filter-Based Clock Synchronization in IEEE 1588 Networks”, IEEE Transactıons on Instrumentatıon and Measurement, vol. 60, no. 8, August 2011.
[3] Zhu S., Xu Y., Zhang J., Wang Y., “The Study ard Analysis of joint Adaptive Clock Recovery,Mechanism for TDMOIP”, IEEE International Conference on Networking, Sensing and Control, 2008.
[4] Aweya J., Ouellette M., Montuno D. Y., Felske K., “Circuit emulation services over Ethernet—Part 1: Clock synchronization using timestamps”, Internatıonal Journal Of Network Management, 14: 29–44, 2004.I. S. Jacobs and C. P. Bean, “Fine particles, thin films and exchange anisotropy,” in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New York: Academic, 1963, pp. 271–350.
[5] Trump T., “Estimatıon Of Clock Skew In Telephony Over Packet Swıtched Networks” IEEE International Conference on Acoustics, Speech, and Signal Processing, 2000.
[6] Umayabashi, M., Cui Z., Takagi K., Iwata A., “Proposal of High Stable Clock Recovery Method Based on Queuing-Delay Measurement Scheme for TDM PWE3 over PSN”, OSA/OFC/NFOEC, 2009
[7] Shen Y., Ge N., “Dual-Stage Clock Recovery for TDM in Packet Networks”, Proceedings ofISCIT, 2005.
[8] Shen G., Nizam M. H. M., Liu E., Gui L., Xu X., “Fast and Accurate Clock Recovery in Packet Switched Networks”, National 973 program, 2004
[9] Shuai L., Yueming L., Yuefeng J., “A Buffer Level Clock Recovery Based On Least Mean Squares In Ptn” IC-BNMT, 2009
[10] ITU-T Rec. G.823, The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 2000.