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Impact of Process Variations on the Vertical Silicon Nanowire Tunneling FET (TFET)

Authors: Z. X. Chen, D. -L. Kwong, T. S. Phua, X. P. Wang, G. -Q. Lo

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device Simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1087776

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References:


[1] C. Hu, "Green transistor as a solution to the IC power crisis," in 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, pp. 16-20.
[2] W. M. Reddick and G. A. J. Amaratunga, "Silicon surface tunnel transistor," Applied Physics Letters, vol. 67, no. 4, pp. 494-496, 1995.
[3] M. Born, et al., "Tunnel FET: A CMOS Device for high Temperature Applications," in 25th International Conference on Microelectronics, 2006, pp. 124-127.
[4] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field- Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, 2007.
[5] K. Boucart and A. M. Ionescu, "Double-Gate Tunnel FET With High-κ Gate Dielectric," IEEE Transactions on Electron Devices, vol. 54, no. 7, pp. 1725-1733, 2007.
[6] P.-F. Wang, et al., "Complementary tunneling transistor for low power application," Solid-State Electronics, vol. 48, no. 12, pp. 2281-2286, 2004.
[7] N. B. Patel, A. Ramesha, and S. Mahapatra, "Performance enhancement of the tunnel field effect transistor using a SiGe source," in International Workshop on Physics of Semiconductor Devices, 2007, pp. 111-114.
[8] K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering," IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 909-917, 2005.
[9] T. Krishnamohan, D. Kim, S. Raghunathan, and K. C. Saraswat, "Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive current and <60mV/dec subthreshold slope," in International Electron Device Meeting, 2008, pp. 947-949.
[10] O. M. Nayfeh, et al., "Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Letters, vol. 29, no. 9, pp. 1074-1077, 2008.
[11] A. S. Verhulst, et al., "Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates," IEEE Electron Device Letters, vol. 29, no. 12, pp. 1398-1401, 2008.
[12] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction," Applied Physics Letters, vol. 91, no. 24, p. 243505, 2007.
[13] P.-F. Wang, T. Nirschl, D. Schmitt-Landsiedel, and W. Hansch, "Simulation of the Esaki-tunneling FET," Solid-State Electronics, vol. 47, no. 7, pp. 1187-1192, 2003.
[14] S. O. Koswatta, D. E. Nikonov, and M. S. Lundstrom, "Computational study of carbon nanotube p-i-n tunnel FETs," in IEEE International Electron Devices Meeting, 2005, pp. 518-521.
[15] N. Singh, et al., "Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance," in International Electron Devices Meeting, 2006, pp. 1-4.
[16] N. Singh, et al., "High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices," IEEE Electron Device Letters, vol. 27, no. 5, pp. 383-386, 2006.
[17] N. Singh, et al., "Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications," IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3107-3118, 2008.
[18] J. Goldberger, A. I. Hochbaum, R. Fan, and P. Yang, "Silicon Vertically Integrated Nanowire Field Effect Transistors," Nano Letters, vol. 6, no. 5, pp. 973-977, 2006.
[19] B. Yang, et al., "Vertical Silicon-Nanowire Formation and Gate-All- Around MOSFET," IEEE Electron Device Letters, vol. 29, no. 7, pp. 791-794, 2008.
[20] E. O. Kane, "Zener tunneling in semiconductors," Journal of Physics and Chemistry of Solids, vol. 12, no. 2, pp. 181-188, 1960.