Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30526
Single Event Transient Tolerance Analysis in 8051 Microprocessor Using Scan Chain

Authors: Jong Tae Kim, Jong Kang Park, Jun Sung Go


As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: scan chain, single event transient, soft error

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 899


[1] R.C. Baumann. “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Transactions on Device and Materials Reliability, 5(3):305–316, 2005.
[2] Phillip P. Shivani, “Fault-Tolerant Computing for Radiation Environments,” Stanford University, 2001.
[3] E. Ibe, H. Taniguchi, Y. Yahagi, K.-i. Shimbo, and T. Toba, “Impact of scaling on neutron-induced soft error in srams from a 250 nm to a 22 nm design rule,” IEEE Transactions on Electron Devices, 57(7):1527–1538, 2010.
[4] Varadan Savulimedu Veeravalli, Andreas Steininger, “Performance of Radiation Hardening Techniques under Voltage and Temperature Variations,” Aerospace Conference, 2013 IEEE
[5] Yihua Chen., Minghua Tang, Shaoan Yan, Wanli Zhang, Youlin Yin, “Radiation hardened by design techniques to mitigating P-hit single event transient,” Nanoelectronics Conference (INEC), 2016 IEEE International
[6] P. Adell, R.D. Schrimpf, H.J. Barnaby, R. Marec, C. Chatry, P. Calvel, C. Barillot, O. Mion, “Analysis of single-event transients in analog circuits,” IEEE Transactions on Nuclear Science Volume: 47, Issue: 6, Dec 2000
[7] S. Buchner, M. Baze, D. Brown, D. McMorrow, J. Melinger, “Comparison of error rates in combinatorial and sequential logic,” IEEE Transactions on Nuclear Science, vol.44, pp. 2209–2216, Dec. 1997.
[8] Mehdi Saremi, Aymeric Privat, Hugh J. Barnaby, and Lawrence T. Clark, “Physically Based Predictive Model for Single Event Transients in CMOS Gates,” IEEE Transactions on Electron Devices, Vol. 63, No. 6, June 2016.
[9] P. Maillard, “Single event transient modeling and mitigation techniques for mixed-signal delay locked loop(DLL) and clock circuits,” Vanderbilt University Electrical Engineering, 2014.
[10] Joep Aerts, E. J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based ICs,” International Test Conference, 1998.
[11] G. G. Oh, S. N. Seo, J. Y. Jang, “SCAN Failure Analysis Based on Statistical Method,” Korea Test Association, June 2007.