Search results for: bootloader

Authors: Jungho Moon, Lae Jeong Park

Abstract:

This paper introduces the development of a firmware downloader for students attending microcontroller-related courses taught by the authors In the courses, AVR microcontroller experiment kits are used for programming exercise and the AVR microcontroller is programmed through a serial communication interface using a bootloader preinstalled on it. To use the bootloader, a matching firmware downloader that runs on a host computer and communicates with the bootloader is also required. When firmware downloading is completed, the serial port used for it needs to be closed. If the downloaded firmware uses serial communication, the serial port needs to be reopened in a serial terminal. As a result, the programmer of the AVR board switches from the downloader program and the serial terminal and vice versa. It is a simple task but quite a hassle to do each time new firmware needs downloading. To provide a more convenient programming environment for the courses, the authors developed a downloader program that includes a serial terminal in it. The program operates in downloader or terminal mode and the mode switching is performed automatically; therefore manual mode switching is not necessary. The feature provides a more convenient development environment by eliminating the need for manual mode switching each time firmware downloading is required.

Keywords: bootloader, firmware downloader, microcontroller, serial communication

Procedia PDF Downloads 194

Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: hardware scheduler, nMPRA processor, real-time systems, scheduling methods

Procedia PDF Downloads 267